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Diffstat (limited to 'demo/demo_c_0.asm')
| -rw-r--r-- | demo/demo_c_0.asm | 529 |
1 files changed, 529 insertions, 0 deletions
diff --git a/demo/demo_c_0.asm b/demo/demo_c_0.asm new file mode 100644 index 0000000..8338791 --- /dev/null +++ b/demo/demo_c_0.asm @@ -0,0 +1,529 @@ +;-------------------------------------------------------- +; File Created by SDCC : free open source ANSI-C Compiler +; Version 2.9.0 #5416 (Oct 6 2009) (UNIX) +; This file was generated Tue Oct 27 23:03:10 2009 +;-------------------------------------------------------- + .module demo_c_0 + .optsdcc -mmcs51 --model-small + +;-------------------------------------------------------- +; Public variables in this module +;-------------------------------------------------------- + .globl _main + .globl _someFunction + .globl _CY + .globl _AC + .globl _F0 + .globl _RS1 + .globl _RS0 + .globl _OV + .globl _FL + .globl _P + .globl _PS + .globl _PT1 + .globl _PX1 + .globl _PT0 + .globl _PX0 + .globl _RD + .globl _WR + .globl _T1 + .globl _T0 + .globl _INT1 + .globl _INT0 + .globl _TXD + .globl _RXD + .globl _P3_7 + .globl _P3_6 + .globl _P3_5 + .globl _P3_4 + .globl _P3_3 + .globl _P3_2 + .globl _P3_1 + .globl _P3_0 + .globl _EA + .globl _ES + .globl _ET1 + .globl _EX1 + .globl _ET0 + .globl _EX0 + .globl _P2_7 + .globl _P2_6 + .globl _P2_5 + .globl _P2_4 + .globl _P2_3 + .globl _P2_2 + .globl _P2_1 + .globl _P2_0 + .globl _SM0 + .globl _SM1 + .globl _SM2 + .globl _REN + .globl _TB8 + .globl _RB8 + .globl _TI + .globl _RI + .globl _P1_7 + .globl _P1_6 + .globl _P1_5 + .globl _P1_4 + .globl _P1_3 + .globl _P1_2 + .globl _P1_1 + .globl _P1_0 + .globl _TF1 + .globl _TR1 + .globl _TF0 + .globl _TR0 + .globl _IE1 + .globl _IT1 + .globl _IE0 + .globl _IT0 + .globl _P0_7 + .globl _P0_6 + .globl _P0_5 + .globl _P0_4 + .globl _P0_3 + .globl _P0_2 + .globl _P0_1 + .globl _P0_0 + .globl _B + .globl _A + .globl _ACC + .globl _PSW + .globl _IP + .globl _P3 + .globl _IE + .globl _P2 + .globl _SBUF + .globl _SCON + .globl _P1 + .globl _TH1 + .globl _TH0 + .globl _TL1 + .globl _TL0 + .globl _TMOD + .globl _TCON + .globl _PCON + .globl _DPH + .globl _DPL + .globl _SP + .globl _P0 + .globl _i + .globl _some_variable +;-------------------------------------------------------- +; special function registers +;-------------------------------------------------------- + .area RSEG (DATA) +G$P0$0$0 == 0x0080 +_P0 = 0x0080 +G$SP$0$0 == 0x0081 +_SP = 0x0081 +G$DPL$0$0 == 0x0082 +_DPL = 0x0082 +G$DPH$0$0 == 0x0083 +_DPH = 0x0083 +G$PCON$0$0 == 0x0087 +_PCON = 0x0087 +G$TCON$0$0 == 0x0088 +_TCON = 0x0088 +G$TMOD$0$0 == 0x0089 +_TMOD = 0x0089 +G$TL0$0$0 == 0x008a +_TL0 = 0x008a +G$TL1$0$0 == 0x008b +_TL1 = 0x008b +G$TH0$0$0 == 0x008c +_TH0 = 0x008c +G$TH1$0$0 == 0x008d +_TH1 = 0x008d +G$P1$0$0 == 0x0090 +_P1 = 0x0090 +G$SCON$0$0 == 0x0098 +_SCON = 0x0098 +G$SBUF$0$0 == 0x0099 +_SBUF = 0x0099 +G$P2$0$0 == 0x00a0 +_P2 = 0x00a0 +G$IE$0$0 == 0x00a8 +_IE = 0x00a8 +G$P3$0$0 == 0x00b0 +_P3 = 0x00b0 +G$IP$0$0 == 0x00b8 +_IP = 0x00b8 +G$PSW$0$0 == 0x00d0 +_PSW = 0x00d0 +G$ACC$0$0 == 0x00e0 +_ACC = 0x00e0 +G$A$0$0 == 0x00e0 +_A = 0x00e0 +G$B$0$0 == 0x00f0 +_B = 0x00f0 +;-------------------------------------------------------- +; special function bits +;-------------------------------------------------------- + .area RSEG (DATA) +G$P0_0$0$0 == 0x0080 +_P0_0 = 0x0080 +G$P0_1$0$0 == 0x0081 +_P0_1 = 0x0081 +G$P0_2$0$0 == 0x0082 +_P0_2 = 0x0082 +G$P0_3$0$0 == 0x0083 +_P0_3 = 0x0083 +G$P0_4$0$0 == 0x0084 +_P0_4 = 0x0084 +G$P0_5$0$0 == 0x0085 +_P0_5 = 0x0085 +G$P0_6$0$0 == 0x0086 +_P0_6 = 0x0086 +G$P0_7$0$0 == 0x0087 +_P0_7 = 0x0087 +G$IT0$0$0 == 0x0088 +_IT0 = 0x0088 +G$IE0$0$0 == 0x0089 +_IE0 = 0x0089 +G$IT1$0$0 == 0x008a +_IT1 = 0x008a +G$IE1$0$0 == 0x008b +_IE1 = 0x008b +G$TR0$0$0 == 0x008c +_TR0 = 0x008c +G$TF0$0$0 == 0x008d +_TF0 = 0x008d +G$TR1$0$0 == 0x008e +_TR1 = 0x008e +G$TF1$0$0 == 0x008f +_TF1 = 0x008f +G$P1_0$0$0 == 0x0090 +_P1_0 = 0x0090 +G$P1_1$0$0 == 0x0091 +_P1_1 = 0x0091 +G$P1_2$0$0 == 0x0092 +_P1_2 = 0x0092 +G$P1_3$0$0 == 0x0093 +_P1_3 = 0x0093 +G$P1_4$0$0 == 0x0094 +_P1_4 = 0x0094 +G$P1_5$0$0 == 0x0095 +_P1_5 = 0x0095 +G$P1_6$0$0 == 0x0096 +_P1_6 = 0x0096 +G$P1_7$0$0 == 0x0097 +_P1_7 = 0x0097 +G$RI$0$0 == 0x0098 +_RI = 0x0098 +G$TI$0$0 == 0x0099 +_TI = 0x0099 +G$RB8$0$0 == 0x009a +_RB8 = 0x009a +G$TB8$0$0 == 0x009b +_TB8 = 0x009b +G$REN$0$0 == 0x009c +_REN = 0x009c +G$SM2$0$0 == 0x009d +_SM2 = 0x009d +G$SM1$0$0 == 0x009e +_SM1 = 0x009e +G$SM0$0$0 == 0x009f +_SM0 = 0x009f +G$P2_0$0$0 == 0x00a0 +_P2_0 = 0x00a0 +G$P2_1$0$0 == 0x00a1 +_P2_1 = 0x00a1 +G$P2_2$0$0 == 0x00a2 +_P2_2 = 0x00a2 +G$P2_3$0$0 == 0x00a3 +_P2_3 = 0x00a3 +G$P2_4$0$0 == 0x00a4 +_P2_4 = 0x00a4 +G$P2_5$0$0 == 0x00a5 +_P2_5 = 0x00a5 +G$P2_6$0$0 == 0x00a6 +_P2_6 = 0x00a6 +G$P2_7$0$0 == 0x00a7 +_P2_7 = 0x00a7 +G$EX0$0$0 == 0x00a8 +_EX0 = 0x00a8 +G$ET0$0$0 == 0x00a9 +_ET0 = 0x00a9 +G$EX1$0$0 == 0x00aa +_EX1 = 0x00aa +G$ET1$0$0 == 0x00ab +_ET1 = 0x00ab +G$ES$0$0 == 0x00ac +_ES = 0x00ac +G$EA$0$0 == 0x00af +_EA = 0x00af +G$P3_0$0$0 == 0x00b0 +_P3_0 = 0x00b0 +G$P3_1$0$0 == 0x00b1 +_P3_1 = 0x00b1 +G$P3_2$0$0 == 0x00b2 +_P3_2 = 0x00b2 +G$P3_3$0$0 == 0x00b3 +_P3_3 = 0x00b3 +G$P3_4$0$0 == 0x00b4 +_P3_4 = 0x00b4 +G$P3_5$0$0 == 0x00b5 +_P3_5 = 0x00b5 +G$P3_6$0$0 == 0x00b6 +_P3_6 = 0x00b6 +G$P3_7$0$0 == 0x00b7 +_P3_7 = 0x00b7 +G$RXD$0$0 == 0x00b0 +_RXD = 0x00b0 +G$TXD$0$0 == 0x00b1 +_TXD = 0x00b1 +G$INT0$0$0 == 0x00b2 +_INT0 = 0x00b2 +G$INT1$0$0 == 0x00b3 +_INT1 = 0x00b3 +G$T0$0$0 == 0x00b4 +_T0 = 0x00b4 +G$T1$0$0 == 0x00b5 +_T1 = 0x00b5 +G$WR$0$0 == 0x00b6 +_WR = 0x00b6 +G$RD$0$0 == 0x00b7 +_RD = 0x00b7 +G$PX0$0$0 == 0x00b8 +_PX0 = 0x00b8 +G$PT0$0$0 == 0x00b9 +_PT0 = 0x00b9 +G$PX1$0$0 == 0x00ba +_PX1 = 0x00ba +G$PT1$0$0 == 0x00bb +_PT1 = 0x00bb +G$PS$0$0 == 0x00bc +_PS = 0x00bc +G$P$0$0 == 0x00d0 +_P = 0x00d0 +G$FL$0$0 == 0x00d1 +_FL = 0x00d1 +G$OV$0$0 == 0x00d2 +_OV = 0x00d2 +G$RS0$0$0 == 0x00d3 +_RS0 = 0x00d3 +G$RS1$0$0 == 0x00d4 +_RS1 = 0x00d4 +G$F0$0$0 == 0x00d5 +_F0 = 0x00d5 +G$AC$0$0 == 0x00d6 +_AC = 0x00d6 +G$CY$0$0 == 0x00d7 +_CY = 0x00d7 +;-------------------------------------------------------- +; overlayable register banks +;-------------------------------------------------------- + .area REG_BANK_0 (REL,OVR,DATA) + .ds 8 +;-------------------------------------------------------- +; internal ram data +;-------------------------------------------------------- + .area DSEG (DATA) +G$some_variable$0$0==. +_some_variable:: + .ds 4 +G$i$0$0==. +_i:: + .ds 2 +;-------------------------------------------------------- +; overlayable items in internal ram +;-------------------------------------------------------- + .area OSEG (OVR,DATA) +;-------------------------------------------------------- +; Stack segment in internal ram +;-------------------------------------------------------- + .area SSEG (DATA) +__start__stack: + .ds 1 + +;-------------------------------------------------------- +; indirectly addressable internal ram data +;-------------------------------------------------------- + .area ISEG (DATA) +;-------------------------------------------------------- +; absolute internal ram data +;-------------------------------------------------------- + .area IABS (ABS,DATA) + .area IABS (ABS,DATA) +;-------------------------------------------------------- +; bit data +;-------------------------------------------------------- + .area BSEG (BIT) +;-------------------------------------------------------- +; paged external ram data +;-------------------------------------------------------- + .area PSEG (PAG,XDATA) +;-------------------------------------------------------- +; external ram data +;-------------------------------------------------------- + .area XSEG (XDATA) +;-------------------------------------------------------- +; absolute external ram data +;-------------------------------------------------------- + .area XABS (ABS,XDATA) +;-------------------------------------------------------- +; external initialized ram data +;-------------------------------------------------------- + .area XISEG (XDATA) + .area HOME (CODE) + .area GSINIT0 (CODE) + .area GSINIT1 (CODE) + .area GSINIT2 (CODE) + .area GSINIT3 (CODE) + .area GSINIT4 (CODE) + .area GSINIT5 (CODE) + .area GSINIT (CODE) + .area GSFINAL (CODE) + .area CSEG (CODE) +;-------------------------------------------------------- +; interrupt vector +;-------------------------------------------------------- + .area HOME (CODE) +__interrupt_vect: + ljmp __sdcc_gsinit_startup +;-------------------------------------------------------- +; global & static initialisations +;-------------------------------------------------------- + .area HOME (CODE) + .area GSINIT (CODE) + .area GSFINAL (CODE) + .area GSINIT (CODE) + .globl __sdcc_gsinit_startup + .globl __sdcc_program_startup + .globl __start__stack + .globl __mcs51_genXINIT + .globl __mcs51_genXRAMCLEAR + .globl __mcs51_genRAMCLEAR + G$main$0$0 ==. + C$demo_c_0.c$10$1$1 ==. +; demo_c_0.c:10: unsigned long some_variable=0; ///< Documentation for this variable comes here + clr a + mov _some_variable,a + mov (_some_variable + 1),a + mov (_some_variable + 2),a + mov (_some_variable + 3),a + .area GSFINAL (CODE) + ljmp __sdcc_program_startup +;-------------------------------------------------------- +; Home +;-------------------------------------------------------- + .area HOME (CODE) + .area HOME (CODE) +__sdcc_program_startup: + lcall _main +; return from main will lock up + sjmp . +;-------------------------------------------------------- +; code +;-------------------------------------------------------- + .area CSEG (CODE) +;------------------------------------------------------------ +;Allocation info for local variables in function 'someFunction' +;------------------------------------------------------------ +;somevalue Allocated to registers r2 +;------------------------------------------------------------ + G$someFunction$0$0 ==. + C$demo_c_0.c$20$0$0 ==. +; demo_c_0.c:20: void someFunction(unsigned char somevalue) +; ----------------------------------------- +; function someFunction +; ----------------------------------------- +_someFunction: + ar2 = 0x02 + ar3 = 0x03 + ar4 = 0x04 + ar5 = 0x05 + ar6 = 0x06 + ar7 = 0x07 + ar0 = 0x00 + ar1 = 0x01 + mov r2,dpl + C$demo_c_0.c$23$1$1 ==. +; demo_c_0.c:23: P1=somevalue; + mov _P1,r2 + C$demo_c_0.c$24$1$1 ==. +; demo_c_0.c:24: P3=somevalue^0xFF; + mov a,#0xFF + xrl a,r2 + mov _P3,a + C$demo_c_0.c$25$1$1 ==. + XG$someFunction$0$0 ==. + ret +;------------------------------------------------------------ +;Allocation info for local variables in function 'main' +;------------------------------------------------------------ +;------------------------------------------------------------ + G$main$0$0 ==. + C$demo_c_0.c$28$1$1 ==. +; demo_c_0.c:28: int main() +; ----------------------------------------- +; function main +; ----------------------------------------- +_main: + C$demo_c_0.c$31$1$1 ==. +; demo_c_0.c:31: while(1) { +00102$: + C$demo_c_0.c$32$2$2 ==. +; demo_c_0.c:32: for(i=0; i<255; i++) { + clr a + mov _i,a + mov (_i + 1),a +00104$: + clr c + mov a,_i + subb a,#0xFF + mov a,(_i + 1) + xrl a,#0x80 + subb a,#0x80 + jnc 00107$ + C$demo_c_0.c$33$3$3 ==. +; demo_c_0.c:33: someFunction(i+2); + mov r2,_i + mov a,#0x02 + add a,r2 + mov dpl,a + lcall _someFunction + C$demo_c_0.c$34$3$3 ==. +; demo_c_0.c:34: some_variable++; + inc _some_variable + clr a + cjne a,_some_variable,00114$ + inc (_some_variable + 1) + cjne a,(_some_variable + 1),00114$ + inc (_some_variable + 2) + cjne a,(_some_variable + 2),00114$ + inc (_some_variable + 3) +00114$: + C$demo_c_0.c$32$2$2 ==. +; demo_c_0.c:32: for(i=0; i<255; i++) { + inc _i + clr a + cjne a,_i,00104$ + inc (_i + 1) + sjmp 00104$ +00107$: + C$demo_c_0.c$36$2$2 ==. +; demo_c_0.c:36: some_variable-=22; + mov a,_some_variable + add a,#0xea + mov _some_variable,a + mov a,(_some_variable + 1) + addc a,#0xff + mov (_some_variable + 1),a + mov a,(_some_variable + 2) + addc a,#0xff + mov (_some_variable + 2),a + mov a,(_some_variable + 3) + addc a,#0xff + mov (_some_variable + 3),a + C$demo_c_0.c$40$1$1 ==. +; demo_c_0.c:40: return 0; + C$demo_c_0.c$41$1$1 ==. + XG$main$0$0 ==. + sjmp 00102$ + .area CSEG (CODE) + .area CONST (CODE) + .area XINIT (CODE) + .area CABS (ABS,CODE) |