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-rw-r--r--[-rwxr-xr-x]lib/simulator/engine/engine_instructions.tcl184
1 files changed, 97 insertions, 87 deletions
diff --git a/lib/simulator/engine/engine_instructions.tcl b/lib/simulator/engine/engine_instructions.tcl
index d732414..19c45af 100755..100644
--- a/lib/simulator/engine/engine_instructions.tcl
+++ b/lib/simulator/engine/engine_instructions.tcl
@@ -2,7 +2,7 @@
# Part of MCU 8051 IDE ( http://mcu8051ide.sf.net )
############################################################################
-# Copyright (C) 2007-2009 by Martin Ošmera #
+# Copyright (C) 2007, 2008, 2009, 2010, 2011, 2012 by Martin Ošmera #
# martin.osmera@gmail.com #
# #
# This program is free software; you can redistribute it and#or modify #
@@ -21,6 +21,11 @@
# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. #
############################################################################
+# >>> File inclusion guard
+if { ! [ info exists _ENGINE_INSTRUCTIONS_TCL ] } {
+set _ENGINE_INSTRUCTIONS_TCL _
+# <<< File inclusion guard
+
# --------------------------------------------------------------------------
# DESCRIPTION
# Part of simulator engine functionality.
@@ -41,7 +46,7 @@ private method ins_acall {haddr laddr} {
stack_push [expr {($pc & 255)}]
stack_push [expr {($pc & 0xFF00) >> 8}]
- incr laddr [expr {$haddr << 8}]
+ incr laddr [expr {($haddr << 8) | $pc & 0x0f800}]
incr run_statistics(6)
$this subprograms_call 1 $pc $laddr
$this stack_monitor_set_last_values_as 1 2
@@ -70,7 +75,7 @@ private method ins_add_D {addr} {
}
if {$addr < 128} {
ins_add $ram($addr)
- } {
+ } else {
ins_add [read_sfr $addr]
}
}
@@ -83,7 +88,7 @@ private method ins_add_ID {addr} {
incr_pc 1
if {[check_address_validity I $addr]} {
alo_add [undefined_octet]
- } {
+ } else {
alo_add $ram($addr)
}
evaluate_sfr 224
@@ -111,7 +116,7 @@ private method ins_addc_D {addr} {
}
if {$addr < 128} {
ins_addc $ram($addr)
- } {
+ } else {
ins_addc [read_sfr $addr]
}
}
@@ -125,7 +130,7 @@ private method ins_addc_ID {addr} {
if {[check_address_validity I $addr]} {
alo_addc [undefined_octet]
return
- } {
+ } else {
alo_addc $ram($addr)
}
}
@@ -136,7 +141,7 @@ private method ins_addc_ID {addr} {
# @return void
private method ins_ajmp {haddr laddr} {
set time 2
- incr laddr [expr {$haddr << 8}]
+ incr laddr [expr {($haddr << 8) | $pc & 0x0f800}]
set pc $laddr
}
@@ -155,7 +160,7 @@ private method ins_anl {addr val} {
if {$sync_ena} {
$this Simulator_sync_reg $addr
}
- } {
+ } else {
set rmw_instruction 1
write_sfr $addr [expr {[read_sfr $addr] & $val}]
evaluate_sfr $addr
@@ -185,7 +190,7 @@ private method ins_anl_A_D {addr} {
if {$sync_ena} {
$this Simulator_sync_reg $addr
}
- } {
+ } else {
ins_anl_A [read_sfr $addr]
evaluate_sfr $addr
}
@@ -222,7 +227,7 @@ private method ins_anl_C_N {addr} {
set time 2
if {[check_address_validity B $addr]} {
setBit $symbol(C) [expr {rand() > 0.5}]
- } {
+ } else {
if {[getBit $addr]} {setBit $symbol(C) 0}
}
evaluate_bit $symbol(C)
@@ -235,10 +240,10 @@ private method ins_anl_C_N {addr} {
private method ins_cjne_AD {addr roff} {
if {[check_address_validity D $addr]} {
set val [undefined_octet]
- } {
+ } else {
if {$addr < 128} {
set val $ram($addr)
- } {
+ } else {
set val $sfr($addr)
}
}
@@ -254,15 +259,14 @@ private method ins_cjne {val0 val1 roff} {
set time 2
if {$val0 != $val1} {
- if {$val0 < $val1} {
- setBit $symbol(C) 1
- } {
- setBit $symbol(C) 0
- }
-
if {$roff > 127} {incr roff -256}
incr_pc $roff
}
+ if {$val0 < $val1} {
+ setBit $symbol(C) 1
+ } else {
+ setBit $symbol(C) 0
+ }
}
## Instruction: CJNE @Ri, ...
@@ -275,19 +279,18 @@ private method ins_cjne_ID {addr val1 roff} {
if {[check_address_validity I $addr]} {
set val0 [undefined_octet]
- } {
+ } else {
set val0 $ram($addr)
}
if {$val0 != $val1} {
- if {$val0 < $val1} {
- setBit $symbol(C) 1
- } {
- setBit $symbol(C) 0
- }
-
if {$roff > 127} {incr roff -256}
incr_pc $roff
}
+ if {$val0 < $val1} {
+ setBit $symbol(C) 1
+ } else {
+ setBit $symbol(C) 0
+ }
}
## Instruction: CLR
@@ -309,7 +312,7 @@ private method ins_clr {opr} {
setBit $symbol(C) 0
evaluate_bit $symbol(C)
# Some bit
- } {
+ } else {
if {[check_address_validity B $opr]} {return}
set rmw_instruction 1
setBit $opr 0
@@ -335,17 +338,17 @@ private method ins_cpl {opr} {
} elseif {$opr == {C}} {
if {[getBit $symbol(C)]} {
setBit $symbol(C) 0
- } {
+ } else {
setBit $symbol(C) 1
}
evaluate_bit $symbol(C)
# Some bit
- } {
+ } else {
if {[check_address_validity B $opr]} {return}
set rmw_instruction 1
if {[getBit $opr]} {
setBit $opr 0
- } {
+ } else {
setBit $opr 1
}
evaluate_bit $opr
@@ -423,7 +426,7 @@ private method ins_div {} {
setBit $symbol(OV) 1
set sfr(224) 0
set sfr($symbol(B)) 0
- } {
+ } else {
setBit $symbol(OV) 0
set A $sfr(224)
set sfr(224) [expr {$A / $sfr($symbol(B))}]
@@ -449,7 +452,7 @@ private method ins_djnz {addr roff} {
incr_pc $roff
}
evaluate_sfr $addr
- } {
+ } else {
if {$ram($addr) != 0} {
if {$roff > 127} {incr roff -256}
incr_pc $roff
@@ -517,7 +520,7 @@ private method ins_jb {addr roff} {
set time 2
if {[check_address_validity B $addr]} {
set val [expr {rand() > 0.5}]
- } {
+ } else {
set val [getBit $addr]
}
if {$val} {
@@ -534,7 +537,7 @@ private method ins_jnb {addr roff} {
set time 2
if {[check_address_validity B $addr]} {
set val [expr {rand() > 0.5}]
- } {
+ } else {
set val [getBit $addr]
}
if {!$val} {
@@ -552,7 +555,7 @@ private method ins_jbc {addr roff} {
set time 2
if {[check_address_validity B $addr]} {
set val [expr {rand() > 0.5}]
- } {
+ } else {
set val [getBit $addr]
}
if {$val} {
@@ -653,7 +656,7 @@ private method ins_mov {addr val} {
if {$sync_ena} {
$this Simulator_sync_reg $addr
}
- } {
+ } else {
write_sfr $addr $val
evaluate_sfr $addr
}
@@ -670,7 +673,7 @@ private method ins_mov_D {addr1 addr0} {
if {[check_address_validity D $addr0]} {return}
if {[check_address_validity D $addr1]} {
set val [undefined_octet]
- } {
+ } else {
if {$addr1 < 128} {
set val $ram($addr1)
} {
@@ -686,7 +689,7 @@ private method ins_mov_D {addr1 addr0} {
if {$sync_ena} {
$this Simulator_sync_reg $addr0
}
- } {
+ } else {
write_sfr $addr0 $val
evaluate_sfr $addr0
}
@@ -699,10 +702,10 @@ private method ins_mov_D {addr1 addr0} {
private method ins_mov_ID2 {addr0 addr1} {
if {[check_address_validity D $addr1]} {
ins_mov_ID0 $addr0 [undefined_octet]
- } {
+ } else {
if {$addr1 < 128} {
ins_mov_ID0 $addr0 $ram($addr1)
- } {
+ } else {
ins_mov_ID0 $addr0 [read_sfr $addr1]
}
}
@@ -720,7 +723,7 @@ private method ins_mov_ID1 {addr addr_id} {
if {[check_address_validity D $addr]} {return}
if {[check_address_validity I $addr_id]} {
set val [undefined_octet]
- } {
+ } else {
set val $ram($addr_id)
}
if {$addr < 128} {
@@ -731,7 +734,7 @@ private method ins_mov_ID1 {addr addr_id} {
if {$sync_ena} {
$this Simulator_sync_reg $addr
}
- } {
+ } else {
write_sfr $addr $val
evaluate_sfr $addr
}
@@ -788,7 +791,7 @@ private method ins_mov_Rx_ADDR {idx addr} {
}
if {$addr < 128} {
set ram($t_addr) $ram($addr)
- } {
+ } else {
set ram($t_addr) [read_sfr $addr]
}
@@ -806,21 +809,21 @@ private method ins_mov_bit {dest source} {
if {$dest == {C}} {
if {[check_address_validity B $source]} {
set val [expr {rand() < 0.5}]
- } {
+ } else {
set val [getBit $source]
}
if {$val} {
setBit $symbol(C) 1
- } {
+ } else {
setBit $symbol(C) 0
}
- } {
+ } else {
set rmw_instruction 1
incr time
if {[check_address_validity B $dest]} {return}
if {[getBit $symbol(C)]} {
setBit $dest 1
- } {
+ } else {
setBit $dest 0
}
}
@@ -837,7 +840,7 @@ private method ins_movc {arg} {
if {$arg == {DPTR}} {
set addr [expr {($sfr(224) + $sfr($symbol($DPL))) + ($sfr($symbol($DPH)) << 8)}]
# MOVC A, @A+PC
- } {
+ } else {
set addr $pc
incr addr $sfr(224)
}
@@ -853,7 +856,7 @@ private method ins_movc {arg} {
set sfr(224) [undefined_octet]
} elseif {$code($addr) != {}} {
set sfr(224) $code($addr)
- } {
+ } else {
set sfr(224) [undefined_octet]
}
@@ -885,14 +888,14 @@ private method ins_movx {opr0 opr1} {
if {$Saddr < $eram_size && !$controllers_conf(EXTRAM)} {
if {[check_address_validity E $Saddr]} {
set sfr(224) [undefined_octet]
- } {
+ } else {
set sfr(224) $eram($Saddr)
}
# Read from data EEPROM
} elseif {$Saddr < $eeprom_size && $controllers_conf(EEMEN)} {
if {[check_address_validity P $Saddr]} {
set sfr(224) [undefined_octet]
- } {
+ } else {
set complement_MSB 0
foreach reg $eeprom_prev {
if {$Saddr == [lindex $reg 0]} {
@@ -902,13 +905,13 @@ private method ins_movx {opr0 opr1} {
}
if {$complement_MSB} {
set sfr(224) [expr {$eeprom($Saddr) ^ 0x80}]
- } {
+ } else {
set sfr(224) $eeprom($Saddr)
}
}
# Read from external data memory
} else {
- if {$feature_avaliable(xram) && [$this pale_is_enabled]} {
+ if {$feature_available(xram) && [$this pale_is_enabled]} {
for {set i -3} {$i < 0} {incr i} {
if {!$controllers_conf(X2)} {
$this pale_WPBBL $PIN(RD) {X} $i
@@ -918,7 +921,7 @@ private method ins_movx {opr0 opr1} {
$this pale_WPBBL $PIN(RD) {X} $i
$this pale_WPBL 0 X $i
$this pale_WPBL 2 X $i
- } {
+ } else {
incr i
$this pale_WPBL 0 X [expr {int($i / 2)}]
$this pale_WPBL 2 X [expr {int($i / 2)}]
@@ -928,7 +931,7 @@ private method ins_movx {opr0 opr1} {
}
if {[check_address_validity X $Saddr]} {
set sfr(224) [undefined_octet]
- } {
+ } else {
set sfr(224) $xram($Saddr)
}
}
@@ -978,7 +981,7 @@ private method ins_movx {opr0 opr1} {
set eeprom_WR_ofs "0x$offset"
::X::eeprom_write_buffer_set_offset $eeprom_WR_ofs $this
- # Start EEPROM programing cycle
+ # Start EEPROM programming cycle
if {!$controllers_conf(EELD)} {
# Write data to data EEPROM
set eeprom_prev {}
@@ -993,7 +996,7 @@ private method ins_movx {opr0 opr1} {
set eeprom_WR_buff($i) {}
}
- # Clear write buffer hexeditor
+ # Clear write buffer hex editor
::X::eeprom_write_buffer_set_offset {} $this
::X::clear_eeprom_write_buffer $this
@@ -1017,7 +1020,7 @@ private method ins_movx {opr0 opr1} {
# Write to external data memory
} else {
- if {$feature_avaliable(xram) && [$this pale_is_enabled]} {
+ if {$feature_available(xram) && [$this pale_is_enabled]} {
for {set i -3} {$i < 0} {incr i} {
if {!$controllers_conf(X2)} {
$this pale_WPBBL $PIN(WR) {X} $i
@@ -1027,7 +1030,7 @@ private method ins_movx {opr0 opr1} {
$this pale_WPBBL $PIN(WR) {X} $i
$this pale_WPBL 0 X $i
$this pale_WPBL 2 X $i
- } {
+ } else {
incr i
$this pale_WPBL 0 X [expr {int($i / 2)}]
$this pale_WPBL 2 X [expr {int($i / 2)}]
@@ -1037,6 +1040,7 @@ private method ins_movx {opr0 opr1} {
}
if {[check_address_validity X $Daddr]} {return}
+ stepback_reg_change X $Daddr
set xram($Daddr) $sfr(224)
}
@@ -1062,7 +1066,7 @@ private method ins_mul {} {
if {$result > 255} {
set sfr(240) [expr {($result & 0xFF00) >> 8}]
setBit $symbol(OV) 1
- } {
+ } else {
set sfr(240) 0
setBit $symbol(OV) 0
}
@@ -1096,7 +1100,7 @@ private method ins_orl {addr val} {
if {$sync_ena} {
$this Simulator_sync_reg $addr
}
- } {
+ } else {
set rmw_instruction 1
write_sfr $addr [expr {[read_sfr $addr] | $val}]
evaluate_sfr $addr
@@ -1113,7 +1117,7 @@ private method ins_orl_D {addr0 addr1} {
ins_orl $addr0 [undefined_octet]
} elseif {$addr1 < 128} {
ins_orl $addr0 $ram($addr1)
- } {
+ } else {
ins_orl $addr0 [read_sfr $addr1]
}
}
@@ -1129,7 +1133,7 @@ private method ins_orl_ID {addr addr_id} {
if {[check_address_validity D $addr]} {return}
if {[check_address_validity I $addr_id]} {
set val [undefined_octet]
- } {
+ } else {
set val $ram($addr_id)
}
if {$addr < 128} {
@@ -1140,7 +1144,7 @@ private method ins_orl_ID {addr addr_id} {
if {$sync_ena} {
$this Simulator_sync_reg $addr
}
- } {
+ } else {
set rmw_instruction 1
write_sfr $addr [expr {[read_sfr $addr] | $val}]
evaluate_sfr $addr
@@ -1157,7 +1161,7 @@ private method ins_orl_not_bit {addr} {
setBit $symbol(C) [expr {rand() < 0.5}]
} elseif {[getBit $symbol(C)] || ![getBit $addr]} {
setBit $symbol(C) 1
- } {
+ } else {
setBit $symbol(C) 0
}
}
@@ -1172,7 +1176,7 @@ private method ins_orl_bit {addr} {
setBit $symbol(C) [expr {rand() < 0.5}]
} elseif {[getBit $symbol(C)] || [getBit $addr]} {
setBit $symbol(C) 1
- } {
+ } else {
setBit $symbol(C) 0
}
}
@@ -1193,7 +1197,7 @@ private method ins_pop {addr} {
if {$sync_ena} {
$this Simulator_sync_reg $addr
}
- } {
+ } else {
write_sfr $addr [stack_pop]
evaluate_sfr $addr
}
@@ -1243,13 +1247,15 @@ private method ins_reti {} {
$this interrupt_monitor_reti [lindex $inter_in_p_flags end]
set interrupts_in_progress [lreplace $interrupts_in_progress end end]
set inter_in_p_flags [lreplace $inter_in_p_flags end end]
- if {[llength $interrupts_in_progress]} {
- set vector [format %X [intr2vector [lindex $interrupts_in_progress end]]]
- simulator_Sbar [mc "Interrupt at vector 0x%s " $vector] 1 $this
- } {
- simulator_Sbar {} 0 $this
+ if {$::GUI_AVAILABLE} {
+ if {[llength $interrupts_in_progress]} {
+ set vector [format %X [intr2vector [lindex $interrupts_in_progress end]]]
+ simulator_Sbar [mc "Interrupt at vector 0x%s " $vector] 1 $this
+ } else {
+ simulator_Sbar {} 0 $this
+ }
}
- } {
+ } else {
$this simulator_invalid_reti_dlg $pc $Line($pc)
}
@@ -1295,7 +1301,7 @@ private method ins_rlc {} {
if {$sfr(224) > 255} {
incr sfr(224) -256
setBit $symbol(C) 1
- } {
+ } else {
setBit $symbol(C) 0
}
@@ -1313,7 +1319,7 @@ private method ins_rr {} {
}
if {[expr {$sfr(224) % 2}]} {
set C 1
- } {
+ } else {
set C 0
}
@@ -1335,7 +1341,7 @@ private method ins_rrc {} {
}
if {[expr {$sfr(224) % 2}]} {
set C 1
- } {
+ } else {
set C 0
}
@@ -1347,7 +1353,7 @@ private method ins_rrc {} {
if {$C} {
setBit $symbol(C) 1
- } {
+ } else {
setBit $symbol(C) 0
}
@@ -1363,7 +1369,7 @@ private method ins_setb {opr} {
if {$opr == {C}} {
setBit $symbol(C) 1
- } {
+ } else {
if {[check_address_validity B $opr]} {return}
set rmw_instruction 1
setBit $opr 1
@@ -1399,7 +1405,7 @@ private method ins_subb_D {addr} {
ins_subb [undefined_octet]
} elseif {$addr < 128} {
ins_subb $ram($addr)
- } {
+ } else {
ins_subb $sfr($addr)
}
}
@@ -1412,7 +1418,7 @@ private method ins_subb_ID {addr} {
incr_pc 1
if {[check_address_validity I $addr]} {
ins_subb [undefined_octet]
- } {
+ } else {
alo_subb $ram($addr)
}
evaluate_sfr 224
@@ -1457,7 +1463,7 @@ private method ins_xch {addr} {
if {$sync_ena} {
$this Simulator_sync_reg $addr
}
- } {
+ } else {
set sfr(224) [read_sfr $addr]
write_sfr $addr $A
evaluate_sfr $addr
@@ -1499,14 +1505,14 @@ private method ins_xchd {addr} {
set val [undefined_octet]
} elseif {$addr < 128} {
set val $ram($addr)
- } {
+ } else {
set val $sfr($addr)
}
if {${::Simulator::reverse_run_steps}} {
stepback_reg_change S 224
if {$addr < 128} {
stepback_reg_change I $addr
- } {
+ } else {
stepback_reg_change S $addr
}
}
@@ -1518,7 +1524,7 @@ private method ins_xchd {addr} {
set val [expr {($val & 240) + $nibble0}]
if {$addr < 128} {
set ram($addr) $val
- } {
+ } else {
set sfr($addr) $val
}
@@ -1545,7 +1551,7 @@ private method ins_xrl {addr val} {
if {$sync_ena} {
$this Simulator_sync_reg $addr
}
- } {
+ } else {
set rmw_instruction 1
write_sfr $addr [expr {[read_sfr $addr] ^ $val}]
evaluate_sfr $addr
@@ -1561,7 +1567,7 @@ private method ins_xrl_D {addr0 addr1} {
ins_xrl $addr0 [undefined_octet]
} elseif {$addr1 < 128} {
ins_xrl $addr0 $ram($addr1)
- } {
+ } else {
ins_xrl $addr0 [read_sfr $addr1]
}
}
@@ -1577,7 +1583,7 @@ private method ins_xrl_ID {addr addr_id} {
if {[check_address_validity I $addr_id]} {
set val [undefined_octet]
- } {
+ } else {
set val $ram($addr_id)
}
if {$addr < 128} {
@@ -1588,9 +1594,13 @@ private method ins_xrl_ID {addr addr_id} {
if {$sync_ena} {
$this Simulator_sync_reg $addr
}
- } {
+ } else {
set rmw_instruction 1
write_sfr $addr [expr {[read_sfr $addr] ^ $val}]
evaluate_sfr $addr
}
}
+
+# >>> File inclusion guard
+}
+# <<< File inclusion guard
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-25 12:45:08 +0000