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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-09-30 14:37:12 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-09-30 20:48:54 +0200 |
| commit | e42d616eb106c112b1610becd33e0767d35a1a03 (patch) | |
| tree | 8c3d4533a9eea5f2cc55cfa53202375738282c04 | |
| parent | 8dc65f673411559f06f975763085e828eea2cdeb (diff) | |
Remove use of reserved Python keyword 'async' from code
Gbp-Pq: Name 0001-Remove-use-of-reserved-Python-keyword-async-from-cod.patch
| -rw-r--r-- | myhdl/_always_seq.py | 8 | ||||
| -rw-r--r-- | myhdl/conversion/_toVHDL.py | 10 |
2 files changed, 9 insertions, 9 deletions
diff --git a/myhdl/_always_seq.py b/myhdl/_always_seq.py index 056279c..90de53c 100644 --- a/myhdl/_always_seq.py +++ b/myhdl/_always_seq.py @@ -45,7 +45,7 @@ _error.EmbeddedFunction = "embedded functions in always_seq function not support class ResetSignal(_Signal): - def __init__(self, val, active, async): + def __init__(self, val, active, async1): """ Construct a ResetSignal. This is to be used in conjunction with the always_seq decorator, @@ -53,7 +53,7 @@ class ResetSignal(_Signal): """ _Signal.__init__(self, bool(val)) self.active = bool(active) - self.async = async + self.async1 = async1 def always_seq(edge, reset): @@ -91,8 +91,8 @@ class _AlwaysSeq(_Always): if reset is not None: self.genfunc = self.genfunc_reset active = self.reset.active - async = self.reset.async - if async: + async1 = self.reset.async1 + if async1: if active: senslist.append(reset.posedge) else: diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 9aeeeb1..c460610 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -1838,12 +1838,12 @@ class _ConvertAlwaysSeqVisitor(_ConvertVisitor): senslist = self.tree.senslist edge = senslist[0] reset = self.tree.reset - async = reset is not None and reset.async + async1 = reset is not None and reset.async1 sigregs = self.tree.sigregs varregs = self.tree.varregs self.write("%s: process (" % self.tree.name) self.write(edge.sig) - if async: + if async1: self.write(', ') self.write(reset) self.write(") is") @@ -1853,7 +1853,7 @@ class _ConvertAlwaysSeqVisitor(_ConvertVisitor): self.writeline() self.write("begin") self.indent() - if not async: + if not async1: self.writeline() self.write("if %s then" % edge._toVHDL()) self.indent() @@ -1870,7 +1870,7 @@ class _ConvertAlwaysSeqVisitor(_ConvertVisitor): self.write("%s := %s;" % (n, _convertInitVal(reg, init))) self.dedent() self.writeline() - if async: + if async1: self.write("elsif %s then" % edge._toVHDL()) else: self.write("else") @@ -1881,7 +1881,7 @@ class _ConvertAlwaysSeqVisitor(_ConvertVisitor): self.writeline() self.write("end if;") self.dedent() - if not async: + if not async1: self.writeline() self.write("end if;") self.dedent() |