* EE 307 CMOS NAND Gates for F04 MoHAT Project
*
Vdd 1 0 2.5
VinA 2A 0 PULSE(0 2.5 10ns 0.25ns 0.25ns 29.5ns 40ns)
VinB 2B 0 PULSE(0 2.5 0ns 0.25ns 0.25ns 19.5ns 30ns)
R2 2A 20A 1n
R3 2B 20B 1n
* Standard NAND
MPA 3 2A 1 1 PMOD1
MPB 3 2B 1 1 PMOD1
MNA 3 2A 4 0 NMOD1
MNB 4 2B 0 0 NMOD1
CL1 3 0 10p
* Symmetrical NAND
MPA2 30 20A 1 1 PMOD1
MPB2 30 20B 1 1 PMOD1
MNA1 30 20A 40 0 NMOD1
MNB1 40 20B 0 0 NMOD1
MNB2 30 20B 50 0 NMOD1
MNA2 50 20A 0 0 NMOD1
CL2 30 0 10p
.MODEL NMOD1 NMOS (L=1U W=50U KP=200U GAMMA=0.9 phi=0.6 lambda=0.02 VTO=0.7)
.MODEL PMOD1 PMOS (L=1U W=50U KP=100U GAMMA=0.9 phi=0.6 lambda=0.02 VTO=-0.7)


.TRAN 0.0 50ns 0ns 20ps

.PRINT TRAN V(1) V(2A) V(2B) V(20A) V(20B) V(3) V(4) V(30) V(40) V(50)

.Probe

.END