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authorKiwamu Okabe <kiwamu@debian.or.jp>2016-12-07 21:45:07 +0000
committerKiwamu Okabe <kiwamu@debian.or.jp>2016-12-07 21:45:07 +0000
commit8246a055d7773ff0990e009757392f37c26982ab (patch)
tree81460f6588cb9efaed28455e1eb0999f97e9c4fd
Import verilog-mode_20161124.fd230e6.orig.tar.gz
[dgit import orig verilog-mode_20161124.fd230e6.orig.tar.gz]
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723 files changed, 43190 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..e4a30c8
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,19 @@
+.timestamps
+ASSIGNMENT.doc
+ChangeLog
+ChangeLog.txt
+e
+emacs-version.h
+gnu22
+gnuhead
+gnutrunk
+mmencoded_verilog-mode
+skip_for_xemacs
+verilog-mode-gnu-want.el
+verilog-mode-tognu.el
+verilog-mode.elc
+verilog.info
+x
+*.elc
+*.old
+*.new
diff --git a/0test.el b/0test.el
new file mode 100644
index 0000000..0ef230d
--- /dev/null
+++ b/0test.el
@@ -0,0 +1,212 @@
+;; DESCRIPTION: Run verilog-mode tests, as part of "make test"
+;;
+;; Copyright 2008-2013 by Michael McNamara and Wilson Snyder. This package
+;; is free software; you can redistribute it and/or modify it under the
+;; terms of either the GNU Lesser General Public License or the Perl
+;; Artistic License.
+;;
+;; VERILOG_MODE_DEBUG=1 # Enable verilog-debug
+;; VERILOG_MODE_NO_INDENTS=1 # Disable indent checks
+;; VERILOG_MODE_TEST_FILE=filename.v # Run only specified test
+;; VERILOG_MODE_START_FILE=filename.v # Start at specified test
+;; VERILOG_MODE_THREAD=#of# # Multithreaded testing
+;; VERILOG_MODE_PROFILE=1 # Profile - see batch_prof.el
+;; HARNESS_UPDATE_GOLDEN=1 # Update golden reference files
+
+(defvar diff-flags "-u")
+(defvar vl-threading (and (not (getenv "VERILOG_MODE_TEST_FILE"))
+ (getenv "VERILOG_MODE_THREAD")))
+
+(defun global-replace-regexp (from to)
+ (goto-char (point-min))
+ (while (re-search-forward from nil t)
+ (replace-match to nil nil)))
+
+(defun verilog-test-file (file temp-file)
+ (save-excursion
+ (message (concat file ": finding..."))
+ (find-file (concat "tests/" file))
+ (verilog-mode)
+ (message (concat file ": deleting indent..."))
+ (global-replace-regexp "[ \t]+$" "")
+
+ (message (concat file ": deleting autos..."))
+ (verilog-delete-auto)
+
+ (cond
+ ((string-match "^inject_" file)
+ (message (concat file ": testing inject-auto..."))
+ (verilog-inject-auto))
+ (t
+ (message (concat file ": testing auto..."))
+ (verilog-auto)))
+ (message (concat file ": auto OK..."))
+
+ (when (string-match "^label_" file)
+ (message (concat file ": testing auto labeling of begin/end..."))
+ (verilog-label-be))
+
+ (unless (getenv "VERILOG_MODE_NO_INDENTS")
+ (verilog-test-indent-buffer file)
+
+ (untabify (point-min) (point-max))
+ )
+ (write-file (concat "../" temp-file))
+ (kill-buffer nil))
+ ;;
+ (vl-diff-file (concat "tests_ok/" file) temp-file))
+
+(defun verilog-test-indent-buffer (file )
+ (interactive)
+ (message (concat file ": testing indent..."))
+ (save-excursion
+ (goto-char (point-min))
+ (let* ((ln 0))
+ (while (not (eobp))
+ ;;(message (format "%d" ln))
+ ;;(message (format "%s : %d - indent" file ln))
+ (electric-verilog-tab)
+ ;;(message (format "%s : %d - pretty-expr" file ln))
+ (verilog-pretty-expr t )
+ ;;(message (format "%s : %d - pretty-declaration" file ln))
+ (verilog-pretty-declarations t)
+ (forward-line 1)
+ (setq ln (1+ ln))
+ )
+ (message (format "Indented %d lines" ln))
+ ))
+ (message (concat file ": indents OK...")))
+
+(defun vl-diff-file (golden-file temp-file)
+ (message (concat golden-file ": running diff of " golden-file " and " temp-file ))
+ (with-temp-buffer
+ (let* ((status
+ (call-process "diff" nil t t diff-flags "--label" "GOLDEN_REFERENCE" golden-file "--label" "CURRENT_BEHAVIOR" temp-file )))
+ (cond ((and (not (equal status 0))
+ (getenv "HARNESS_UPDATE_GOLDEN"))
+ (message "***HARNESS_UPDATE_GOLDEN set - updating Golden Reference File")
+ (call-process "cp" nil t t temp-file golden-file))
+ ((not (equal status 0))
+ (message (concat "diff -c " golden-file " " temp-file))
+ (message "***Golden Reference File\n---Generated Test File")
+ (message "%s" (buffer-string))
+ (message "To promote current to golden, in shell buffer hit newline anywhere in next line (^P RETURN):")
+ (message (concat "cp " temp-file " " golden-file "; VERILOG_MODE_START_FILE=" golden-file " " again ))
+ (error ""))
+ (t
+ (message "Verified %s" golden-file))))))
+
+(defun vl-do-on-thread (file-num)
+ "Return true to process due to multithreading"
+ (cond (vl-threading
+ (or (string-match "\\([0-9]+\\)of\\([0-9]+\\)" vl-threading)
+ (error "VERILOG_MODE_THREAD not in #of# form"))
+ (let ((th (string-to-number (match-string 1 vl-threading)))
+ (numth (string-to-number (match-string 2 vl-threading))))
+ (equal (1+ (mod file-num numth)) th)))
+ (t t)))
+
+(defun verilog-test ()
+ (let ((files (directory-files "tests"))
+ (tests-run 0)
+ (file-num 0)
+ file cf temp-file)
+
+ (when (getenv "VERILOG_MODE_DEBUG")
+ (setq verilog-debug t))
+
+ (when (getenv "VERILOG_MODE_TEST_FILE")
+ (setq files (list (getenv "VERILOG_MODE_TEST_FILE")))
+ (message "**** Only testing files in $VERILOG_MODE_TEST_FILE"))
+
+ (when (getenv "VERILOG_MODE_START_FILE")
+ (let* ((startfiles (list (getenv "VERILOG_MODE_START_FILE")))
+ (startfile (car startfiles)))
+ (message (concat "Starting from file " startfile))
+ (catch 'done
+ (while files
+ (setq file (car files))
+ (if (or (string-equal file startfile)
+ (string-equal (concat "tests_ok/" file) startfile))
+ (progn
+ (message (concat "matched " file))
+ (throw 'done 0))
+ (progn
+ (setq files (cdr files))))))))
+
+ (message "emacs-version %s" emacs-version)
+
+ (while files
+ (setq file (car files))
+ (setq temp-file (concat (if running-on-xemacs "x/t/" "e/t/")
+ file))
+ (cond ((equal "." file))
+ ((equal ".." file))
+ ((string-match "#" file)) ;; Backups
+ ((string-match "~$" file))
+ ((string-match "\.f$" file))
+ ((string-match "\.dontrun$" file))
+ ((file-directory-p (concat "tests/" file)))
+ ((progn (setq file-num (1+ file-num))
+ (not (vl-do-on-thread file-num))))
+ (t
+ (message (concat "Considering test " file ))
+ (if running-on-xemacs
+ (progn
+ (setq cf (concat "skip_for_xemacs/" file))
+ (if (file-exists-p cf ) ;
+ (message (concat "Skipping testing " file " on Xemacs because file " cf "exists"))
+ (progn
+ (verilog-test-file file temp-file)
+ (setq tests-run (1+ tests-run))
+ )
+ ))
+ (progn
+ (verilog-test-file file temp-file)
+ (setq tests-run (1+ tests-run))
+ ))
+ (message (format " %d tests run so far, %d left... %s"
+ tests-run (length files)
+ (if vl-threading (concat "Thread " vl-threading) "")))
+ ))
+ (setq files (cdr files))))
+ (message "Tests Passed on %s" (emacs-version))
+ "Tests Passed")
+
+(defun vl-indent-file ()
+ "Reindent file"
+ (interactive)
+ (save-excursion
+ (goto-char (point-min))
+ (while (not (eobp))
+ (electric-verilog-tab)
+ (end-of-line)
+ (delete-char (- (skip-chars-backward " \t")))
+ (forward-line 1)
+ )
+ )
+ (write-file (buffer-file-name))
+ )
+
+(progn
+ (save-excursion
+ (with-temp-buffer
+ (verilog-mode)))
+
+ ;; Setup
+ (require `compile)
+ (defun ask-user-about-lock() nil) ;; XEmacs - Disable lock conflicts
+ (setq running-on-xemacs (string-match "XEmacs" emacs-version))
+ (setq make-backup-files nil)
+ (setq-default make-backup-files nil)
+ (setq diff-flags (if (getenv "VERILOG_MODE_NO_INDENTS") "-wBu" "-u"))
+ ;;(setq verilog-auto-lineup 'all)
+ (setq enable-local-variables t)
+ (setq enable-local-eval t)
+ (setq auto-mode-alist (cons '("\\.v\\'" . verilog-mode) auto-mode-alist))
+ (setq-default fill-column 100)
+ (if running-on-xemacs
+ (setq again "make test_xemacs")
+ (setq again "make test_emacs"))
+ (verilog-test)
+)
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..94a9ed0
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,674 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
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+
+ The licenses for most software and other practical works are designed
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+patent license under the contributor's essential patent claims, to
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+
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+and the Corresponding Source of the work is not available for anyone
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+consistent with the requirements of this License, to extend the patent
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+actual knowledge that, but for the patent license, your conveying the
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+
+ If, pursuant to or in connection with a single transaction or
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+covered work, and grant a patent license to some of the parties
+receiving the covered work authorizing them to use, propagate, modify
+or convey a specific copy of the covered work, then the patent license
+you grant is automatically extended to all recipients of the covered
+work and works based on it.
+
+ A patent license is "discriminatory" if it does not include within
+the scope of its coverage, prohibits the exercise of, or is
+conditioned on the non-exercise of one or more of the rights that are
+specifically granted under this License. You may not convey a covered
+work if you are a party to an arrangement with a third party that is
+in the business of distributing software, under which you make payment
+to the third party based on the extent of your activity of conveying
+the work, and under which the third party grants, to any of the
+parties who would receive the covered work from you, a discriminatory
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+conveyed by you (or copies made from those copies), or (b) primarily
+for and in connection with specific products or compilations that
+contain the covered work, unless you entered into that arrangement,
+or that patent license was granted, prior to 28 March 2007.
+
+ Nothing in this License shall be construed as excluding or limiting
+any implied license or other defenses to infringement that may
+otherwise be available to you under applicable patent law.
+
+ 12. No Surrender of Others' Freedom.
+
+ If conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot convey a
+covered work so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you may
+not convey it at all. For example, if you agree to terms that obligate you
+to collect a royalty for further conveying from those to whom you convey
+the Program, the only way you could satisfy both those terms and this
+License would be to refrain entirely from conveying the Program.
+
+ 13. Use with the GNU Affero General Public License.
+
+ Notwithstanding any other provision of this License, you have
+permission to link or combine any covered work with a work licensed
+under version 3 of the GNU Affero General Public License into a single
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+License will continue to apply to the part which is the covered work,
+but the special requirements of the GNU Affero General Public License,
+section 13, concerning interaction through a network will apply to the
+combination as such.
+
+ 14. Revised Versions of this License.
+
+ The Free Software Foundation may publish revised and/or new versions of
+the GNU General Public License from time to time. Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+ Each version is given a distinguishing version number. If the
+Program specifies that a certain numbered version of the GNU General
+Public License "or any later version" applies to it, you have the
+option of following the terms and conditions either of that numbered
+version or of any later version published by the Free Software
+Foundation. If the Program does not specify a version number of the
+GNU General Public License, you may choose any version ever published
+by the Free Software Foundation.
+
+ If the Program specifies that a proxy can decide which future
+versions of the GNU General Public License can be used, that proxy's
+public statement of acceptance of a version permanently authorizes you
+to choose that version for the Program.
+
+ Later license versions may give you additional or different
+permissions. However, no additional obligations are imposed on any
+author or copyright holder as a result of your choosing to follow a
+later version.
+
+ 15. Disclaimer of Warranty.
+
+ THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
+APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
+HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
+OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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+IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
+ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+ 16. Limitation of Liability.
+
+ IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
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+THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
+GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
+USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
+DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
+PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
+EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
+SUCH DAMAGES.
+
+ 17. Interpretation of Sections 15 and 16.
+
+ If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+ To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+ <one line to give the program's name and a brief idea of what it does.>
+ Copyright (C) <year> <name of author>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+ If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+ <program> Copyright (C) <year> <name of author>
+ This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+ You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+<http://www.gnu.org/licenses/>.
+
+ The GNU General Public License does not permit incorporating your program
+into proprietary programs. If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library. If this is what you want to do, use the GNU Lesser General
+Public License instead of this License. But first, please read
+<http://www.gnu.org/philosophy/why-not-lgpl.html>.
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..8bf3b6d
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,193 @@
+# DESCRIPTION: Run verilog-mode tests, as part of "make test"
+#
+# Copyright 2008-2013 by Michael McNamara and Wilson Snyder. This package
+# is free software; you can redistribute it and/or modify it under the
+# terms of either the GNU Lesser General Public License or the Perl
+# Artistic License.
+#
+######################################################################
+# Common targets:
+# make # Compile source for GNU and Xemacs
+# make test # Run self tests
+# # See x/verilog-mode.el for version to install
+######################################################################
+
+S=/home/mac/development/www.verilog.com/src/
+D=$(S)data
+F=/home/mac/external_webpage/src/verilog.com/ftp
+# the directory where the .elc files will be installed
+XEMACS = xemacs
+XEMACS_DEST = /usr/local/lib/xemacs/xemacs-packages/lisp/prog-modes/
+EMACS = emacs
+EMACS_DEST = /usr/share/emacs/site-lisp/
+ELC = -batch -q -f batch-byte-compile
+MAKECHANGELOG = perl makechangelog
+
+default : e/verilog-mode.elc x/verilog-mode.elc
+
+release : .timestamps
+install : .timestamps ChangeLog test $(D)/mmencoded_verilog-mode $(D)/emacs-version.h\
+ $(S)ChangeLog.txt email $(S)bits/verilog-mode.el local \
+# ftp
+ @echo Installation up to date
+
+.timestamps:
+ @mkdir -p $@
+
+test: .timestamps/test
+.timestamps/test: x/verilog-mode.elc e/verilog-mode.elc mmencoded_verilog-mode verilog.info 0test.el .timestamps
+ifeq ($(VERILOG_MODE_TEST_FILE),)
+ $(MAKE) test_batch test_errors test_emacs test_xemacs
+ @touch $@
+ @echo ======= ALL TESTS PASSED
+else
+ $(MAKE) test_emacs test_xemacs
+endif
+
+#Usage: $(call test-emacs_sub,label,threading)
+define test_emacs_sub
+test_emacs:: $(1)
+$(1): e/verilog-mode.elc
+ @echo
+ @echo == $(1)
+ @mkdir -p e/t
+ VERILOG_MODE_THREAD=$(2) time $(EMACS) --batch -q --no-site-file -l e/verilog-mode.elc -l 0test.el
+endef
+
+$(eval $(call test_emacs_sub,test_emacs_1,1of5))
+ifeq ($(VERILOG_MODE_TEST_FILE),)
+$(eval $(call test_emacs_sub,test_emacs_2,2of5))
+$(eval $(call test_emacs_sub,test_emacs_3,3of5))
+$(eval $(call test_emacs_sub,test_emacs_4,4of5))
+$(eval $(call test_emacs_sub,test_emacs_5,5of5))
+endif
+
+#Usage: $(call test_xemacs_sub,label,threading)
+define test_xemacs_sub
+test_xemacs:: $(1)
+$(1): x/verilog-mode.elc
+ @echo
+ @echo == $(1)
+ @mkdir -p x/t
+ VERILOG_MODE_THREAD=$(2) time $(XEMACS) --batch -vanilla -l x/verilog-mode.elc -l 0test.el
+endef
+
+$(eval $(call test_xemacs_sub,test_xemacs_1,1of5))
+ifeq ($(VERILOG_MODE_TEST_FILE),)
+$(eval $(call test_xemacs_sub,test_xemacs_2,2of5))
+$(eval $(call test_xemacs_sub,test_xemacs_3,3of5))
+$(eval $(call test_xemacs_sub,test_xemacs_4,4of5))
+$(eval $(call test_xemacs_sub,test_xemacs_5,5of5))
+endif
+
+test_errors:
+ @echo
+ @echo == test_errors
+ -# The multiline errors must be in one read()s output or the comint may not match it
+ -cat error_msgs.out
+
+test_batch: e/verilog-mode.elc
+ @echo == test_batch
+ mkdir -p e/b
+ time ./batch_test.pl
+
+local: .timestamps/local
+.timestamps/local: verilog-mode.el
+ cp verilog-mode.el $(XEMACS_DEST)verilog-mode.el
+ rm -f $(XEMACS_DEST)verilog-mode.elc
+ $(XEMACS) $(ELC) $(XEMACS_DEST)verilog-mode.el
+ cp verilog-mode.el $(EMACS_DEST)verilog-mode.el
+ rm -f $(EMACS_DEST)verilog-mode.elc
+ $(EMACS) $(ELC) $(EMACS_DEST)verilog-mode.el
+ @touch $@
+
+ftp: .timestamps/ftp
+.timestamps/ftp: $(F) mmencoded_verilog-mode verilog-mode.el README
+ cp mmencoded_verilog-mode $(F)
+ cp verilog-mode.el $(F)
+ cp README $(F)/.message
+ @touch $@
+
+$(F):
+ mkdir $(F)
+
+ChangeLog.txt mmencoded_verilog-mode emacs-version.h : make_log.pl verilog-mode.el README
+ifneq ($(VERILOGMODE_SKIP_MAKELOG),1)
+ ./make_log.pl
+endif
+
+ChangeLog : verilog-mode.el makechangelog
+ $(MAKECHANGELOG) --git verilog-mode.el > $@
+
+email: .timestamps/email
+.timestamps/email: mmencoded_verilog-mode
+ ./make_mail.pl
+ @touch $@
+
+$(D)/mmencoded_verilog-mode : mmencoded_verilog-mode
+ cp $? $@
+$(D)/emacs-version.h : emacs-version.h
+ cp $? $@
+ touch $(S)verilog-mode.html
+$(S)ChangeLog.txt : ChangeLog.txt
+ cp $? $@
+$(S)bits/verilog-mode.el : verilog-mode.el
+ cp $? $@
+
+x/verilog-mode.el : verilog-mode.el ./config_rev.pl
+ rm -rf x
+ mkdir x
+ ./config_rev.pl . . <verilog-mode.el >x/verilog-mode.el
+
+e/verilog-mode.el : verilog-mode.el ./config_rev.pl
+ -rm -rf e
+ -mkdir e
+ ./config_rev.pl . . <verilog-mode.el >e/verilog-mode.el
+
+e/verilog-mode.el.gz : e/verilog-mode.el
+ gzip --best $< --stdout > $@
+
+x/verilog-mode.elc : x/verilog-mode.el
+ $(XEMACS) $(ELC) x/verilog-mode.el
+
+e/verilog-mode.elc : e/verilog-mode.el
+ $(EMACS) $(ELC) e/verilog-mode.el
+
+verilog.info : verilog.texinfo
+ makeinfo verilog.texinfo > verilog.info
+
+######################################################################
+# GNU GIT version
+
+gnutrunk:
+ @echo "gnutrunk needs to be a symlink to a emacs/trunk git checkout"
+ false
+
+.PHONY: gnu-update gnu-update-trunk
+gnu-update: gnu-update-trunk
+gnu-update-trunk: gnutrunk
+ echo "NOT DOING: cd gnutrunk && git pull"
+
+.PHONY: gnu-diff-trunk gnu-diff
+gnu-diff: gnu-diff-trunk
+gnu-diff-trunk: gnu-update-trunk verilog-mode-tognu.el
+ diff -u gnutrunk/lisp/progmodes/verilog-mode.el verilog-mode-tognu.el
+verilog-mode.patch: gnu-update verilog-mode-tognu.el
+ diff -u gnutrunk/lisp/progmodes/verilog-mode.el verilog-mode-tognu.el > $@
+# Before install, clean to make sure we get proper git ID
+gnu-cp:
+ $(MAKE) clean
+ $(MAKE) verilog-mode-tognu.el
+ cp verilog-mode-tognu.el gnutrunk/lisp/progmodes/verilog-mode.el
+
+verilog-mode-tognu.el: e/verilog-mode.el Makefile
+ cat e/verilog-mode.el \
+ | sed 's/verilog-mode-version "\(.*\)"/verilog-mode-version "\1-GNU"/g' \
+ | sed 's/verilog-mode-release-emacs nil/verilog-mode-release-emacs t/g' \
+ > verilog-mode-tognu.el
+
+######################################################################
+# Clean
+
+clean::
+ /bin/rm -rf .timestamps e x test_dir verilog-mode.patch verilog-mode-tognu.el mmencoded_verilog-mode *.info
diff --git a/README b/README
new file mode 100644
index 0000000..ab90af9
--- /dev/null
+++ b/README
@@ -0,0 +1,40 @@
+This is the source distribution for verilog-mode.
+
+Please see http://www.veripool.org/verilog-mode
+for more information.
+
+ make
+ make test
+ cp e/verilog-mode.el <your emacs site lisp path>
+
+======================================================================
+TESTS
+
+Make sure both emacs and xemacs are installed and "make test". Testing can run on multiple cores with "make -j 10 test".
+
+Under the hood this is (mostly) running 0test.el. This reads in each file
+under tests/ directory, autos, reindents, and compares the result to the
+matching filename in the tests_ok directory.
+
+Test failures generally look like this:
+
+ diff -c tests_ok/autoinout_ma.v e/t/autoinout_ma.v
+ ***Golden Reference File
+ ---Generated Test File
+ --- GOLDEN_REFERENCE
+ +++ CURRENT_BEHAVIOR
+ ...
+ - output sina,
+ + output siuna,
+ To promote current to golden, in shell buffer hit newline anywhere in next line (^P RETURN):
+ cp e/t/autoinout_ma.v tests_ok/autoinout_ma.v; VERILOG_MODE_START_FILE=tests_ok/autoinout_ma.v make test_emacs
+
+This indicates the generated output doesn't match what is in tests_ok. To
+fix this make sure that the change is expected then do the "cp" shown to
+update the golden references:
+
+ cp e/t/autoinout_ma.v tests_ok/autoinout_ma.v
+
+Then "make test" again. The suggested VERILOG_MODE_START_FILE can also be
+used to jump right to that individual test inside the "make test"
+
diff --git a/TODO b/TODO
new file mode 100644
index 0000000..bbb32ed
--- /dev/null
+++ b/TODO
@@ -0,0 +1,65 @@
+# DESCRIPTION: To-do list for verilog-mode
+######################################################################
+
+Occasionally:
+ * M-x checkdoc
+ * Make sure it's as byte compile clean as possible.
+
+Features
+ Make a hiearchy map of the current module and below in a spare buffer.
+
+;From: Dan Nicolaescu <dann@ics.uci.edu>
+;Date: Sun, 14 Oct 2007 10:49:43 -0700
+
+; > (defvar verilog-mode-map ()
+; > "Keymap used in Verilog mode.")
+; > (if verilog-mode-map
+; > ()
+; > (setq verilog-mode-map (make-sparse-keymap))
+; > (define-key verilog-mode-map ";" 'electric-verilog-semi)
+
+; Better use:
+
+; (defvar verilog-mode-map
+; (let ((map (make-sparse-keymap)))
+; (define-key map ";" 'electric-verilog-semi)
+; ... etc etc
+
+
+From: Stefan Monnier <monnier@iro.umontreal.ca>
+Date: Sat, 13 Oct 2007 22:41:15 -0400
+
+ - Rather than create a new syntax-table in each buffer, just do
+
+ (defvar verilog-mode-syntax-table
+ (let ((st (make-syntax-table)))
+ (modify-syntax-table ...)
+ ...
+ st))
+
+ once and forall (inlining the only calls to verilog-setup-dual-comments
+ and verilog-populate-syntax-table).
+ Regarding verilog-setup-dual-comments, even if you consider the XEmacs
+ solution cleaner, the Emacs solution is not only equivalent but it also
+ works under XEmacs, so you can use it everywhere and remove an
+ emacs-version check.
+ - You can then remove the verilog-emacs-features abomination.
+
+ - The part
+
+ (require 'verilog-mode)
+
+ is pretty hideous and deserves either to be fixed (i.e. removed), or large
+ comments justifying each part.
+ Also some of the subsequent requires are unneeded (e.g. the `imenu' one).
+
+ - Use easy-menu-add rather than add-submenu so it works on both Emacs
+ and XEmacs.
+
+ - Emacs-21's comment-region and uncomment-region should work correctly
+ (including mangling nested comments, although in a different way from the
+ one you chose).
+
+ verilog-comment-regiont and verilog-uncomment-region
+ can (probably) be dropped when running under Emacs>=21 (and the C-c C-c
+ binding could also be removed if you assume your users will use M-;)
diff --git a/attic/verilog-lex.el b/attic/verilog-lex.el
new file mode 100644
index 0000000..57022e0
--- /dev/null
+++ b/attic/verilog-lex.el
@@ -0,0 +1,161 @@
+;;
+;; Lexical analysis
+;;
+
+(defconst verilog-token-comma ?, "Verilog-lex ','.")
+(defconst verilog-token-semi ?; "Verilog-lex ';'.")
+(defconst verilog-token-equal ?= "Verilog-lex '='.")
+(defconst verilog-token-par ?( "Verilog-lex '('.")
+(defconst verilog-token-en ?) "Verilog-lex ')'.")
+(defconst verilog-token-bra ?{ "Verilog-lex '{'.")
+(defconst verilog-token-ce ?} "Verilog-lex '}'.")
+
+;; Lexical tokens specific to verilog-lex-decl
+(defconst verilog-token-ASSIGN 300 "Verilog-lex 'KEYWORD'.")
+(defconst verilog-token-PARAMETER 306 "Verilog-lex 'KEYWORD'.")
+(defconst verilog-token-SIGNED 307 "Verilog-lex 'KEYWORD'.")
+(defconst verilog-token-bracketed 311 "Verilog-lex '[...]'; value is what's within brackets.")
+(defconst verilog-token-decl-const 301 "Verilog-lex declare constant.")
+(defconst verilog-token-decl-wire 302 "Verilog-lex declare wire.")
+(defconst verilog-token-direction 303 "Verilog-lex directional.")
+(defconst verilog-token-ignore-begin 304 "Verilog-lex block to ignore begin.")
+(defconst verilog-token-ignore-end 305 "Verilog-lex block to ignore end.")
+(defconst verilog-token-symbol 310 "Verilog-lex symbol.")
+(defconst verilog-token-synth-enum 312 "Verilog-lex Synopsys enum token; value is name of enumeration.")
+(defconst verilog-token-type 308 "Verilog-lex data type.")
+(defconst verilog-token-keyword 313 "Verilog-lex generic keyword.")
+
+(defconst verilog-lex-keywords
+ '(
+ ("assign" verilog-token-ASSIGN)
+ ("bit" verilog-token-type)
+ ("byte" verilog-token-type)
+ ("class" verilog-token-ignore-begin)
+ ("clocking" verilog-token-ignore-begin)
+ ("covergroup" verilog-token-ignore-begin)
+ ("endclass" verilog-token-ignore-end)
+ ("endclocking" verilog-token-ignore-end)
+ ("endfunction" verilog-token-ignore-end)
+ ("endgroup" verilog-token-ignore-end)
+ ("endproperty" verilog-token-ignore-end)
+ ("endsequence" verilog-token-ignore-end)
+ ("endtask" verilog-token-ignore-end)
+ ("function" verilog-token-ignore-begin)
+ ("genvar" verilog-token-decl-const)
+ ("inout" verilog-token-direction)
+ ("input" verilog-token-direction)
+ ("int" verilog-token-type)
+ ("integer" verilog-token-type)
+ ("localparam" verilog-token-decl-const)
+ ("logic" verilog-token-type)
+ ("longint" verilog-token-type)
+ ("output" verilog-token-direction)
+ ("parameter" verilog-token-PARAMETER)
+ ("property" verilog-token-ignore-begin)
+ ("randsequence" verilog-token-ignore-begin)
+ ("real" verilog-token-type)
+ ("reg" verilog-token-type)
+ ("sequence" verilog-token-ignore-begin)
+ ("shortint" verilog-token-type)
+ ("shortreal" verilog-token-type)
+ ("signed" verilog-token-signing)
+ ("supply" verilog-token-decl-const)
+ ("supply0" verilog-token-decl-const)
+ ("supply1" verilog-token-decl-const)
+ ("task" verilog-token-ignore-begin)
+ ("time" verilog-token-type)
+ ("tri" verilog-token-decl-wire)
+ ("tri0" verilog-token-decl-wire)
+ ("tri1" verilog-token-decl-wire)
+ ("triand" verilog-token-decl-wire)
+ ("trior" verilog-token-decl-wire)
+ ("trireg" verilog-token-type)
+ ("wand" verilog-token-decl-wire)
+ ("wire" verilog-token-decl-wire)
+ ("wor" verilog-token-decl-wire)
+ )
+ "Map of keyword and token to return for `verilog-lex'.")
+
+(defun verilog-lex (begin end for-decls)
+ "Lexically analyze Verilog text between BEGIN to END into tokens.
+With FOR-DECL true, parse only for declarations. Returns list of
+tokens, with each token a list of the text for that token and the
+verilog-token-TYPE."
+ (let ((functask 0)
+ tokens token keywd ignore-next-symbol)
+ (save-excursion
+ (goto-char begin)
+ (while (< (point) end)
+ ;;(if dbg (setq dbg (cons (format "Pt %s Vec %s Kwd'%s'\n" (point) vec keywd) dbg)))
+ (cond
+ ;; For performance it's better if frequent cases are first
+ ((looking-at "//")
+ (when (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
+ (setq tokens (cons (list (match-string 1) verilog-token-synth-enum) tokens)))
+ (search-forward "\n"))
+ ((looking-at "/\\*")
+ (forward-char 2)
+ (when (looking-at "[^*]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
+ (setq tokens (cons (list (match-string 1) verilog-token-synth-enum) tokens)))
+ (or (search-forward "*/")
+ (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
+ ((looking-at "(\\*")
+ (forward-char 2)
+ (or (looking-at "\\s-*)") ; It's an "always @ (*)"
+ (search-forward "*)")
+ (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
+ ((eq ?\" (following-char))
+ (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
+ (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
+ ;; []: Grab all text to ending ]. Probably should match bracket pairs and strip comments, but old version didn't
+ ((looking-at "\\[[^]]+\\]")
+ (goto-char (match-end 0))
+ (setq tokens (cons (list (match-string 0) verilog-token-bracketed) tokens)))
+ ;; Single character tokens we just pass through
+ ((looking-at "[;,=(){}]")
+ (setq tokens (cons (list (following-char) (following-char)) tokens))
+ (forward-char 1))
+ ;; Ifdef, ignore name of define
+ ((looking-at "`ifn?def\\>")
+ (goto-char (match-end 0))
+ (setq ignore-next-symbol t))
+ ;; Normal identifier
+ ((looking-at "[`a-zA-Z0-9_$]+")
+ (goto-char (match-end 0))
+ ;; buffer-substring is faster than match-string, and this is hot code.
+ (setq keywd (buffer-substring-no-properties (match-beginning 0) (match-end 0)))
+ (cond (ignore-next-symbol ;; preproc identifier after `ifdef
+ (setq ignore-next-symbol nil))
+ ((member keywd verilog-keywords)
+ (setq token (assoc keywd verilog-lex-keywords))
+ ;; Now you'll see why the token list has text first then the token number;
+ ;; we can just return the assoc result directly
+ (cond ((eq token verilog-token-ignore-begin)
+ (setq functask (1+ functask)))
+ ((eq token verilog-token-ignore-end)
+ (setq functask (1- functask)))
+ (token
+ (setq tokens (cons token tokens)))
+ (t
+ (setq tokens (cons (list keywd verilog-token-keyword) tokens)))))
+ ;; Must be typedef or symbol. For speed, ignore if inside begin/end
+ ((and (eq functask 0)
+ (verilog-typedef-name-p keywd))
+ (setq tokens (cons (list keywd verilog-token-typedef) tokens)))
+ ;; Normal user symbol
+ ((eq functask 0)
+ (setq tokens (cons (list keywd verilog-token-symbol) tokens)))))
+ ;; Escaped identifier -- note we remember the \ if escaped
+ ((looking-at "\\\\[^ \t\n\f]+")
+ (goto-char (match-end 0))
+ (when (eq functask 0)
+ (setq tokens (cons (list (concat (match-string-no-properties 0) " ") ;; Escaped ID needs space at end
+ verilog-token-symbol)
+ tokens))))
+ ;; Default
+ (t
+ (forward-char 1)))
+ ;; End of parser while
+ (skip-syntax-forward " "))
+ tokens)))
+
diff --git a/batch_prof.el b/batch_prof.el
new file mode 100644
index 0000000..61f97a1
--- /dev/null
+++ b/batch_prof.el
@@ -0,0 +1,81 @@
+;; DESCRIPTION: Profile driven test as part of "make test"
+;;
+;; Copyright 2008-2013 by Michael McNamara and Wilson Snyder. This package
+;; is free software; you can redistribute it and/or modify it under the
+;; terms of either the GNU Lesser General Public License or the Perl
+;; Artistic License.
+
+(require 'elp)
+
+(defun t-make-test (count filename)
+ (save-excursion
+ (find-file filename)
+ (delete-region (point-min) (point-max))
+ (insert "
+module EX_TIME_CONSUME (/*AUTOARG*/);
+/*AUTOOUTPUT*/
+/*AUTOINPUT*/
+/*AUTOWIRE*/
+")
+ (setq i 0)
+ (while (< i count)
+ (insert "//----------------------------------------------------------------------\n")
+ (insert "/* batch_prof_cell AUTO_TEMPLATE (\n")
+ (insert (format " .Z(Z_%d)); */\n" i))
+ (insert (format "batch_prof_cell CELL_%d (/*AUTOINST*/);\n" i))
+ (setq i (+ 1 i)))
+ (insert "endmodule\n")
+ (save-buffer)))
+
+(defun t-size-test (count)
+ ;; Note is running in tests_batch_ok directory
+ (setq filename (format "e/b/batch_prof_%s.v" count))
+ (t-make-test count filename)
+ (when profile
+ (elp-reset-all))
+ (setq start (current-time))
+ (save-excursion
+ (find-file filename)
+ (verilog-auto))
+ (setq end (current-time))
+ (setq delta (time-to-seconds (time-subtract end start)))
+ (setq msper (/ (* 1000 delta) count))
+ (message "Count: %5d Time: %6.3f msec/inst: %6.3f File: %s"
+ count delta msper filename)
+ (when profile
+ (elp-results))
+ (when nil
+ (save-excursion
+ (find-file filename)
+ (save-buffer)))
+ msper)
+
+;;======================================================================
+
+(setq make-backup-files nil)
+(copy-file "tests/batch_prof_cell.v" "e/b/batch_prof_cell.v" t)
+(setq verilog-debug t)
+(setq verilog-library-flags "-I.")
+(setq verilog-auto-star-expand nil)
+(setq profile (getenv "VERILOG_MODE_PROFILE"))
+
+(when profile
+ (elp-restore-all)
+ (elp-instrument-package "verilog"))
+
+(when t
+ ;; Need to read the templated file
+ (setq t1 (t-size-test 1))
+ (setq t10 (t-size-test 10))
+ (setq t100 (t-size-test 100))
+ (setq t1000 (t-size-test 1000))
+ (when (getenv "VERILOG_MODE_10000")
+ (setq t10000 (t-size-test 10000)))
+
+ (setq slope (/ t1000 t100))
+ (setq order (1+ (/ (log slope)
+ (log 10))))
+ (message "Slope: %f Complexity: O(n^%f)" slope order)
+ (if (> slope 1.3)
+ (error "Test failed, large modules are too slow compared to small modules"))
+)
diff --git a/batch_test.el b/batch_test.el
new file mode 100644
index 0000000..808be4b
--- /dev/null
+++ b/batch_test.el
@@ -0,0 +1,8 @@
+;; DESCRIPTION: Common Emacs flags needed for batch_test.pl
+;;
+;; Copyright 2008-2013 by Michael McNamara and Wilson Snyder. This package
+;; is free software; you can redistribute it and/or modify it under the
+;; terms of either the GNU Lesser General Public License or the Perl
+;; Artistic License.
+
+(setq verilog-library-flags "-I. -I../../tests")
diff --git a/batch_test.pl b/batch_test.pl
new file mode 100755
index 0000000..e4782a3
--- /dev/null
+++ b/batch_test.pl
@@ -0,0 +1,75 @@
+#!/usr/bin/perl -w
+# DESCRIPTION: Run batch tests, as part of "make test"
+#
+# Copyright 2008-2013 by Michael McNamara and Wilson Snyder. This package
+# is free software; you can redistribute it and/or modify it under the
+# terms of either the GNU Lesser General Public License or the Perl
+# Artistic License.
+
+my $tmpdir = "e";
+
+my @tests = map { s!^.*/!!; $_;} glob("tests_batch_ok/*");
+
+my @tests_args;
+foreach my $test (@tests) {
+ run("/bin/cp tests/$test e/b/$test");
+ push @tests_args, "e/b/$test";
+}
+
+run("emacs --version"
+ );
+
+run("emacs --batch --no-site-file -l $tmpdir/verilog-mode.elc"
+ ." -l ./batch_test.el"
+ ." ".join(' ',@tests_args)
+ ." -f verilog-batch-delete-auto"
+ );
+
+run("emacs --batch --no-site-file -l $tmpdir/verilog-mode.elc"
+ ." -l ./batch_test.el"
+ ." ".join(' ',@tests_args)
+ ." -f verilog-batch-auto"
+ );
+
+run("emacs --batch --no-site-file -l $tmpdir/verilog-mode.elc"
+ ." -l ./batch_test.el"
+ ." e/b/autoinst_lopaz.v"
+ ." -f verilog-batch-diff-auto"
+ );
+
+run("emacs --batch --no-site-file -l $tmpdir/verilog-mode.elc"
+ ." -l ./batch_test.el"
+ ." e/b/autoinst_star.v"
+ ." -f verilog-batch-diff-auto"
+ );
+
+run("emacs --batch --no-site-file -l $tmpdir/verilog-mode.elc"
+ ." -l ./batch_test.el"
+ ." ".join(' ',@tests_args)
+ ." -f verilog-batch-indent"
+ );
+
+foreach my $test (@tests) {
+ run("diff tests_batch_ok/$test e/b/$test");
+}
+
+run("emacs --batch --no-site-file -l $tmpdir/verilog-mode.elc"
+ ." -l ./batch_test.el"
+ ." ".join(' ',@tests_args)
+ ." -f verilog-batch-delete-trailing-whitespace"
+ );
+
+run("emacs --batch --no-site-file -l $tmpdir/verilog-mode.elc"
+ ." -l ./batch_prof.el"
+ );
+
+#######################################################################
+
+sub run {
+ # Run a system command, check errors
+ my $command = shift;
+ print "\t$command\n";
+ system "$command";
+ my $status = $?;
+ ($status == 0) or die "%Error: Command Failed $command, stopped";
+}
diff --git a/config_rev.pl b/config_rev.pl
new file mode 100755
index 0000000..720b982
--- /dev/null
+++ b/config_rev.pl
@@ -0,0 +1,35 @@
+#!/usr/bin/perl -w
+# DESCRIPTION: Query's git to get version number
+######################################################################
+#
+# Copyright 2005-2013 by Wilson Snyder. This is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+#
+######################################################################
+
+my $dir = $ARGV[0]; defined $dir or die "%Error: No directory argument,";
+chdir $dir;
+my $file = $ARGV[1]; defined $file or die "%Error: No file argument,";
+
+my $rev = 'UNKNOWN_REV';
+my $data = `git log --pretty=format:'%ad-%h' --date=short -1 $file`;
+if ($data =~ /(^20.*)/i) {
+ $rev = $1;
+}
+
+$data = `git status $file`;
+if ($data =~ /Changed but not updated/i
+ || $data =~ /Changes to be committed/i) {
+ $rev .= "-mod";
+}
+
+# Filter the code
+my $wholefile = join('',<STDIN>);
+$wholefile =~ s/__VMVERSION__-__VMREVISION__/$rev/mg;
+$wholefile =~ s/__VMPACKAGER__/vpo/mg;
+print $wholefile;
+
+# Die after the print, so at least the header has good contents
+$rev =~ /UNKNOWN/ and warn "%Warning: No git revision found,";
diff --git a/error_file.v b/error_file.v
new file mode 100644
index 0000000..700b75a
--- /dev/null
+++ b/error_file.v
@@ -0,0 +1,44 @@
+1;
+2;
+3;
+4;
+5;
+6;
+7;
+8;
+9;
+10;
+11;
+12;
+13;
+14;
+15;
+16;
+17;
+18;
+19;
+20;
+21;
+22;
+23;
+24;
+25;
+26;
+27;
+28;
+29;
+30;
+31;
+32;
+33;
+34;
+35;
+36;
+37;
+38;
+39;
+40;
+
+// Local Variables:
+// compile-command: "make test_errors "
+// End:
diff --git a/error_msgs.out b/error_msgs.out
new file mode 100644
index 0000000..163b5c2
--- /dev/null
+++ b/error_msgs.out
@@ -0,0 +1,30 @@
+A bunch of error messages that Emacs should
+recognize if you type C-x ` and take you to the correct line of error_file.v
+Note the 'gnu' compilation-error-regexp-alist in messes some up - to be fixed.
+(setq compilation-error-regexp-alist (delete 'gnu compilation-error-regexp-alist))
+
+Warning: code located there (error_file.v line 9) is dangerous
+(W1800) error_file.v 21: Problems
+f*E,1364 (error_file.v,2) Issues
+Error: code located here (error_file.v line 8) is fatal
+ERROR : error_file.v, line 1: erroneous
+INFO : error_file.v, line 7: informational
+WARNING : error_file.v, line 6: curious
+nctool: *E,UNDIDN (error_file.v,11|22): 'zz': the message [12.5(IEEE)].
+nctool: *W,TRUNCZ (error_file.v,14|0): a W message.
+nctool: *W,URDREG[CN_ABSTR] (error_file.v,15|0): another W message in 'foo'.
+Verilog-Perl: %Error: error_file.v:16: Some message from Verilog-Perl etc.
+Verilog-Perl: %Warning: ./error_file.v:17: Some message from Verilog-Perl etc.
+%Warning: ./error_file.v:17: Some message from Verilator etc.
+# This must be in one echo, or the comint may not match it
+In file error_file.v line 5:
+a
+b
+Failure was obsevred
+la di da
+syntax error: problems
+error_file.v 7: here is where they are
+
+// Local Variables:
+// compile-command: "make test_errors "
+// End:
diff --git a/make_log.pl b/make_log.pl
new file mode 100755
index 0000000..48854db
--- /dev/null
+++ b/make_log.pl
@@ -0,0 +1,82 @@
+#!/usr/bin/perl
+
+unlink("log");
+$attach_name = "verilog-mode.el.gz";
+$encoded_data = `gzip -c9 verilog-mode.el | mmencode `;
+if ( -d ".svn") {
+ system("svn log verilog-mode.el > log");
+ open(LOG,"<log");
+ while(<LOG>) {
+ if (/^r([\d\.]+)/) {
+ $rev = $1;
+ last;
+ }
+ }
+
+} else {
+ system("cvs log verilog-mode.el > log");
+ open(LOG,"<log");
+ while(<LOG>) {
+ if (/^head: ([\d\.]+)$/) {
+ $rev = $1;
+ }
+ last if (/^description:$/);
+ }
+}
+open(O,">emacs-version.h");
+open(C,">ChangeLog.txt");
+$release_date = `date +"%D"`;
+print O <<"X";
+<define-tag emacs-vid>
+$rev
+</define-tag>
+<define-tag emacs-release-date>
+$release_date
+</define-tag>
+X
+close(O);
+
+open(O,">mmencoded_verilog-mode");
+print O <<"XX";
+MIME-version: 1.0
+Content-type: multipart/mixed; boundary="Message-Boundary"
+Content-transfer-encoding: 7BIT
+X-attachments: verilog-mode.el.gz
+
+--Message-Boundary
+Content-type: text/plain; charset=US-ASCII
+Content-transfer-encoding: 7BIT
+Content-description: Mail message body
+
+
++----------------------------------------------------------------+
+| Here is version $rev of verilog-mode for emacs! |
++----------------------------------------------------------------+
+XX
+open(IO, "<README");
+while (<IO>){
+ print O $_;
+}
+print O "\nLast few changes to the verilog-mode:\n";
+while(<LOG>) {
+ $log++ if (/^----------------------------$/);
+ print C $_;
+ last if ($log > 10);
+ print O $_;
+}
+while(<LOG>) {
+ print C $_;
+}
+close(LOG);
+print O <<"XX";
+
+--Message-Boundary
+Content-type: application/octet-stream; name="$attach_name"
+Content-Transfer-Encoding: base64
+Content-disposition: attachment; filename="$attach_name"
+
+$encoded_data
+--Message-Boundary--
+XX
+close(O);
+unlink("log");
diff --git a/make_mail.pl b/make_mail.pl
new file mode 100755
index 0000000..6f09f69
--- /dev/null
+++ b/make_mail.pl
@@ -0,0 +1,35 @@
+#!/usr/bin/perl
+$owner = "mac";
+$destination = "mac\@verilog.com";
+$verilog = "/home/mac/development/www.verilog.com/src/data/mmencoded_verilog-mode";
+
+if ( -d ".svn") {
+ open(LOG,"<log");
+ while(<LOG>) {
+ if (/^r([\d\.]+)/) {
+ $rev = $1;
+ last;
+ }
+ }
+} else {
+ open(LOG,"<log");
+ while(<LOG>) {
+ if (/^head: ([\d\.]+)$/) {
+ $rev = $1;
+ }
+ last if (/^description:$/);
+ }
+}
+open(VM, "< $verilog") || die "Can not open $verilog\n";
+open(SM, "|/usr/lib/sendmail -bm -f $owner -F \"Mike McNamara\" -t");
+
+# $destination = "mac\@verilog.com";
+# open(SM, "> mail.test");
+
+print SM "To: $destination\nReply-To: mac\@verilog.com\nBCC: mac\@verilog.com\nSubject: SUBSCRIPTION: Emacs Verilog-mode $rev\n";
+
+while(<VM>) {
+ print SM $_;
+}
+close(SM) || die "mailing dies with error: $!\n";
+close(VM);
diff --git a/makechangelog b/makechangelog
new file mode 100755
index 0000000..17e4e51
--- /dev/null
+++ b/makechangelog
@@ -0,0 +1,201 @@
+#!/usr/bin/perl -w # -*- Perl -*-
+# See copyright, etc in below POD section.
+######################################################################
+
+require 5.006_001;
+use Getopt::Long;
+#use Data::Dumper; $Data::Dumper::Indent=1; #Debug
+use IO::File;
+use IO::Dir;
+use Pod::Usage;
+use strict;
+use vars qw ($Debug);
+
+#======================================================================
+# main
+
+our $Opt_FileA;
+our $Opt_FileB;
+our $Opt_Git;
+our $Opt_Svn;
+
+autoflush STDOUT 1;
+autoflush STDERR 1;
+Getopt::Long::config ("no_auto_abbrev");
+if (! GetOptions (
+ "help" => \&usage,
+ "debug" => sub { $Debug = 1; },
+ "<>" => \&parameter,
+ "git!" => \$Opt_Git,
+ "svn!" => \$Opt_Svn,
+ )) {
+ die "%Error: Bad usage, try 'makechangelog --help'\n";
+}
+
+if ($Opt_Svn) {
+ my $now = $Opt_FileA;
+ $Opt_FileA = ".svn/text-base/${now}.svn-base";
+ $Opt_FileB = $now;
+} elsif ($Opt_Git) {
+ my $now = $Opt_FileA;
+ $Opt_FileA = "/tmp/mcl.$$";
+ $Opt_FileB = $now;
+ system("git show HEAD:${now} > $Opt_FileA");
+}
+read_file($Opt_FileA, $Opt_FileB);
+
+if ($Opt_Git) {
+ unlink($Opt_FileA);
+}
+
+#----------------------------------------------------------------------
+
+sub usage {
+ print '$Id$ ', "\n";
+ pod2usage(-verbose=>2, -exitval => 2);
+ exit (1);
+}
+
+sub parameter {
+ my $param = shift;
+ if (!$Opt_FileA) {
+ $Opt_FileA = $param;
+ } elsif (!$Opt_FileB) {
+ $Opt_FileB = $param;
+ } else {
+ die "%Error: Unknown parameter: $param\n";
+ }
+}
+
+#######################################################################
+
+sub read_file {
+ my $a = shift;
+ my $b = shift;
+ my @l = (read_lines($a), read_lines($b));
+
+ # Note we ignore whitespace
+ my $fh = IO::File->new("diff -b -c $a $b |") or die "%Error: $!,";
+ my @ln = (0,0);
+ my %difffuncs;
+ my $mode = 0;
+ my @difflines;
+ while (defined(my $line = $fh->getline)) {
+ my $fn = "";
+ if ($line =~ /^\*\*\* (\d+)/) {
+ $mode = 0;
+ $ln[$mode] = $1 - 1;
+ } elsif ($line =~ /^\-\-\- (\d+)/) {
+ $mode = 1;
+ $ln[$mode] = $1 - 1;
+ } elsif ($line =~ /^\*\*\*/) {
+ } elsif ($line =~ /^\-\-\-/) {
+ } else {
+ $ln[$mode]++;
+
+ if ($line =~ /^[!-+]/) {
+ my $checkline = substr($line,2);
+ chomp $checkline;
+ $checkline =~ s/;.*$//;
+ $checkline =~ s/[ \t\n]+$//;
+ if ($checkline ne "") {
+ $fn = $l[$mode][ $ln[$mode] ] || "Line#".$ln[$mode];
+ $difffuncs{$fn} = 1;
+ }
+ }
+ }
+ (my $fnq = $fn||"") =~ s/^verilog-/v-/g;
+ push @difflines, sprintf ("%05d: %-20s: %s",$ln[$mode],substr($fnq,0,20), $line);
+ }
+ $fh->close;
+
+ print "-*- Change-Log -*-\n\n";
+
+ my ($sec,$min,$hour,$mday,$mon,$year,$wday,$yday,$isdst) = localtime();
+ printf "<Put one line comment with trailing period here. This must be first line of commit message.>\n\n";
+
+ print "\t* verilog-mode.el";
+ my $f="";
+ my $sep = " (";
+ foreach my $func (sort keys %difffuncs) {
+ next if $func eq 'verilog-mode-release-date';
+ next if $func eq 'verilog-mode-version';
+ $f .= $sep.$func;
+ $sep = ", ";
+ }
+ $f .= ")" if $f;
+ print "$f:\n";
+
+ print "\n";
+ print "="x70,"\n";
+ print join('',@difflines);
+}
+
+sub read_lines {
+ my $filename = shift;
+
+ my @lines;
+
+ my $func;
+ my $fh = IO::File->new($filename) or die "%Error: $! $filename\n";
+ my $ln = 0;
+ while (defined(my $line = $fh->getline)) {
+ $ln++;
+ $func = undef if ($line =~ /^\(/);
+ $func = $1 if $line =~ /^\(def[---a-z]+\s+\'?(\S+)/;
+ $lines[$ln] = $func;
+ printf "%05d %-30s %s", $ln, $func||"", $line if $Debug;
+ }
+ $fh->close;
+ return \@lines;
+}
+
+#######################################################################
+__END__
+
+=pod
+
+=head1 NAME
+
+makechangelog -
+
+=head1 SYNOPSIS
+
+ ./makechangelog --svn verilog-mode.el
+
+=head1 DESCRIPTION
+
+dd
+
+=head1 ARGUMENTS
+
+=over 4
+
+=item --help
+
+Displays this message and program version and exits.
+
+=back
+
+=head1 DISTRIBUTION
+
+This is part of the L<http://www.veripool.org/> free Verilog EDA software
+tool suite. The latest version is available from CPAN and from
+L<http://www.veripool.org/>.
+
+Copyright 2008-2013 by Wilson Snyder. This package is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License or the Perl Artistic License.
+
+=head1 AUTHORS
+
+Wilson Snyder <wsnyder@wsnyder.org>
+
+=head1 SEE ALSO
+
+=cut
+
+######################################################################
+### Local Variables:
+### compile-command: "./makechangelog --svn verilog-mode.el"
+### End:
diff --git a/tests/abc.sv b/tests/abc.sv
new file mode 100644
index 0000000..427039a
--- /dev/null
+++ b/tests/abc.sv
@@ -0,0 +1,20 @@
+
+covergroup CB;
+ a: coverpoint tr.a
+ {
+ bins a0 = {0};
+ bins a1 = {1};
+ option.weight=0;
+ }
+ b: coverpoint tr.b {
+ bins b0 = {0};
+ bins b1 = {1};
+ option.weight=0;
+ }
+ ab: cross a,b {
+ bins a0b0 = binsof(a.a0) && binsof(b.b0);
+ bins a1b0 = binsof(a.a1) && binsof(b.b0);
+ bins b0 = binsof(b.b0);
+ }
+ endgroup // CB
+
diff --git a/tests/auto_delete_whitespace.v b/tests/auto_delete_whitespace.v
new file mode 100644
index 0000000..a540897
--- /dev/null
+++ b/tests/auto_delete_whitespace.v
@@ -0,0 +1,12 @@
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Wilson Snyder.
+
+// Note intentional whitespace on following line
+// SPACES
+module x;
+ // TAB
+endmodule
+
+// Local Variables:
+// verilog-auto-delete-trailing-whitespace: t
+// End:
diff --git a/tests/autoarg_comment.v b/tests/autoarg_comment.v
new file mode 100644
index 0000000..a05b058
--- /dev/null
+++ b/tests/autoarg_comment.v
@@ -0,0 +1,12 @@
+module autoarg_comment
+
+ // Copyright 1997-1998, blah, blah, blah
+
+ (/*AUTOARG*/);
+
+ //verilint 332 OFF //* Not all possible cases covered, but default case exists
+
+ input (* ATTRIB="val" *) income;
+ output outgo2;
+
+endmodule
diff --git a/tests/autoarg_jwells_comment.v b/tests/autoarg_jwells_comment.v
new file mode 100644
index 0000000..92afa5a
--- /dev/null
+++ b/tests/autoarg_jwells_comment.v
@@ -0,0 +1,11 @@
+module tahoetop(/*AUTOARG*/);
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ // End of automatics
+
+
+ // the pad instance to look like "pads pads (/*AUTOINST*/". Then at
+ // diff the new against the old. Finally delete /*AUTOINST*/. This will
+
+endmodule
diff --git a/tests/autoarg_quote_cmt.v b/tests/autoarg_quote_cmt.v
new file mode 100644
index 0000000..540b2ad
--- /dev/null
+++ b/tests/autoarg_quote_cmt.v
@@ -0,0 +1,8 @@
+// bug360
+module f (/*AUTOARG*/);
+
+always @* r = "test/*";
+
+ input x;
+
+endmodule
diff --git a/tests/autoarg_single.v b/tests/autoarg_single.v
new file mode 100644
index 0000000..4963961
--- /dev/null
+++ b/tests/autoarg_single.v
@@ -0,0 +1,13 @@
+// msg1354
+module f (/*AUTOARG*/);
+
+ output o2;
+ input z;
+ input a;
+ input q;
+ output o1;
+endmodule
+
+// Local Variables:
+// verilog-auto-arg-format:single
+// End:
diff --git a/tests/autoarg_sort_fedeli.v b/tests/autoarg_sort_fedeli.v
new file mode 100644
index 0000000..125bbcf
--- /dev/null
+++ b/tests/autoarg_sort_fedeli.v
@@ -0,0 +1,11 @@
+module (/*AUTOARG*/);
+ output o2;
+ input z;
+ input a;
+ input q;
+ output o1;
+endmodule
+
+// Local Variables:
+// verilog-auto-arg-sort:t
+// End:
diff --git a/tests/autoarg_string_bug259.v b/tests/autoarg_string_bug259.v
new file mode 100644
index 0000000..0f9431e
--- /dev/null
+++ b/tests/autoarg_string_bug259.v
@@ -0,0 +1,31 @@
+module bug_minimal
+ (input wire GND,
+ input wire VDD,
+
+ inout wire PIN1,
+ inout wire PIN2,
+ inout wire PIN3,
+ inout wire PIN4
+
+ /*AUTOARG*/);
+
+ // ----------------------------------------------------------------
+ /*AUTOWIRE*/
+
+ // ----------------------------------------------------------------
+ task force_value_to_1;
+ begin
+ $display("Enable test module checking ...");
+ force `value = 1'b1;
+ end
+ endtask
+
+ // ---------------------------------------------------------------
+ task force_value_to_0;
+ begin
+ $display("Disable test module checking ...");
+ force `value = 1'b0;
+ end
+ endtask
+
+endmodule
diff --git a/tests/autoarg_supply_bug438.v b/tests/autoarg_supply_bug438.v
new file mode 100644
index 0000000..af18a63
--- /dev/null
+++ b/tests/autoarg_supply_bug438.v
@@ -0,0 +1,17 @@
+module top
+ (
+ /*AUTOINPUT*/
+ );
+
+ /*AUTOWIRE*/
+
+ inst_module inst (/*AUTOINST*/);
+endmodule
+
+module inst_module (input supply0 VDD,
+ input supply1 VSS,
+ input non_supply,
+ input supply1 VDD_from_child
+ );
+
+endmodule
diff --git a/tests/autoascii_myers.v b/tests/autoascii_myers.v
new file mode 100644
index 0000000..c97729b
--- /dev/null
+++ b/tests/autoascii_myers.v
@@ -0,0 +1,76 @@
+module testit;
+ reg clk;
+ reg a_i;
+ reg b_i;
+
+ reg a_o;
+ reg b_o;
+ reg rst_n;
+
+ reg [7:0] shreg;
+
+
+ //== State enumeration
+ parameter [2:0] // synopsys enum state_info
+ SM_IDLE = 3'b000,
+ SM_SEND = 3'b001,
+ SM_WAIT1 = 3'b010;
+ //== State variables
+ reg [2:0] /* synopsys enum state_info */
+ state_r; /* synopsys state_vector state_r */
+ reg [2:0] /* synopsys enum state_info */
+ state_e1;
+
+ //== ASCII state decoding
+
+ /*AUTOASCIIENUM("state_r", "_stateascii_r", "sm_")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [39:0] _stateascii_r; // Decode of state_r
+ always @(state_r) begin
+ case ({state_r})
+ SM_IDLE: _stateascii_r = "idle ";
+ SM_SEND: _stateascii_r = "send ";
+ SM_WAIT1: _stateascii_r = "wait1";
+ default: _stateascii_r = "%Erro";
+ endcase
+ end
+ // End of automatics
+
+ initial begin
+ clk = 0;
+ a_i = 0;
+ b_i = 0;
+ rst_n = 0;
+ #20 rst_n = 1;
+ end
+ always #5 clk = ~clk;
+
+ always @(posedge clk or rst_n) begin
+ if (~rst_n) begin
+ a_o <= 0;
+ b_o <= 0;
+ shreg <= 8'b00110011;
+ end
+ else begin
+ a_o <= a_i;
+ b_o <= b_i;
+ shreg <= {shreg[6:0], shreg[7]};
+ end
+ end
+
+ task set_a_i;
+ begin
+ a_i = shreg[0];
+ end
+ endtask // set_a_i
+
+ always @(shreg & a_o) begin
+ set_a_i;
+ end
+
+ initial begin
+ $vcdpluson;
+ #500 $finish;
+ end
+
+endmodule // testit
diff --git a/tests/autoascii_peltan.v b/tests/autoascii_peltan.v
new file mode 100644
index 0000000..2c3f4b8
--- /dev/null
+++ b/tests/autoascii_peltan.v
@@ -0,0 +1,37 @@
+module autoascii_peltan
+ (
+ input test,
+ output [1:0] test_out
+ );
+
+`include "autoascii_peltan_inc.v"
+
+ // Duplicate of what's in _inc
+ localparam [3:0] /* synopsys enum xstate */
+ state0 = 4'h0;
+
+ wire [3:0] /* synopsys enum xstate */
+ xstate;
+
+ /* synopsys translate off */
+
+ /*AUTOASCIIENUM("xstate", "v_xstate")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [47:0] v_xstate; // Decode of xstate
+ always @(xstate) begin
+ case ({xstate})
+ state0: v_xstate = "state0";
+ state1: v_xstate = "state1";
+ default: v_xstate = "%Error";
+ endcase
+ end
+ // End of automatics
+
+ /* synopsys translate on */
+
+endmodule // sample
+
+// Local Variables:
+// verilog-library-directories:(".")
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests/autoascii_peltan_inc.v b/tests/autoascii_peltan_inc.v
new file mode 100644
index 0000000..3e59724
--- /dev/null
+++ b/tests/autoascii_peltan_inc.v
@@ -0,0 +1,3 @@
+localparam [3:0] /* synopsys enum xstate */
+ state0 = 4'h0,
+ state1 = 4'h1;
diff --git a/tests/autoasciienum_auto.v b/tests/autoasciienum_auto.v
new file mode 100644
index 0000000..b28d286
--- /dev/null
+++ b/tests/autoasciienum_auto.v
@@ -0,0 +1,22 @@
+// Code ok to distribute
+
+module autoasciienum_auto();
+
+ reg [2:0] /* auto enum sm_psm */ sm_psm;
+ reg [2:0] /* auto enum sm_ps2 */ sm_ps2;
+
+ localparam [2:0] // auto enum sm_psm
+ PSM_IDL = 0,
+ PSM_RST = 6,
+ PSM_ZOT = 7;
+
+ localparam [2:0] // auto enum sm_ps2
+ PS2_IDL = 0,
+ PS2_FOO = 1;
+
+ /*AUTOASCIIENUM("sm_psm", "_sm_psm__ascii", "_")*/
+ /*AUTOASCIIENUM("sm_ps2", "_sm_ps2__ascii", "_")*/
+
+endmodule : autoasciienum_auto
+
+
diff --git a/tests/autoasciienum_ex.v b/tests/autoasciienum_ex.v
new file mode 100644
index 0000000..3e74d7e
--- /dev/null
+++ b/tests/autoasciienum_ex.v
@@ -0,0 +1,33 @@
+module sm (/*AUTOARG*/
+ // Outputs
+ state_e1, state_r
+ );
+
+ output [2:0] state_e1;
+ output [2:0] state_r;
+
+ //== State enumeration
+ parameter [2:0] // synopsys enum state_info
+ SM_IDLE = 3'b000,
+ SM_ACT = 3'b010;
+ //== State variables
+ reg [2:0] /* synopsys enum state_info */
+ state_r; /* synopsys state_vector state_r */
+ reg [2:0] /* synopsys enum state_info */
+ state_e1;
+
+ //== ASCII state decoding
+
+ /*AUTOASCIIENUM("state_r", "_stateascii_r", "sm_")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [31:0] _stateascii_r; // Decode of state_r
+ always @(state_r) begin
+ case ({state_r})
+ SM_IDLE: _stateascii_r = "idle";
+ SM_ACT: _stateascii_r = "act ";
+ default: _stateascii_r = "%Err";
+ endcase
+ end
+ // End of automatics
+
+endmodule
diff --git a/tests/autoasciienum_frominc.v b/tests/autoasciienum_frominc.v
new file mode 100644
index 0000000..d572a20
--- /dev/null
+++ b/tests/autoasciienum_frominc.v
@@ -0,0 +1,36 @@
+module sm (/*AUTOARG*/);
+
+ //==================== Constant declarations ==============
+
+`include "autoasciienum_param.v"
+
+ //==================== Intermediate Variables =============
+
+ reg [3:0] /* synopsys enum En_C14ChipNum */ chip_r;
+
+ //==================== DEBUG ASCII CODE =========================
+
+ /*AUTOASCIIENUM("chip_r", "chip_r__ascii","Ep_C14ChipNum_")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [31:0] chip_r__ascii; // Decode of chip_r
+ always @(chip_r) begin
+ case ({chip_r})
+ EP_C14ChipNum_RNP: chip_r__ascii = "rnp ";
+ EP_C14ChipNum_SPP: chip_r__ascii = "spp ";
+ EP_C14ChipNum_SRP: chip_r__ascii = "srp ";
+ EP_C14ChipNum_SMM2: chip_r__ascii = "smm2";
+ EP_C14ChipNum_SMM: chip_r__ascii = "smm ";
+ EP_C14ChipNum_TTE: chip_r__ascii = "tte ";
+ EP_C14ChipNum_DLE: chip_r__ascii = "dle ";
+ EP_C14ChipNum_OASP: chip_r__ascii = "oasp";
+ default: chip_r__ascii = "%Err";
+ endcase
+ end
+ // End of automatics
+
+endmodule
+
+//==== Emacs verilog-mode controls ====
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests/autoasciienum_onehot.v b/tests/autoasciienum_onehot.v
new file mode 100644
index 0000000..0584f1a
--- /dev/null
+++ b/tests/autoasciienum_onehot.v
@@ -0,0 +1,43 @@
+// lint_checking MODLNM OFF
+
+module autoasciienum_onehot (
+ input clk,
+ input rst_n,
+ output ack
+);
+
+ localparam // synopsys enum state_info
+ IDLE = 0,
+ S1 = 1,
+ S2 = 2,
+ S3 = 3,
+ DONE = 4;
+
+ reg [4:0] // synopsys enum state_info
+ cur_state, nxt_state;
+
+ always @ (*) begin
+ nxt_state = 5'h0;
+
+ case (1'b1)
+ cur_state[IDLE] : nxt_state[S1] = 1'b1;
+ cur_state[S1] : nxt_state[S2] = 1'b1;
+ cur_state[S2] : nxt_state[S3] = 1'b1;
+ cur_state[S3] : nxt_state[DONE] = 1'b1;
+ cur_state[DONE] : nxt_state[DONE] = 1'b1;
+ endcase
+ end
+
+ always @ (posedge clk or negedge rst_n)
+ if (rst_n == 1'b0) begin
+ cur_state <= 'h1;
+ end
+ else begin
+ cur_state <= nxt_state;
+ end
+
+ assign ack = cur_state[DONE];
+
+ /*AUTOASCIIENUM("cur_state", "cur_state_ascii")*/
+
+endmodule
diff --git a/tests/autoasciienum_param.v b/tests/autoasciienum_param.v
new file mode 100644
index 0000000..33e7d8a
--- /dev/null
+++ b/tests/autoasciienum_param.v
@@ -0,0 +1,16 @@
+
+`ifdef NOTDEFINED
+module just_for_proper_indentation ();
+`endif
+
+ //Verilint 175 off //WARNING: Unused parameter
+
+ parameter // synopsys enum En_C14ChipNum
+ EP_C14ChipNum_OASP = 4'h0,
+ EP_C14ChipNum_DLE = 4'h2,
+ EP_C14ChipNum_TTE = 4'h3,
+ EP_C14ChipNum_SMM = 4'h4,
+ EP_C14ChipNum_SMM2 = 4'h5,
+ EP_C14ChipNum_SRP = 4'h6,
+ EP_C14ChipNum_SPP = 4'h7,
+ EP_C14ChipNum_RNP = 4'h8;
diff --git a/tests/autoasciienum_reed.v b/tests/autoasciienum_reed.v
new file mode 100644
index 0000000..807bab5
--- /dev/null
+++ b/tests/autoasciienum_reed.v
@@ -0,0 +1,22 @@
+
+module sm ();
+
+ localparam STATES = 7;
+
+ localparam /* synopsys enum states */
+ IDLE = 0, // '001
+ READ = 1, // '002
+ THINK = 2, // '004
+ SEND = 3, // '008
+ WAIT = 4, // '040
+ GET_ACK = 5, // '080
+ WAIT_REGBUS = 6; // '100
+
+ reg [STATES-1:0] /*synopsys enum states*/
+ state_i, state_r; /* synopsys state_vector state_r */
+
+ /*AUTOASCIIENUM("state_r","state_onehot,ascii_r","","onehot")*/
+
+ /*AUTOASCIIENUM("state_r","state_notonehot_ascii_r")*/
+
+endmodule
diff --git a/tests/autoasciienum_sm.v b/tests/autoasciienum_sm.v
new file mode 100644
index 0000000..09b9fee
--- /dev/null
+++ b/tests/autoasciienum_sm.v
@@ -0,0 +1,95 @@
+module sm (/*AUTOARG*/
+ // Outputs
+ state_r,
+ // Inputs
+ clk, rst_
+ );
+
+ //==================== Constant declarations ==============
+
+ parameter [2:0] // synopsys enum state_info
+ IDLE = 3'b000,
+ SEND = 3'b001,
+ WAIT1 = 3'b010,
+ UPDATE1 = 3'b011,
+ WAIT2 = 3'b100;
+
+ parameter [2:0] /* synopsys enum state_info */ UPDATE2 = 3'b101;
+
+ parameter [2:0] NOT_A_STATE_ELEMENT = 3'b101;
+
+ parameter [2:0] /* synopsys enum other */
+ A_OTHER_STATE_ELEMENT = 3'b101;
+
+ //==================== Input Signals ======================
+
+ input clk; // System clock signal
+ input rst_;
+
+ //==================== Output Signals =====================
+
+ // s_ynopsys requires the enum comment between the keyword and the symbol While this seems silly,
+ // verilog requires this also to avoid misleading people that also use their tools.
+
+ output [2:0] state_r; // SM State information (to GPF)
+
+ //==================== Intermediate Variables =============
+
+ reg [2:0] /* synopsys enum state_info */ state_r; /* synopsys state_vector state_r */
+ reg [2:0] /* synopsys enum state_info */ state_e1; // next state of state-machine
+
+ //==================== Code Begin =========================
+
+ always @(/*AUTOSENSE*/state_r) begin
+ case(state_r) // synopsys full_case parallel_case
+ IDLE: begin
+ state_e1 = SEND;
+ end
+ SEND: begin
+ state_e1 = WAIT1;
+ end
+ WAIT1: begin
+ state_e1 = UPDATE1;
+ end
+ UPDATE1: begin
+ state_e1 = UPDATE2;
+ end
+ WAIT2: begin
+ state_e1 = UPDATE2;
+ end
+
+ UPDATE2: begin
+ state_e1 = IDLE;
+ end
+ default: state_e1 = state_r;
+ endcase
+ end
+
+ always @(posedge clk or negedge rst_) begin
+ if (~rst_) begin
+ state_r <= #0 IDLE;
+ end
+ else begin
+ state_r <= #0 state_e1;
+ end
+ end
+
+ //==================== DEBUG ASCII CODE =========================
+
+ /*AUTOASCIIENUM("state_r", "_stateascii_r")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [55:0] _stateascii_r; // Decode of state_r
+ always @(state_r) begin
+ case ({state_r})
+ IDLE: _stateascii_r = "idle ";
+ SEND: _stateascii_r = "send ";
+ WAIT1: _stateascii_r = "wait1 ";
+ UPDATE1: _stateascii_r = "update1";
+ WAIT2: _stateascii_r = "wait2 ";
+ UPDATE2: _stateascii_r = "update2";
+ default: _stateascii_r = "%Error ";
+ endcase
+ end
+ // End of automatics
+
+endmodule
diff --git a/tests/autoconst_gesmith.v b/tests/autoconst_gesmith.v
new file mode 100644
index 0000000..281fb1d
--- /dev/null
+++ b/tests/autoconst_gesmith.v
@@ -0,0 +1,20 @@
+module(/*AUTOARG*/)
+
+
+ always @(`ot.BOZ or
+ /*AUTOSENSE*/b)
+ begin
+ /*AUTO_CONSTANT(`ot.BOC) */
+ i = b;
+ c = `ot.BOC;
+ d = `ot.BOZ;
+ end
+
+ always @(/*AUTOSENSE*/b)
+ begin
+ /*AUTO_CONSTANT(ot.BOB) */
+ i = b;
+ c = ot.BOB;
+ end
+
+endmodule
diff --git a/tests/autoconstant_gooch.v b/tests/autoconstant_gooch.v
new file mode 100644
index 0000000..7015d10
--- /dev/null
+++ b/tests/autoconstant_gooch.v
@@ -0,0 +1,102 @@
+module autoconstant_gooch
+ (/*AUTOARG*/
+ // Outputs
+ out1, out2, out3,
+ // Inputs
+ in1, in2, in3
+ );
+
+ input [3:0] in1;
+ input [3:0] in2;
+ input [3:0] in3;
+ output [3:0] out1;
+ reg [3:0] out1;
+ output [3:0] out2;
+ reg [3:0] out2;
+ output [3:0] out3;
+ reg [3:0] out3;
+
+
+
+ always @(/*AUTOSENSE*/in1 or in2 or in3)
+ begin
+ case (in1)
+ 4'b0001 : begin
+ out1 = in2;
+ end
+ 4'b0010 : begin
+ out1 = in2 + in3;
+ end
+ 4'b0100 : begin
+ out1 = in2 - in3;
+ end
+ 4'b1000 : begin
+ out1 = in2;
+ end
+ default : begin
+ out1 = {4{1'b0}};
+ end
+ endcase
+ end
+
+
+ always @(/*AUTOSENSE*/in1 or in2 or in3)
+ begin
+ case (in1)
+ 4'b0001 : begin
+ out2 = in2;
+ end
+ 4'b0010 : begin
+ out2 = in2 + in3;
+ end
+ 4'b0100 : begin
+ out2 = in2 - in3;
+ end
+ 4'b1000 : begin
+ out2 = in2;
+ end
+ default : begin
+ out2 = {4{1'b0}};
+ end
+ endcase
+ end
+
+
+ always @(/*AUTOSENSE*/in1 or in2 or in3)
+ begin
+ /* AUTO_CONSTANT( temp )*/
+ /* AxxxUTO_CONSTANT temp */
+ out3 = in1 + in2;
+ temp2 = temp;
+
+ // ERROR here - above constant definition is not
+ // correct - no braces - and so parser keeps looking
+ // for the first variable it finds between a pair of
+ // braces - in this case, in2. This in2 is now a
+ // "constant" and is removed from all sensitivity lists.
+ // ( in2 )
+
+ case (in1)
+ 4'b0001 : begin
+ out3 = in2;
+ end
+ 4'b0010 : begin
+ out3 = in2 + in3;
+ end
+ 4'b0100 : begin
+ out3 = in2 - in3;
+ end
+ 4'b1000 : begin
+ out3 = in2;
+ end
+ default : begin
+ out3 = {4{1'b0}};
+ end
+ endcase
+ end
+
+
+
+endmodule
+
+
diff --git a/tests/autoinout.v b/tests/autoinout.v
new file mode 100644
index 0000000..97527cb
--- /dev/null
+++ b/tests/autoinout.v
@@ -0,0 +1,32 @@
+module io1_sub(
+ /*AUTOARG*/);
+
+ /*AUTOINPUT*/
+
+ /*AUTOINOUT*/
+
+ /*AUTOOUTPUT*/
+
+ /* inst AUTO_TEMPLATE (
+ .lower_inb (1'b1),
+ )*/
+
+
+ instio instio (/*AUTOINST*/);
+
+endmodule
+
+module instio (/*AUTOARG*/);
+
+ input lower_ina;
+ inout lower_io;
+ output lower_out;
+ input sec_ina;
+ inout sec_io;
+ output sec_out;
+
+ wire lower_out = lower_ina | lower_io;
+ wire sec_out = sec_ina | sec_io;
+
+endmodule
+
diff --git a/tests/autoinout_lovell.v b/tests/autoinout_lovell.v
new file mode 100644
index 0000000..98583ed
--- /dev/null
+++ b/tests/autoinout_lovell.v
@@ -0,0 +1,32 @@
+// Matthew Lovell <lovell@hp.com>
+
+module top_test(/*AUTOARG*/);
+
+ /*AUTOOUTPUT*/
+
+ /*AUTOINPUT*/
+
+ /* leaf AUTO_TEMPLATE (
+ // Original reported bug
+ .a ({aa, test2.test3.no, test3.test4.no2}),
+ // Others
+ .b ( ~ ba),
+ .c ({\c-escaped-nvec , \c-escaped-vec [2:0] }),
+ .d ({da,~ db [1:0] , dc [2:0]}),
+ // Msg246
+ .e ({{4*1{1'b0}},Z_int[15:0],{1'b4{1'b0}},Z0_int[7:0]}),
+ .f (hi.ear.ial),
+ );
+ */
+ leaf l1 (/*AUTOINST*/);
+endmodule // top_test
+
+module leaf(/*AUTOARG*/);
+ output a;
+ output b;
+ input c;
+ input d;
+ input e;
+ input f;
+ input z;
+endmodule
diff --git a/tests/autoinout_ma.v b/tests/autoinout_ma.v
new file mode 100644
index 0000000..52c3468
--- /dev/null
+++ b/tests/autoinout_ma.v
@@ -0,0 +1,16 @@
+module foo
+ (
+ input soutb,
+ output sina,
+
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ ) ;
+ bar i_bar(/*AUTOINST*/);
+
+endmodule // foo
+
+module bar (/*AUTOARG*/) ;
+ input sina, sinb;
+ output souta, soutb;
+endmodule // bar
diff --git a/tests/autoinout_moller.v b/tests/autoinout_moller.v
new file mode 100644
index 0000000..a2dc5d4
--- /dev/null
+++ b/tests/autoinout_moller.v
@@ -0,0 +1,49 @@
+module a ( /*AUTOARG*/
+ // Outputs
+ o1,
+ // Inouts
+ io1,
+ // Inputs
+ i1
+ ) ;
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input i1; // To b of b.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output o1; // From b of b.v
+ // End of automatics
+
+ /*AUTOINOUT*/
+ // Beginning of automatic inouts (from unused autoinst inouts)
+ inout io1; // To/From b of b.v
+ // End of automatics
+
+ b b
+ (/*AUTOINST*/
+ // Outputs
+ .o1 (o1),
+ // Inouts
+ .io1 (io1),
+ // Inputs
+ .i1 (i1));
+
+endmodule // a
+
+module b (/*AUTOARG*/
+ // Outputs
+ o1,
+ // Inouts
+ io1,
+ // Inputs
+ i1
+ ) ;
+
+ input i1 ;
+ output o1 ;
+ inout io1 ;
+
+endmodule // b
diff --git a/tests/autoinout_regexp.v b/tests/autoinout_regexp.v
new file mode 100644
index 0000000..92d326d
--- /dev/null
+++ b/tests/autoinout_regexp.v
@@ -0,0 +1,32 @@
+module io1_sub(
+ /*AUTOARG*/);
+
+ /*AUTOINPUT("^s")*/
+
+ /*AUTOINOUT("^s")*/
+
+ /*AUTOOUTPUT("^s")*/
+
+ /* inst AUTO_TEMPLATE (
+ .lower_inb (1'b1),
+ )*/
+
+
+ instio instio (/*AUTOINST*/);
+
+endmodule
+
+module instio (/*AUTOARG*/);
+
+ input lower_ina;
+ inout lower_io;
+ output lower_out;
+ input sec_ina;
+ inout sec_io;
+ output sec_out;
+
+ wire lower_out = lower_ina | lower_io;
+ wire sec_out = sec_ina | sec_io;
+
+endmodule
+
diff --git a/tests/autoinout_v2k.v b/tests/autoinout_v2k.v
new file mode 100644
index 0000000..fef7854
--- /dev/null
+++ b/tests/autoinout_v2k.v
@@ -0,0 +1,55 @@
+module parent
+ (
+
+ /*AUTOINPUT*/
+
+ /*AUTOOUTPUT*/
+
+ /*AUTOINOUT*/
+ );
+
+
+ /*AUTOWIRE*/
+
+
+ child_a sub_module
+ (/*AUTOINST*/);
+
+ child_b sub_module
+ (/*AUTOINST*/);
+
+endmodule // parent
+
+module child_a
+ (
+ input [3:0] a,
+ input [3:0] a2,
+ input [3:0] a3,
+ input [3:0] a4,
+ inout [5:0] c,
+ inout [5:0] c2,
+ inout c3,
+ output [2:0] b,
+ output [2:0] b2,
+ output [2:0] b3,
+ output [2:0] b4,
+ input clk,
+ output d
+ );
+endmodule
+
+
+module child_b
+ (
+ output [3:0] a,
+ output [3:0] a4,
+ inout [5:0] c,
+ inout [5:0] c2,
+ inout c3,
+ input [2:0] b,
+ input [2:0] b2,
+ input [2:0] b3,
+ input [2:0] b4,
+ input clk
+ );
+endmodule
diff --git a/tests/autoinoutcomp.v b/tests/autoinoutcomp.v
new file mode 100644
index 0000000..da211b3
--- /dev/null
+++ b/tests/autoinoutcomp.v
@@ -0,0 +1,11 @@
+module autoinoutmodule (/*AUTOARG*/);
+
+ output lower_inb;
+
+ /*AUTOINOUTCOMP("inst")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+
+ wire lower_out = lower_ina | lower_inb;
+
+endmodule
+
diff --git a/tests/autoinoutin.v b/tests/autoinoutin.v
new file mode 100644
index 0000000..57e4410
--- /dev/null
+++ b/tests/autoinoutin.v
@@ -0,0 +1,6 @@
+module autoinoutin (/*AUTOARG*/);
+
+ /*AUTOINOUTIN("inst")*/
+
+endmodule
+
diff --git a/tests/autoinoutmodport_bourduas_type.v b/tests/autoinoutmodport_bourduas_type.v
new file mode 100644
index 0000000..0cc4beb
--- /dev/null
+++ b/tests/autoinoutmodport_bourduas_type.v
@@ -0,0 +1,31 @@
+//-*- mode: Verilog; verilog-indent-level: 3; indent-tabs-mode: nil; tab-width: 1 -*-
+
+module apl2c_connect(autoinoutmodport_type_intf ctl_i,
+ /*AUTOINOUTMODPORT("autoinoutmodport_type_intf", "ctl_cb")*/
+);
+
+ /*AUTOASSIGNMODPORT("autoinoutmodport_type_intf", "ctl_cb", "ctl_i")*/
+
+endmodule
+
+interface autoinoutmodport_type_intf(input logic clk, input logic rst_n);
+ import uvm_pkg::*;
+ import ap_defines::*;
+
+ logic [4:0] inst;
+ isel_t isel;
+ logic replay;
+
+ clocking ctl_cb @(posedge clk);
+ input inst;
+ input isel;
+ input replay;
+ endclocking: ctl_cb
+
+ modport ctl_mp(clocking ctl_cb);
+
+endinterface
+
+// Local Variables:
+// verilog-typedef-regexp:"_t"
+// End:
diff --git a/tests/autoinoutmodule.v b/tests/autoinoutmodule.v
new file mode 100644
index 0000000..3ba8b2c
--- /dev/null
+++ b/tests/autoinoutmodule.v
@@ -0,0 +1,19 @@
+module autoinoutmodule (/*AUTOARG*/
+ // Outputs
+ lower_out,
+ // Inputs
+ lower_inb, lower_ina
+ );
+
+ /*AUTOINOUTMODULE("inst")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output lower_out;
+ input lower_inb;
+ input lower_ina;
+ // End of automatics
+ // Beginning of automatic in/out/inouts (from specific module)
+
+ wire lower_out = lower_ina | lower_inb;
+
+endmodule
+
diff --git a/tests/autoinoutmodule_iface.v b/tests/autoinoutmodule_iface.v
new file mode 100644
index 0000000..b090eac
--- /dev/null
+++ b/tests/autoinoutmodule_iface.v
@@ -0,0 +1,11 @@
+// bug721
+module my_core
+ (
+ /*AUTOINOUTMODULE("autoinoutmodule_iface_sub")*/
+ /*AUTOINOUT*/
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+);
+/*AUTOWIRE*/
+
+endmodule
diff --git a/tests/autoinoutmodule_iface_sub.v b/tests/autoinoutmodule_iface_sub.v
new file mode 100644
index 0000000..96b404c
--- /dev/null
+++ b/tests/autoinoutmodule_iface_sub.v
@@ -0,0 +1,4 @@
+module autoinoutmodule_iface_sub
+ (my_svi.master my_svi_port,
+ );
+endmodule
diff --git a/tests/autoinoutmodule_ign.v b/tests/autoinoutmodule_ign.v
new file mode 100644
index 0000000..2d37443
--- /dev/null
+++ b/tests/autoinoutmodule_ign.v
@@ -0,0 +1,8 @@
+module autoinoutmodule (/*AUTOARG*/);
+
+ /*AUTOINOUTMODULE("inst","\(ina\|out\)","","ina")*/
+
+ wire lower_out = lower_ina;
+
+endmodule
+
diff --git a/tests/autoinoutmodule_re2.v b/tests/autoinoutmodule_re2.v
new file mode 100644
index 0000000..1d0da2a
--- /dev/null
+++ b/tests/autoinoutmodule_re2.v
@@ -0,0 +1,10 @@
+module autoinoutmodule_re2 (/*AUTOARG*/);
+
+ /*AUTOINOUTMODULE("inst","","input.*")*/
+
+ /*AUTOINOUTMODULE("inst","","output.*")*/
+
+ wire lower_out = lower_ina;
+
+endmodule
+
diff --git a/tests/autoinoutmodule_regexp.v b/tests/autoinoutmodule_regexp.v
new file mode 100644
index 0000000..2eec4b9
--- /dev/null
+++ b/tests/autoinoutmodule_regexp.v
@@ -0,0 +1,8 @@
+module autoinoutmodule (/*AUTOARG*/);
+
+ /*AUTOINOUTMODULE("inst","\(ina\|out\)")*/
+
+ wire lower_out = lower_ina;
+
+endmodule
+
diff --git a/tests/autoinoutmodule_v2k.v b/tests/autoinoutmodule_v2k.v
new file mode 100644
index 0000000..36df410
--- /dev/null
+++ b/tests/autoinoutmodule_v2k.v
@@ -0,0 +1,8 @@
+module autoinoutmodule (
+ /*AUTOINOUTMODULE("inst")*/
+ );
+
+ wire lower_out = lower_ina | lower_inb;
+
+endmodule
+
diff --git a/tests/autoinoutparam.v b/tests/autoinoutparam.v
new file mode 100644
index 0000000..8d3d106
--- /dev/null
+++ b/tests/autoinoutparam.v
@@ -0,0 +1,8 @@
+module autoinoutparam (/*AUTOARG*/);
+
+ /*AUTOINOUTPARAM("inst","param1")*/
+
+ /*AUTOINOUTPARAM("inst")*/
+
+endmodule
+
diff --git a/tests/autoinput_array_bug294.v b/tests/autoinput_array_bug294.v
new file mode 100644
index 0000000..7d765e2
--- /dev/null
+++ b/tests/autoinput_array_bug294.v
@@ -0,0 +1,21 @@
+module mod1(input logic [1:0] reg1[4],
+ input logic reg2[5][6],
+ input logic [1:0] [3:0] [2:0] reg4);
+endmodule
+
+module mod2(output logic [1:0] reg1[4],
+ output logic [1:0] [3:0] [2:0] reg4);
+endmodule
+
+module dut (
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ );
+
+ /*AUTOWIRE*/
+
+ mod1 foo_i(/*AUTOINST*/);
+
+ /* drv_i AUTO_TEMPLATE (.reg1(reg1[]), );*/
+ mod2 drv_i(/*AUTOINST*/);
+endmodule
diff --git a/tests/autoinput_asharma.v b/tests/autoinput_asharma.v
new file mode 100644
index 0000000..569ee1f
--- /dev/null
+++ b/tests/autoinput_asharma.v
@@ -0,0 +1,30 @@
+module io1_sub(
+ /*AUTOARG*/
+ // Outputs
+ lower_out,
+ // Inputs
+ lower_ina
+ );
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input lower_ina; // To inst of inst.v
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output lower_out; // From inst of inst.v
+ // End of automatics
+
+ /* inst AUTO_TEMPLATE (
+ .lower_inb (1'b1),
+ )*/
+
+
+ inst inst (/*AUTOINST*/
+ // Outputs
+ .lower_out (lower_out),
+ // Inputs
+ .lower_inb (1'b1), // Templated
+ .lower_ina (lower_ina));
+
+endmodule
diff --git a/tests/autoinput_asharma_v2k.v b/tests/autoinput_asharma_v2k.v
new file mode 100644
index 0000000..f2299a5
--- /dev/null
+++ b/tests/autoinput_asharma_v2k.v
@@ -0,0 +1,13 @@
+module io1_sub(
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ );
+
+ /* inst AUTO_TEMPLATE (
+ .lower_inb (1'b1),
+ )*/
+
+
+ inst inst (/*AUTOINST*/);
+
+endmodule
diff --git a/tests/autoinput_concat_ignore.v b/tests/autoinput_concat_ignore.v
new file mode 100644
index 0000000..4bf95a2
--- /dev/null
+++ b/tests/autoinput_concat_ignore.v
@@ -0,0 +1,52 @@
+module xyz (/*AUTOARG*/);
+
+ /*AUTOINPUT*/
+
+ /*AUTOOUTPUT*/
+
+ /*AUTOWIRE*/
+
+ /* abc AUTO_TEMPLATE
+ (
+ // Outputs
+ .signal_c (signal_c),
+ // Inputs
+ .signal_a ({1'b0, signal_f}),
+ .signal_b (signal_b[2:0]));
+ */
+
+ abc u_abc
+ (/*AUTOINST*/);
+
+ /* def AUTO_TEMPLATE
+ (// Outputs
+ .signal_f (signal_f),
+ // Inputs
+ .signal_d ({1'b1, signal_c}),
+ .signal_e ({2'b11, signal_e}));
+ */
+
+ def u_def
+ (/*AUTOINST*/);
+
+endmodule // xyz
+
+module abc (/*AUTOARG*/);
+
+ input [1:0] signal_a;
+ input [2:0] signal_b;
+ output signal_c;
+
+endmodule // abc
+
+module def (/*AUTOARG*/);
+
+ input [1:0] signal_d;
+ input [2:0] signal_e;
+ output signal_f;
+
+endmodule // def
+
+// Local Variables:
+// verilog-auto-ignore-concat: t
+// End:
diff --git a/tests/autoinput_concat_lau.v b/tests/autoinput_concat_lau.v
new file mode 100644
index 0000000..313c2d0
--- /dev/null
+++ b/tests/autoinput_concat_lau.v
@@ -0,0 +1,26 @@
+module sub1 (/*AUTOARG*/);
+
+ input [3:0] bus1;
+ inout [3:0] busout;
+
+ wire busout = bus1;
+
+endmodule
+
+
+module autoinput_concat_lau
+ (
+ /*AUTOINPUT*/
+ /*AUTOINOUT*/
+ );
+
+ /* sub1 AUTO_TEMPLATE (
+ .busout ({2'b0,fooout[1:0]}),
+ .bus1 ({2'b0,~foo[1:0]}),
+ );
+ */
+
+ sub1 sub1 (/*AUTOINST*/);
+
+endmodule
+
diff --git a/tests/autoinput_concat_lau2.v b/tests/autoinput_concat_lau2.v
new file mode 100644
index 0000000..653469d
--- /dev/null
+++ b/tests/autoinput_concat_lau2.v
@@ -0,0 +1,48 @@
+module xyz (/*AUTOARG*/);
+
+ /*AUTOINPUT*/
+
+ /*AUTOOUTPUT*/
+
+ /*AUTOWIRE*/
+
+ /* abc AUTO_TEMPLATE
+ (
+ // Outputs
+ .signal_c (signal_c),
+ // Inputs
+ .signal_a ({1'b0, signal_f}),
+ .signal_b (signal_b[2:0]));
+ */
+
+ abc u_abc
+ (/*AUTOINST*/);
+
+ /* def AUTO_TEMPLATE
+ (// Outputs
+ .signal_f (signal_f),
+ // Inputs
+ .signal_d ({1'b1, signal_c}),
+ .signal_e ({2'b11, signal_e}));
+ */
+
+ def u_def
+ (/*AUTOINST*/);
+
+endmodule // xyz
+
+module abc (/*AUTOARG*/);
+
+ input [1:0] signal_a;
+ input [2:0] signal_b;
+ output signal_c;
+
+endmodule // abc
+
+module def (/*AUTOARG*/);
+
+ input [1:0] signal_d;
+ input [2:0] signal_e;
+ output signal_f;
+
+endmodule // def
diff --git a/tests/autoinput_none.v b/tests/autoinput_none.v
new file mode 100644
index 0000000..50d0fc1
--- /dev/null
+++ b/tests/autoinput_none.v
@@ -0,0 +1,30 @@
+// Julian Gorfajn
+
+`default_nettype none
+
+module top
+ (
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output wire o, // From sub of Sub.v
+ // End of automatics
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input wire i // To sub of Sub.v
+ // End of automatics
+ );
+
+ Sub sub (/*AUTOINST*/
+ // Outputs
+ .o (o),
+ // Inputs
+ .i (i));
+endmodule
+
+module Sub (input i, output o);
+endmodule
+
+// Local Variables:
+// verilog-auto-declare-nettype: "wire"
+// End:
diff --git a/tests/autoinput_paren.v b/tests/autoinput_paren.v
new file mode 100644
index 0000000..ac2678a
--- /dev/null
+++ b/tests/autoinput_paren.v
@@ -0,0 +1,10 @@
+module foo (/*AUTOARG*/) ;
+ /*AUTOINPUT("ab\(c\|d\)")*/
+ bar i_bar(/*AUTOINST*/);
+
+endmodule // foo
+
+module bar (/*AUTOARG*/) ;
+ input abc,abd,bca;
+ output aaa;
+endmodule // bar
diff --git a/tests/autoinsertlast_1.v b/tests/autoinsertlast_1.v
new file mode 100644
index 0000000..9544d08
--- /dev/null
+++ b/tests/autoinsertlast_1.v
@@ -0,0 +1,12 @@
+module ExampInsertLisp;
+
+ /*AUTOINSERTLAST(my-verilog-insert-hello "world")*/
+
+endmodule
+/*
+ Local Variables:
+ eval:
+ (defun my-verilog-insert-hello (who)
+ (insert (concat "initial $write(\"hello " who "\");\n")))
+ End:
+*/
diff --git a/tests/autoinst_2k_fredriksen.v b/tests/autoinst_2k_fredriksen.v
new file mode 100644
index 0000000..98ef916
--- /dev/null
+++ b/tests/autoinst_2k_fredriksen.v
@@ -0,0 +1,21 @@
+module top ();
+
+
+ sub sub(/*AUTOINST*/
+ // Outputs
+ .b (b[PARAM2:0]),
+ // Inputs
+ .a (a[PARAM1:0]));
+
+endmodule // top
+
+module sub
+ #(parameter PARAM1=2,
+ PARAM2=3,
+ PARAM3=6)
+ ( input wire [PARAM1:0] a,
+ output reg [PARAM2:0] b
+ );
+
+
+endmodule
diff --git a/tests/autoinst_ams_vorwerk.v b/tests/autoinst_ams_vorwerk.v
new file mode 100644
index 0000000..187ffb6
--- /dev/null
+++ b/tests/autoinst_ams_vorwerk.v
@@ -0,0 +1,27 @@
+module autoinst_ams_vorwerk;
+
+ latch latch (/*AUTOINST*/);
+
+endmodule
+
+module latch (/*AUTOARG*/);
+
+`ifdef __VAMS_ENABLE__
+ output (* integer groundSensitivity="gnd "; integer supplySensitivity="vdd "; *) q;
+ `else
+ output q;
+`endif
+
+`ifdef __VAMS_ENABLE__
+ input (* integer groundSensitivity="gnd "; integer supplySensitivity="vdd "; *) en;
+ `else
+ input en;
+`endif
+
+`ifdef __VAMS_ENABLE__
+ input (* integer groundSensitivity="gnd "; integer supplySensitivity="vdd "; *) d;
+ `else
+ input d;
+`endif
+
+endmodule
diff --git a/tests/autoinst_array.v b/tests/autoinst_array.v
new file mode 100644
index 0000000..7f3987d
--- /dev/null
+++ b/tests/autoinst_array.v
@@ -0,0 +1,36 @@
+// bug637
+
+module submod_a
+ (
+ //Inputs
+ input wire signed [15:0] serial_in,
+ //Outputs
+ output wire signed [15:0] parallel_out [0:7]
+ );
+endmodule
+
+module submod_b
+ (
+ //Inputs
+ input wire signed [15:0] parallel_out [0:7],
+ //Outputs
+ output wire signed [15:0] final_out [0:7]
+ );
+endmodule
+
+module top
+ (
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ );
+
+ /*AUTOLOGIC*/
+
+ submod_a a_inst
+ (/*AUTOINST*/);
+
+ submod_b b_inst
+ (/*AUTOINST*/);
+
+
+endmodule
diff --git a/tests/autoinst_array_braket.v b/tests/autoinst_array_braket.v
new file mode 100644
index 0000000..3623c75
--- /dev/null
+++ b/tests/autoinst_array_braket.v
@@ -0,0 +1,41 @@
+module sub(output logic [1:-1] oned,
+ output logic [1:-1] [2:-1] twod,
+ output logic [1:-1] [2:-1] [3:-3] threed);
+endmodule
+
+module dut (
+ );
+
+ /*AUTOWIRE*/
+
+ /* sub AUTO_TEMPLATE ();
+ */
+
+ sub sub1 (/*AUTOINST*/);
+
+ /* sub AUTO_TEMPLATE (
+ .oned (b_oned[]),
+ .twod (b_twod[]),
+ .threed (b_threed[]));
+ */
+
+ // NOTE this results in the wrong declaration for b_twod/b_threed
+ sub subb (/*AUTOINST*/);
+
+ /* sub AUTO_TEMPLATE (
+ .oned (c_oned[]),
+ .twod (c_twod[x][]),
+ .threed (c_threed[x][y][]));
+ */
+
+ sub subc (/*AUTOINST*/);
+
+ /* sub AUTO_TEMPLATE (
+ .oned (d_oned[][]),
+ .twod (d_twod[][]),
+ .threed (d_threed[][]));
+ */
+
+ sub subd (/*AUTOINST*/);
+
+endmodule
diff --git a/tests/autoinst_atregexp.v b/tests/autoinst_atregexp.v
new file mode 100644
index 0000000..4f13c77
--- /dev/null
+++ b/tests/autoinst_atregexp.v
@@ -0,0 +1,20 @@
+module ex;
+
+ /* autoinst_paramover_sub AUTO_TEMPLATE "u_\(.*\)" (
+ .a(inA_@[]),
+ .b(outA_@[]),
+ );*/
+
+ autoinst_paramover_sub u_foo(/*AUTOINST*/);
+ autoinst_paramover_sub u_bar(/*AUTOINST*/);
+ autoinst_paramover_sub u_baz(/*AUTOINST*/);
+
+ /* autoinst_paramover_sub AUTO_TEMPLATE (
+ .a(inN_@[]),
+ .b(outN_@[]),
+ );*/
+
+ autoinst_paramover_sub u_0_2(/*AUTOINST*/);
+ autoinst_paramover_sub u_1_3(/*AUTOINST*/);
+
+endmodule
diff --git a/tests/autoinst_belkind_concat.v b/tests/autoinst_belkind_concat.v
new file mode 100644
index 0000000..c1a2df7
--- /dev/null
+++ b/tests/autoinst_belkind_concat.v
@@ -0,0 +1,24 @@
+module aaa (/*AUTOARG*/);
+
+ /*AUTOOUTPUT*/
+ /*AUTOINPUT*/
+ /*AUTOWIRE*/
+
+ wire u0, u1, z0, z1;
+ /*
+ bbb AUTO_TEMPLATE (
+ .xo0 ({(u0), y0}),
+ .xo1 ({y1, (u1)}),
+ .xi0 ({(z0), y2}),
+ .xi1 ({y3, (z1)}),
+ );
+ */
+ bbb bbb (/*AUTOINST*/);
+
+endmodule // aaa
+
+module bbb (/*AUTOARG*/);
+ output [1:0] xo0, xo1;
+ input [1:0] xi0, xi1;
+ /*AUTOTIEOFF*/
+endmodule // bbb
diff --git a/tests/autoinst_bits_lba.v b/tests/autoinst_bits_lba.v
new file mode 100644
index 0000000..59e7f8b
--- /dev/null
+++ b/tests/autoinst_bits_lba.v
@@ -0,0 +1,27 @@
+module lba
+
+ (/*AUTOnotARG*/
+ // Outputs
+ );
+
+
+ /* autoinst_bits_lba_gi AUTO_TEMPLATE (
+ .WWCmdI (WWCmdI[]));
+ */
+
+ autoinst_bits_lba_gi gi (/*AUTOINST*/
+ // Outputs
+ .WWCmdI (WWCmdI[8:0]), // Templated
+ .WWADI (WWADI[31:0]),
+ // Inouts
+ .WWADB (WWADB[31:0]),
+ .WWCmdB (WWCmdB[8:0]),
+ // Inputs
+ .CLK (CLK),
+ .WWADoe (WWADoe),
+ .WWCoe (WWCoe),
+ .WWCmdIfOE (WWCmdIfOE[8:0]),
+ .WWADHold (WWADHold),
+ .iWWADO (iWWADO[31:0]));
+
+endmodule
diff --git a/tests/autoinst_bits_lba_gi.v b/tests/autoinst_bits_lba_gi.v
new file mode 100644
index 0000000..3261f4d
--- /dev/null
+++ b/tests/autoinst_bits_lba_gi.v
@@ -0,0 +1,109 @@
+module autoinst_bits_lba_gi
+
+ // ==xxxxxxx==
+
+ // xxxxxxxxx 1997-1998, xxxxx xxx.
+ // xxx xxxxxx xxxxxxxx
+
+ // ****************************************************************** /
+ // ****************************************************************** /
+ // xxxxx, xxxxxxxxxxxx
+ // xxxxxxx: xxx-4080
+ // xxxxxx: xxx xxxxxxx
+ // xxxxx: xxxxxxx 16, 1998
+ // ******************************************************************* /
+ // ******************************************************************* /
+ // xxxx xxxx: xxx_xx.x
+ // xxxxxxxx xxxxxxx:
+ // $xxx: xxx_xx.x,x $
+ // xxxxxxxx 1.3 1998/03/06 00:27:00 xxx
+ // -- xxxxx xxxxxxx xx xx.xxxx xxx xxxxxxxx xxxxxxx.
+ // -- xxxx xxxxxxxxxxxxx xx xx xxxxxxxxxxx xx xx.x xxx xx.x xx xxxxxxx xxx xxxxxxxxxxx.
+ // -- xxxx xxxxx xxx xxxxxxxxxxxxx xxx1'x (xxxxxxx xx xxxxx) xx xx.x xxx xxxx xxxxxx
+ // xxxxxxxxxx.
+ // -- xxxxx xxxxxxxxxx xxxxxxxx xx xxx xx xxxxxxxxxxx xxx xxxx xxxxxx xxxxxxxxxxxx xxxx.
+ // -- xx xxx xxxxxxxxx xxx xxxxxx xx xx xx xxx xxxxx xxxxx xx xxxx xxxxxxxx xx xxxx.
+ // -- xx xx xxxx xxxxxxx xxx xxx xxxx xxxxxx xxxxxx (xxx xxx xxxx) xxx xxx xxxx/xxxx
+ // xxxxxxxxxx xxxx xxxxxxx.
+ //
+ // xxxxxxxx 1.2 1998/03/04 18:58:55 xxx
+ // xxxxx xxxxxxxxx xxx-xx xxxxxxx xxxxxxx xx xxxx xxxxx.
+ //
+ // xxxxxxxx 1.1 1998/02/23 19:31:52 xxx
+ // xxxxx xxxxx xxxxxx xxx xxxx xxxxx xxxxx xxxxxxxxxx.
+ //
+ // ---------------------------------------------------------------
+ //
+ // xxxxxxx xxx xxxxxxxxx xxx xxxxx xxx xxxxxxx xxx
+ //
+ // xxxx xxxxxx xxxxx xxx xxxxx xxxxxx xxxxxxx/xxxx xxx xxxx
+ // xx.x xxx xx xx xxxxxxxxx xxxx xxxx.x xxxxxx xx
+ // xxxx xxx xxxxxxx xx xxx. xx xxxx xxxxates the
+ // bidir Foo Bus into a chip input for use by li.v
+ //
+ // This module also isolates for input to lbsm.v, and drives
+ // (if so indicated by lbsm.v) the bidir Fooileo Cmd bus.
+ //
+ //
+
+ (
+ CLK,
+ WWADoe,
+ WWCoe,
+ WWCmdIfOE,
+ WWADHold,
+ iWWADO,
+ WWCmdI,
+ WWADI,
+ WWADB,
+ WWCmdB
+ );
+
+ /////////////////////////////////////////////////////////////////////
+ // inputs
+
+ input CLK; // LBA clk
+
+ // inputs from lbsm.v
+ input WWADoe; // FooBus Addr/Data OE
+ input WWCoe; // FooBus Cmd OE
+ input [8:0] WWCmdIfOE; // FooBus Cmd if enabled
+ input WWADHold; // FooBus Addr hold
+
+ // inputs from li.v
+ input [31:0] iWWADO; // FooBus Address/Data out next cycle
+
+
+ /////////////////////////////////////////////////////////////////////
+ // outputs
+
+ // outputs to lbsm.v
+ output [8:0] WWCmdI; // FooBus Command in
+
+ // outputs to li.v
+ output [31:0] WWADI; // FooBus Address/Data in
+
+
+ /////////////////////////////////////////////////////////////////////
+ // bidirs
+
+ // bidirs to/from off-chip
+ inout [31:0] WWADB; // bidir FooBus addr/data
+ inout [8:0] WWCmdB; // bidir FooBus command
+
+ /////////////////////////////////////////////////////////////////////
+ // reg's for outputs (some flops, some not)
+
+ /////////////////////////////////////////////////////////////////////
+ // other flops
+
+ reg [31:0] WWADIfOE; // FooBus Addr/Data Out if enabled
+
+
+
+endmodule
+
+
+// Local Variables:
+// eval:(if (fboundp `verilog-enable-indentation) (verilog-enable-indentation))
+// End:
diff --git a/tests/autoinst_brucet.v b/tests/autoinst_brucet.v
new file mode 100644
index 0000000..702c330
--- /dev/null
+++ b/tests/autoinst_brucet.v
@@ -0,0 +1,39 @@
+module io1_sub(/*AUTOARG*/
+ // Outputs
+ x, y, z,
+ // Inputs
+ a, b
+ );
+
+ input a;
+ input b;
+ output x;
+ output y;
+ output z;
+
+ andcell c0 (
+ .c (x),
+ /*AUTOINST*/
+ // Inputs
+ .a (a),
+ .b (b));
+
+ orcell c0 (
+ .c (y),
+ /*AUTOINST*/
+ // Inputs
+ .a (a),
+ .b (b));
+
+ nandcell c0 (
+ .c (z),
+ /*AUTOINST*/
+ // Inputs
+ .a (a),
+ .b (b));
+
+endmodule
+
+// Local Variables:
+// verilog-library-files:("autoinst_brucet_library.v")
+// End:
diff --git a/tests/autoinst_brucet_library.v b/tests/autoinst_brucet_library.v
new file mode 100644
index 0000000..3bce336
--- /dev/null
+++ b/tests/autoinst_brucet_library.v
@@ -0,0 +1,38 @@
+module andcell (/*AUTOARG*/
+ // Outputs
+ c,
+ // Inputs
+ a, b
+ );
+
+ input a;
+ input b;
+ output c;
+ wire c = a&b;
+endmodule
+
+module nandcell (/*AUTOARG*/
+ // Outputs
+ c,
+ // Inputs
+ a, b
+ );
+
+ input a;
+ input b;
+ output c;
+ wire c = !(a&b);
+endmodule
+
+module orcell (/*AUTOARG*/
+ // Outputs
+ c,
+ // Inputs
+ a, b
+ );
+
+ input a;
+ input b;
+ output c;
+ wire c = a|b;
+endmodule
diff --git a/tests/autoinst_bug373.v b/tests/autoinst_bug373.v
new file mode 100644
index 0000000..eaf20bb
--- /dev/null
+++ b/tests/autoinst_bug373.v
@@ -0,0 +1,47 @@
+typedef struct packed {
+ logic [7:0] data;
+ logic wr_ena;
+} mystruct_s;
+
+module submod
+ (input logic a_port,
+ input logic [4:0] b_bus,
+ input mystruct_s single_struct_is_fine,
+ input mystruct_s [2:0] array_of_struct_is_not,
+ output logic status);
+
+ /*AUTOTIEOFF*/
+ // Beginning of automatic tieoffs (for this module's unterminated outputs)
+ wire status = 1'h0;
+ // End of automatics
+
+endmodule // submod
+
+module top;
+ /*AUTOLOGIC*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic status; // From submod0 of submod.v
+ // End of automatics
+
+ /*AUTOREGINPUT*/
+ // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+ logic a_port; // To submod0 of submod.v
+ mystruct_s [2:0] array_of_struct_is_not; // To submod0 of submod.v
+ logic [4:0] b_bus; // To submod0 of submod.v
+ mystruct_s single_struct_is_fine; // To submod0 of submod.v
+ // End of automatics
+
+ submod submod0
+ (/*AUTOINST*/
+ // Outputs
+ .status (status),
+ // Inputs
+ .a_port (a_port),
+ .b_bus (b_bus[4:0]),
+ .single_struct_is_fine (single_struct_is_fine),
+ .array_of_struct_is_not (array_of_struct_is_not[2:0]));
+endmodule // top
+
+// Local Variables:
+// verilog-typedef-regexp: "_s$"
+// End:
diff --git a/tests/autoinst_case_chakradhara.v b/tests/autoinst_case_chakradhara.v
new file mode 100644
index 0000000..a36dadf
--- /dev/null
+++ b/tests/autoinst_case_chakradhara.v
@@ -0,0 +1,20 @@
+module foo();
+ /*bar AUTO_TEMPLATE (
+ .pme\(.*\)_o (pme\1[]),
+ .PME\(.*\)_o (pMe\1[]),
+ .pme\(.*\)_o (pme\1[]),
+ );
+ */
+ bar bar
+ (/*AUTOINST*/);
+
+endmodule
+
+module bar
+ (/*AUTOARG*/);
+
+ input PME_o;
+ input pme_o;
+ input pmE_o;
+
+endmodule
diff --git a/tests/autoinst_casefold_hou.v b/tests/autoinst_casefold_hou.v
new file mode 100644
index 0000000..c9b063c
--- /dev/null
+++ b/tests/autoinst_casefold_hou.v
@@ -0,0 +1,45 @@
+typedef struct packed {
+ logic a,b,c;
+} tTest;
+
+module test
+ (
+ input clk,rst
+ );
+
+ wire [7:0] data_tm;
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ tTest q; // From foo of foo.v
+ // End of automatics
+
+ /* foo AUTO_TEMPLATE (
+ .tm (data_tm),
+ );
+ */
+
+ foo foo (/*AUTOINST*/
+ // Outputs
+ .q (q),
+ // Inputs
+ .clk (clk),
+ .rst (rst),
+ .tm (data_tm)); // Templated
+ /*AUTO_LISP(setq verilog-typedef-regexp "^t[A-Z]")*/
+endmodule
+
+module foo
+ (
+ input clk,
+ input rst,
+ input [7:0] tm,
+ output tTest q
+ );
+endmodule
+
+// Local Variables:
+// verilog-case-fold:nil
+// verilog-library-directories:(".")
+// verilog-typedef-regexp:"^t[A-Z]"
+// End:
diff --git a/tests/autoinst_cavanaugh_pull.v b/tests/autoinst_cavanaugh_pull.v
new file mode 100644
index 0000000..ec7fd0a
--- /dev/null
+++ b/tests/autoinst_cavanaugh_pull.v
@@ -0,0 +1,80 @@
+
+module fifo(/*AUTOARG*/);
+
+input clk;
+input rst_n;
+output fifo_full_w;
+
+input enqueue_w;
+input [(DATA_WIDTH-1):0] data_in_w;
+
+output data_valid_r;
+input dequeue_w;
+input [1:0] full_threshold;
+
+output [(DATA_WIDTH-1):0] rdata_r;
+
+
+endmodule
+
+module req (p_clk, carb_rst_rnp, req_rp, len_rxp, deq_req, deq_len, deq_val);
+
+ input p_clk;
+ input carb_rst_rnp;
+ input [4:0] len_rxp;
+ input req_rp;
+ input deq_req;
+ output [4:0] deq_len;
+ output deq_val;
+ reg [5:0] fifo_entry1_rp;
+ reg [5:0] fifo_entry2_rp;
+ reg [4:0] deq_len;
+ reg deq_val;
+
+endmodule
+
+module pull( /*AUTOARG*/);
+
+ input clk;
+ input rst_rnpha;
+ input [4:0] lenar_rxp;
+ input rem_rpd;
+ input d_rews;
+ output [4:0] d_len;
+ output d_val;
+
+
+/* req AUTO_TEMPLATE "\(g[a-z0-9]+\|g.*[0-9]\)" (
+ .p_clk (my_clk_@),
+ .len_rxp (carb_rst_rnp_@),
+ .carb_rst_rnp (pull_req1));
+
+*/
+
+ req test432_gbe5(/*AUTOINST*/);
+
+ req gbe9_vreos(/*AUTOINST*/);
+
+
+/* fifo AUTO_TEMPLATE "gbe[0-9]+_\([^\_]+\)" (
+ .clk (@_clk),
+ .\(.*data.*\) (@_\1),
+ .\(.*\)\(full\)\(.*\) (\1@\3),
+ .\(en\|de\)\(.\).+ (@_\1\2));
+*/
+
+
+
+ fifo #(5) gbe2_pull_req (/*AUTOINST*/);
+
+
+ fifo #(5)
+ gbe1_pull_req_fifo( /*AUTOINST*/);
+
+
+
+
+
+
+
+endmodule // pull_arb
diff --git a/tests/autoinst_ciu.v b/tests/autoinst_ciu.v
new file mode 100644
index 0000000..02fb5db
--- /dev/null
+++ b/tests/autoinst_ciu.v
@@ -0,0 +1,20 @@
+module testmux
+ (
+ input wire [2:0] a
+ );
+endmodule
+
+module top_test();
+
+ /* testmux AUTO_TEMPLATE "\(.*\)$" (
+ .a (@_a_value[]),
+ );
+ */
+
+ testmux foo1_1
+ (/*AUTOINST*/);
+
+ testmux foo1_2
+ (/*AUTOINST*/);
+
+endmodule
diff --git a/tests/autoinst_clog2_bug522.v b/tests/autoinst_clog2_bug522.v
new file mode 100644
index 0000000..951d632
--- /dev/null
+++ b/tests/autoinst_clog2_bug522.v
@@ -0,0 +1,21 @@
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by brad Dobbie.
+
+module mod;
+ submod #
+ (.VEC_W(8),
+ .IDX_W($clog2(VEC_W)))
+ submod
+ (/*AUTOINST*/);
+endmodule
+
+module submod (/*AUTOARG*/);
+ parameter VEC_W = 32;
+ parameter IDX_W = $clog2(VEC_W);
+ input [VEC_W-1:0] vec;
+ output [IDX_W-1:0] idx;
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-param-value:t
+// End:
diff --git a/tests/autoinst_cmtcell_msg270.v b/tests/autoinst_cmtcell_msg270.v
new file mode 100644
index 0000000..ef7c969
--- /dev/null
+++ b/tests/autoinst_cmtcell_msg270.v
@@ -0,0 +1,15 @@
+module ex;
+
+ subwidth u_a2 // commented
+ (/*AUTOINST*/
+ // Outputs
+ .bus4a (bus4a[0:3]));
+
+endmodule
+
+module subwidth (/*AUTOARG*/
+ // Outputs
+ bus4a
+ );
+ output [0:3] bus4a;
+endmodule
diff --git a/tests/autoinst_cmtinst_bug383.v b/tests/autoinst_cmtinst_bug383.v
new file mode 100644
index 0000000..ea87fe5
--- /dev/null
+++ b/tests/autoinst_cmtinst_bug383.v
@@ -0,0 +1,33 @@
+module t;
+
+ /*fifo_s AUTO_TEMPLATE (
+ .ignored_signal (1'b1),
+ .out_signal (NC),
+ .out_bus (out_bus[]),
+ );
+ */
+ fifo_s data_fifo (
+ //fifo_s data_fifo (
+ // Inputs
+ .clk (fifo_clk),
+ /*AUTOINST*/);
+
+ /*fifo_s AUTO_TEMPLATE (
+ .ignored_signal (1'b1),
+ .out_signal (NC),
+ .out_bus (out_bus[]),
+ );
+ */
+ //fifo_s data_fifo (
+ fifo_s data_fifo (
+ // Inputs
+ .clk (fifo_clk),
+ /*AUTOINST*/);
+endmodule
+
+module fifo_s;
+ input ignored_signal;
+ input reset;
+ output [31:0] out_bus;
+ output out_signal;
+endmodule
diff --git a/tests/autoinst_cmtparen_tennant.sv b/tests/autoinst_cmtparen_tennant.sv
new file mode 100644
index 0000000..03bbb6e
--- /dev/null
+++ b/tests/autoinst_cmtparen_tennant.sv
@@ -0,0 +1,125 @@
+typedef node logic;
+
+module top
+ #(parameter COLS = 4
+ )
+ ( input logic clk,
+ input logic rstb,
+ input logic [COLS-1:0] ival,
+ input logic [COLS-1:0][1:0] idata_some_extra_sig_length,
+
+ input logic [COLS-1:0][7:0] isig1,
+ input logic [COLS-1:0][6:0] isig2,
+ input logic [COLS-1:0][5:0] isig3,
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input idata_some_extra_sig_lengt,// To isub1 of sub1.v, ...
+ input isig, // To isub1 of sub1.v, ...
+ // End of automatics
+
+ output logic [COLS-1:0] oval,
+ output logic [COLS-1:0][1:0] odata,
+ output logic [COLS-1:0] s3_oval,
+ output logic [COLS-1:0][1:0] s3_odata,
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output s1_odat, // From isub1 of sub1.v
+ output s3_odat // From isub3 of sub3.v
+ // End of automatics
+ );
+
+
+ logic [COLS-1:0][1:0] s1_odata; // From isub1 of sub1.v
+ logic [COLS-1:0] s1_oval; // From isub1 of sub1.v
+ /*AUTOWIRE*/
+
+ /* sub2 AUTO_TEMPLATE(
+ .idata_some_extra_sig_length ( s1_odata),
+ .ival ( s1_oval),
+ );*/
+ sub2 isub2 (/*AUTOINST*/
+ // Outputs
+ .oval (oval[COLS-1:0]),
+ .odata (odata/*[COLS-1:0][1:0]*/),
+ // Inputs
+ .clk (clk),
+ .rstb (rstb),
+ .ival ( s1_oval), // Templated
+ .idata_some_extra_sig_length( s1_odata)); // Templated
+
+ genvar column;
+ /* sub1 AUTO_TEMPLATE(
+ .i.* ( @"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
+ .o.* ( s1_@"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
+ );*/
+ /* sub3 AUTO_TEMPLATE(
+ .i.* ( @"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
+ .o.* ( s3_@"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
+ );*/
+ generate for(column=0;column<4;column++) begin : COLUMN
+ sub1 isub1(/*AUTOINST*/
+ // Outputs
+ .oval ( s1_oval[column] ), // Templated
+ .odata ( s1_odata[column] /* [1:0] */), // Templated
+ // Inputs
+ .clk (clk),
+ .rstb (rstb),
+ .ival ( ival[column] ), // Templated
+ .idata_some_extra_sig_length( idata_some_extra_sig_length[column] /* [1:0] */), // Templated
+ .isig1 ( isig1[column] /* [7:0] */), // Templated
+ .isig2 ( isig2[column] /* [6:0] */), // Templated
+ .isig3 ( isig3[column] /* [5:0] */)); // Templated
+ sub3 isub3(/*AUTOINST*/
+ // Outputs
+ .oval ( s3_oval[column] ), // Templated
+ .odata ( s3_odata[column] /* [1:0] */), // Templated
+ // Inputs
+ .clk (clk),
+ .rstb (rstb),
+ .ival ( ival[column] ), // Templated
+ .idata_some_extra_sig_length( idata_some_extra_sig_length[column] /* [1:0] */)); // Templated
+
+ end endgenerate
+
+
+endmodule // top
+
+module sub1
+ ( input logic clk,
+ input logic rstb,
+ input logic ival,
+ input logic [1:0] idata_some_extra_sig_length,
+ input logic [7:0] isig1,
+ input logic [6:0] isig2,
+ input logic [5:0] isig3,
+ output logic oval,
+ output logic [1:0] odata
+ );
+endmodule // sub
+module sub3
+ ( input logic clk,
+ input logic rstb,
+ input logic ival,
+ input logic [1:0] idata_some_extra_sig_length,
+ output logic oval,
+ output logic [1:0] odata
+ );
+endmodule // sub
+
+module sub2
+ #(parameter COLS = 4
+ )
+ ( input logic clk,
+ input logic rstb,
+ input logic [COLS-1:0] ival,
+ input logic [COLS-1:0][1:0] idata_some_extra_sig_length,
+ output logic [COLS-1:0] oval,
+ output logic [COLS-1:0] [1:0] odata
+ );
+endmodule // sub
+// Local Variables:
+// verilog-typedef-regexp:"\\(^t_\\)\\|\\(^node$\\)\\|\\(_s$\\)\\|\\(_t$\\)"
+// verilog-library-directories:("." )
+// verilog-library-extensions:(".v" ".sv" ".h" ".vr" ".vm")
+// End:
diff --git a/tests/autoinst_crawford_array.v b/tests/autoinst_crawford_array.v
new file mode 100644
index 0000000..285fc49
--- /dev/null
+++ b/tests/autoinst_crawford_array.v
@@ -0,0 +1,79 @@
+`define AUTO_NBR_A_INST 2
+
+module autoinst_crawford_array(/*AUTOARG*/
+ // Outputs
+ a_valid, a_data,
+ // Inputs
+ a_ready, clk, rst_n
+ );
+
+ // a interface
+ output [`AUTO_NBR_A_INST*1-1:0] a_valid;
+ output [`AUTO_NBR_A_INST*8-1:0] a_data;
+ input [`AUTO_NBR_A_INST*1-1:0] a_ready;
+
+ // clock interface
+ input clk;
+ input rst_n;
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ // End of automatics
+
+ // non-arrayed example
+ autoinst_crawford_array_a auto_a_0
+ (/*AUTOINST*/
+ // Outputs
+ .a_valid (a_valid),
+ .a_data (a_data[7:0]),
+ // Inputs
+ .a_ready (a_ready),
+ .clk (clk),
+ .rst_n (rst_n));
+
+ autoinst_crawford_array_a auto_a_1
+ (/*AUTOINST*/
+ // Outputs
+ .a_valid (a_valid),
+ .a_data (a_data[7:0]),
+ // Inputs
+ .a_ready (a_ready),
+ .clk (clk),
+ .rst_n (rst_n));
+
+ // Arrayed instances
+ // AUTOINST does not work for this one :-(
+ // Note it is tricky because I want clk and rst_n to fanout to both instances,
+ // but I want the valid signals to be discreatly tied to each submodule.
+
+ //autoinst_crawford_array_a ary [`AUTO_NBR_A_INST-1:0]
+ // (/*XXXAUTOINST*/
+ // // Outputs
+ // .a_valid (a_valid[1:0]),
+ // .a_data (a_data[15:0]),
+ // // Inputs
+ // .a_ready (a_ready[1:0]),
+ // .clk (clk),
+ // .rst_n (rst_n));
+
+ autoinst_crawford_array_a ary [`AUTO_NBR_A_INST-1:0]
+ (/*AUTOINST*/
+ // Outputs
+ .a_valid (a_valid),
+ .a_data (a_data[7:0]),
+ // Inputs
+ .a_ready (a_ready),
+ .clk (clk),
+ .rst_n (rst_n));
+
+ autoinst_crawford_array_a #(.a(a),b) par [`AUTO_NBR_A_INST-1:0]
+ (/*AUTOINST*/
+ // Outputs
+ .a_valid (a_valid),
+ .a_data (a_data[7:0]),
+ // Inputs
+ .a_ready (a_ready),
+ .clk (clk),
+ .rst_n (rst_n));
+
+endmodule
diff --git a/tests/autoinst_crawford_array_a.v b/tests/autoinst_crawford_array_a.v
new file mode 100644
index 0000000..0f0c47b
--- /dev/null
+++ b/tests/autoinst_crawford_array_a.v
@@ -0,0 +1,39 @@
+`define auto_trq #1 // clock to q delay
+`define auto_tcq #1 // reset to q delay
+
+module autoinst_crawford_array_a(/*AUTOARG*/
+ // Outputs
+ a_valid, a_data,
+ // Inputs
+ a_ready, clk, rst_n
+ );
+
+ // a interface
+ output a_valid;
+ output [7:0] a_data;
+ input a_ready;
+
+ // clock interface
+ input clk;
+ input rst_n;
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg [7:0] a_data;
+ reg a_valid;
+ // End of automatics
+
+ always @(posedge clk or negedge rst_n) begin
+ if(~rst_n) begin
+ a_valid <= `auto_trq 0;
+ a_data <= `auto_trq 0;
+ end
+ else begin
+ if(a_ready) begin
+ a_valid <= `auto_tcq 1;
+ a_data <= `auto_tcq 8'hcc;
+ end
+ end
+ end
+
+endmodule
diff --git a/tests/autoinst_dedefine.v b/tests/autoinst_dedefine.v
new file mode 100644
index 0000000..22f73a5
--- /dev/null
+++ b/tests/autoinst_dedefine.v
@@ -0,0 +1,27 @@
+`define foo 6
+`define bar 0
+
+module autoinst_dedefine;
+
+ /*AUTOOUTPUT*/
+ /*AUTOWIRE*/
+
+ /* bar AUTO_TEMPLATE (
+ .\(.*\) (@"(concat vl-name (verilog-symbol-detick-text vl-bits))"),
+ ); */
+
+ bar sub
+ (/*AUTOINST*/);
+
+endmodule
+
+module bar;
+ output onewide;
+ output [3:1] fourwide;
+ output [`foo-1:`bar] varwide;
+endmodule
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
+
diff --git a/tests/autoinst_ding.v b/tests/autoinst_ding.v
new file mode 100644
index 0000000..5640ee1
--- /dev/null
+++ b/tests/autoinst_ding.v
@@ -0,0 +1,47 @@
+module AA(
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ input wire clock,
+ input wire reset,
+ input wire test_enable,
+ input wire afe_ctrl,
+ input wire cpu_wr,
+ input wire [4:0] cpu_addr,
+ input wire [7:0] cpu_wdata,
+ output wire [7:0] core_data,
+ output wire core_code_error,
+ output wire core_code_idle,
+ output wire [7:0] cpu_rdata
+);
+endmodule
+
+module BB(
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ input wire clock,
+ input wire reset,
+ input wire test_enable,
+ input wire core_code_idle,
+ input wire core_code_error,
+ input wire [7:0] core_data,
+ input wire [8:0] mbist_done,
+ input wire [8:0] mbist_fail,
+ output wire mbist_rst,
+ output reg mbist_test
+);
+endmodule
+
+module TOP(
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ );
+
+AA AA_U(/*AUTOINST*/);
+
+BB BB_U(/*AUTOINST*/);
+
+// Local Variables:
+// verilog-library-directories:(".")
+// End:
+
+endmodule
diff --git a/tests/autoinst_for_myers.v b/tests/autoinst_for_myers.v
new file mode 100644
index 0000000..3b9428e
--- /dev/null
+++ b/tests/autoinst_for_myers.v
@@ -0,0 +1,53 @@
+module InstMod ( ins, outs );
+ output [INWIDTH-1:0] ins;
+ output [OUTWIDTH-1:0] outs;
+endmodule
+
+module test_top;
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [n*INWIDTH +: INWIDTH] ins; // From instName of InstMod.v
+ wire [n*INWIDTH +: INWIDTH] ins2; // From instName2 of InstMod.v
+ wire [n*INWIDTH +: INWIDTH] ins3; // From instName3 of InstMod.v, ..., Couldn't Merge
+ wire [n*OUTWIDTH +: OUTWIDTH] outs; // From instName of InstMod.v
+ wire [n*OUTWIDTH +: OUTWIDTH] outs2; // From instName2 of InstMod.v
+ wire [4*OUTWIDTH-1 : 0] outs3; // From instName3 of InstMod.v, ..., Couldn't Merge
+ // End of automatics
+
+ genvar i;
+ generate
+ for (i=0; i<4; i=i+1) begin
+ /*AUTO_LISP(setq vh-n 4)*/
+ /* InstMod AUTO_TEMPLATE
+ (.ins (ins [n*INWIDTH +: INWIDTH]),
+ .outs (outs[n*OUTWIDTH +: OUTWIDTH])); */
+
+ InstMod instName (/*AUTOINST*/
+ // Outputs
+ .ins (ins [n*INWIDTH +: INWIDTH]), // Templated
+ .outs (outs[n*OUTWIDTH +: OUTWIDTH])); // Templated
+
+ InstMod instName2
+ (// Inputs
+ .ins (ins2 [n*INWIDTH +: INWIDTH]),
+ // Outputs
+ .outs (outs2[n*OUTWIDTH +: OUTWIDTH])
+ /*AUTOINST*/);
+
+ // This works but is ugly
+ InstMod instName3
+ (// Inputs
+ .ins (ins3 [n*INWIDTH +: INWIDTH]),
+ // Outputs
+ .outs (outs3[n*OUTWIDTH +: OUTWIDTH])
+`ifdef NEVER
+ // Inouts
+ .ins (ins3 [4*INWIDTH-1 : 0]),
+ .outs (outs3[4*OUTWIDTH-1 : 0])
+`endif
+ /*AUTOINST*/);
+
+ end
+ endgenerate
+endmodule
diff --git a/tests/autoinst_func.v b/tests/autoinst_func.v
new file mode 100644
index 0000000..185c2d7
--- /dev/null
+++ b/tests/autoinst_func.v
@@ -0,0 +1,45 @@
+module autoinst_func;
+
+ /*AUTO_LISP(defun testfunc (sig bits) (let ((result "{"))
+ (setq result (concat result sig "[0" bits "]"))
+ (concat result "}")))*/
+
+ /* autoinst_wildcard_sub AUTO_TEMPLATE (
+ .sd0_adrs@ (myport@"(substring \\"\1\\" 0 1)"),
+ .\(.*\) (@"(testfunc vl-name vl-bits)"),
+ ); */
+
+ autoinst_wildcard_sub sub0
+ (/*AUTOINST*/
+ // Inouts
+ .sd0_adrs0 (myport0), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs1 (myport1), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs10 (myport1), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs11 (myport1), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs2 (myport2), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs3 (myport3), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs4 (myport4), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs5 (myport5), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs6 (myport6), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs7 (myport7), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs8 (myport8), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs9 (myport9), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_ba0 ({sd0_ba0[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_ba1 ({sd0_ba1[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_clk ({sd0_clk[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm0_l ({sd0_dqm0_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm1_l ({sd0_dqm1_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm2_l ({sd0_dqm2_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm3_l ({sd0_dqm3_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm4_l ({sd0_dqm4_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm5_l ({sd0_dqm5_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm6_l ({sd0_dqm6_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm7_l ({sd0_dqm7_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd_ras_ ({sd_ras_[0]})); // Templated LHS: ^\(.*\)$
+
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-template-numbers: lhs
+// verilog-auto-inst-sort: t
+// End:
diff --git a/tests/autoinst_gate.v b/tests/autoinst_gate.v
new file mode 100644
index 0000000..18dd199
--- /dev/null
+++ b/tests/autoinst_gate.v
@@ -0,0 +1,28 @@
+//bug284
+
+module wrapper
+ (
+ /*AUTOOUTPUT*/
+ /*AUTOINPUT*/
+ );
+
+ //--------------------------------------------------------------------------
+
+ // Note input/output comments aren't needed, and multiple signals
+ // per line are ok
+ or u_or [31:0]
+ (o[31:0], i0[31:0], i1[31:0], i2[31:0],
+ // Inputs,
+ i3[31:0]
+ /*AUTOINST*/);
+
+// bug676
+ buf # 1 mybuf[1:0]
+ (bout[1:0],
+ // Inputs,
+ bin[1:0]
+ /*AUTOINST*/);
+
+ //--------------------------------------------------------------------------
+
+endmodule
diff --git a/tests/autoinst_genvar.v b/tests/autoinst_genvar.v
new file mode 100644
index 0000000..1f491b8
--- /dev/null
+++ b/tests/autoinst_genvar.v
@@ -0,0 +1,28 @@
+module AA(
+ input wire clock,
+ input wire reset,
+ input wire test_enable,
+ input wire afe_ctrl,
+ input wire cpu_wr,
+ input wire [4:0] cpu_addr,
+ input wire [7:0] cpu_wdata,
+ output wire [7:0] core_data,
+ output wire core_code_error,
+ output wire core_code_idle,
+ output wire [7:0] cpu_rdata
+);
+endmodule
+
+module TOP(
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ );
+
+ genvar x;
+
+AA AA_U(
+ // Inputs
+ .test_enable (x),
+ /*AUTOINST*/);
+
+endmodule
diff --git a/tests/autoinst_iface270_sub.v b/tests/autoinst_iface270_sub.v
new file mode 100644
index 0000000..48f6220
--- /dev/null
+++ b/tests/autoinst_iface270_sub.v
@@ -0,0 +1,9 @@
+// See http://www.veripool.org/issues/show/270
+
+interface autoinst_iface270_sub;
+ logic a;
+ logic b;
+ modport master_mp(input a, output b);
+ modport slave_mp(output a, input b);
+ modport monitor (input a, input b);
+endinterface
diff --git a/tests/autoinst_iface270_top.v b/tests/autoinst_iface270_top.v
new file mode 100644
index 0000000..606fbf3
--- /dev/null
+++ b/tests/autoinst_iface270_top.v
@@ -0,0 +1,14 @@
+// See http://www.veripool.org/issues/show/270
+
+module top;
+ /*AUTOWIRE*/
+
+ autoinst_iface270_sub inst_if (/*AUTOINST*/);
+
+ ifio sub (/*AUTOINST*/);
+
+endmodule
+
+module ifio
+ (autoinst_iface270_sub inst_if);
+endmodule
diff --git a/tests/autoinst_iface270_top_bug429.v b/tests/autoinst_iface270_top_bug429.v
new file mode 100644
index 0000000..87433a8
--- /dev/null
+++ b/tests/autoinst_iface270_top_bug429.v
@@ -0,0 +1,18 @@
+// See http://www.veripool.org/issues/show/429
+
+module top;
+ /*AUTOWIRE*/
+
+ autoinst_iface270_sub inst_if (/*AUTOINST*/);
+
+ ifio sub (/*AUTOINST*/);
+
+endmodule
+
+module ifio
+ (autoinst_iface270_sub inst_if);
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-interfaced-ports: nil
+// End:
diff --git a/tests/autoinst_ifdef_fredrickson_200503_sub.v b/tests/autoinst_ifdef_fredrickson_200503_sub.v
new file mode 100644
index 0000000..4edc354
--- /dev/null
+++ b/tests/autoinst_ifdef_fredrickson_200503_sub.v
@@ -0,0 +1,15 @@
+module autoinst_ifdef_fredrickson_200503_sub
+ (input a,
+ `ifdef TEST
+ input c,
+ output wire d,
+ `endif
+ output wire b
+ );
+
+ assign b = a;
+ `ifdef TEST
+ assign d = c;
+ `endif
+
+endmodule // define_sub
diff --git a/tests/autoinst_ifdef_fredrickson_200503_top.v b/tests/autoinst_ifdef_fredrickson_200503_top.v
new file mode 100644
index 0000000..9c714d3
--- /dev/null
+++ b/tests/autoinst_ifdef_fredrickson_200503_top.v
@@ -0,0 +1,12 @@
+module autoinst_ifdef_fredrickson_200503_top();
+
+ autoinst_ifdef_fredrickson_200503_sub sub
+ (/*AUTOINST*/
+ // Outputs
+ .d (d),
+ .b (b),
+ // Inputs
+ .a (a),
+ .c (c));
+
+endmodule // define_top
diff --git a/tests/autoinst_import.v b/tests/autoinst_import.v
new file mode 100644
index 0000000..a2e6373
--- /dev/null
+++ b/tests/autoinst_import.v
@@ -0,0 +1,27 @@
+//bug709
+
+module InstModule
+ (input clk,
+ svi.master svi_modport,
+ svi svi_nomodport);
+endmodule // InstModule
+
+module InstModule1 import mdp_pkg::*;
+ (input clk,
+ svi.master svi_modport,
+ svi svi_nomodport);
+endmodule
+
+module top;
+ InstModule instName
+ (/*AUTOINST*/);
+
+ InstModule1 instName1
+ (/*AUTOINST*/);
+
+endmodule
+
+// Local Variables:
+// verilog-library-directories:(".")
+// verilog-library-extensions:(".v" ".sv")
+// End:
diff --git a/tests/autoinst_instname_all.v b/tests/autoinst_instname_all.v
new file mode 100644
index 0000000..6d38865
--- /dev/null
+++ b/tests/autoinst_instname_all.v
@@ -0,0 +1,17 @@
+module ex;
+
+ /* autoinst_paramover_sub AUTO_TEMPLATE (
+ .\(.*\)(@"vl-cell-name"_\1),
+ );*/
+
+ autoinst_paramover_sub u_a0(/*AUTOINST*/
+ // Inouts
+ .a (u_a0_a), // Templated
+ .b (u_a0_b)); // Templated
+
+ autoinst_paramover_sub u_a1(/*AUTOINST*/
+ // Inouts
+ .a (u_a1_a), // Templated
+ .b (u_a1_b)); // Templated
+
+endmodule
diff --git a/tests/autoinst_instname_carlh.v b/tests/autoinst_instname_carlh.v
new file mode 100644
index 0000000..fcfd17a
--- /dev/null
+++ b/tests/autoinst_instname_carlh.v
@@ -0,0 +1,18 @@
+module ex;
+
+ /* autoinst_paramover_sub AUTO_TEMPLATE (
+ .a(@"vl-cell-name"_in[]),
+ .b(@"(substring inst 2)"_out[]),
+ );*/
+
+ autoinst_paramover_sub u_a0(/*AUTOINST*/
+ // Inouts
+ .a (u_a0_in[bitsa:0]), // Templated
+ .b (a0_out[bitsb:0])); // Templated
+
+ autoinst_paramover_sub u_a1(/*AUTOINST*/
+ // Inouts
+ .a (u_a1_in[bitsa:0]), // Templated
+ .b (a1_out[bitsb:0])); // Templated
+
+endmodule
diff --git a/tests/autoinst_interface.v b/tests/autoinst_interface.v
new file mode 100644
index 0000000..7befb78
--- /dev/null
+++ b/tests/autoinst_interface.v
@@ -0,0 +1,50 @@
+// See bug75
+
+module autoinst_interface
+ (/*AUTOINOUTMODULE("autoinst_interface_sub")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ logic [7:0] count,
+ logic clk,
+ logic reset,
+ logic start,
+ my_svi.master my_svi_port,
+ my_svi my_svi_noport,
+ my_svi my_svi_noport_upper_decl
+ // End of automatics
+ );
+endmodule
+
+module autoinst_interface
+ (/*AUTOINOUTCOMP("autoinst_interface_sub")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ logic clk,
+ logic reset,
+ logic start,
+ logic [7:0] count,
+ my_svi.master my_svi_port,
+ my_svi my_svi_noport,
+ my_svi my_svi_noport_upper_decl
+ // End of automatics
+ );
+endmodule
+
+module top;
+ /*AUTOLOGIC*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic [7:0] count; // From submod0 of autoinst_interface_sub.v
+ // End of automatics
+
+ my_svi my_svi_noport_upper_decl ();
+
+ autoinst_interface_sub submod0 (/*AUTOINST*/
+ // Interfaces
+ .my_svi_port (my_svi_port.master),
+ .my_svi_noport (my_svi_noport),
+ .my_svi_noport_upper_decl(my_svi_noport_upper_decl),
+ // Outputs
+ .count (count[7:0]),
+ // Inputs
+ .clk (clk),
+ .reset (reset),
+ .start (start));
+endmodule
diff --git a/tests/autoinst_interface_bug320.v b/tests/autoinst_interface_bug320.v
new file mode 100644
index 0000000..3a4493c
--- /dev/null
+++ b/tests/autoinst_interface_bug320.v
@@ -0,0 +1,16 @@
+// See bug320
+
+interface intf1;
+ logic a;
+ logic b;
+ modport mp1 (input a, output b);
+endinterface
+
+interface intf2 (intf1.mp1 c);
+ logic e;
+endinterface
+
+module top;
+ intf1 c(.*);
+ intf2 f(.*);
+endmodule
diff --git a/tests/autoinst_interface_star.v b/tests/autoinst_interface_star.v
new file mode 100644
index 0000000..8b2e493
--- /dev/null
+++ b/tests/autoinst_interface_star.v
@@ -0,0 +1,39 @@
+// See bug75
+
+module autoinst_interface
+ (/*AUTOINOUTMODULE("autoinst_interface_sub")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output [7:0] count,
+ input clk,
+ input reset,
+ input start,
+ my_svi.master my_svi_port,
+ my_svi my_svi_noport,
+ my_svi my_svi_noport_upper_decl
+ // End of automatics
+ );
+endmodule
+
+module autoinst_interface
+ (/*AUTOINOUTCOMP("autoinst_interface_sub")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output clk,
+ output reset,
+ output start,
+ input [7:0] count,
+ my_svi.master my_svi_port,
+ my_svi my_svi_noport,
+ my_svi my_svi_noport_upper_decl
+ // End of automatics
+ );
+endmodule
+
+module top;
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [7:0] count; // From submod0 of autoinst_interface_sub.v
+ my_svi my_svi_noport; // To/From submod0 of autoinst_interface_sub.v
+ my_svi my_svi_noport_upper_decl;// To/From submod0 of autoinst_interface_sub.v
+ // End of automatics
+ autoinst_interface_sub submod0 (.*);
+endmodule
diff --git a/tests/autoinst_interface_sub.v b/tests/autoinst_interface_sub.v
new file mode 100644
index 0000000..0da4db0
--- /dev/null
+++ b/tests/autoinst_interface_sub.v
@@ -0,0 +1,20 @@
+interface my_svi;
+ logic enable;
+ logic error;
+ logic [7:0] count2;
+ modport master (
+ input enable,
+ output error,
+ output count2);
+endinterface
+
+module autoinst_interface_sub
+ (input wire clk,
+ input wire reset,
+ input wire start,
+ output reg [7:0] count,
+ my_svi.master my_svi_port,
+ my_svi my_svi_noport,
+ my_svi my_svi_noport_upper_decl
+ );
+endmodule
diff --git a/tests/autoinst_johnson.v b/tests/autoinst_johnson.v
new file mode 100644
index 0000000..8562a33
--- /dev/null
+++ b/tests/autoinst_johnson.v
@@ -0,0 +1,41 @@
+module bfm (/*AUTOARG*/
+ // Inputs
+ name
+ );
+ input [8*5:1] name ;
+endmodule
+
+module tb;
+ // -------------------------------------------------------------------------
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ // End of automatics
+ // -------------------------------------------------------------------------
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ // End of automatics
+ // -------------------------------------------------------------------------
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ // End of automatics
+ // -------------------------------------------------------------------------
+ /* AUTO_CONSTANT ( "name0" "name1" "name2" ) */
+ // -------------------------------------------------------------------------
+ /* bfm AUTO_TEMPLATE (
+ // Inputs
+ .name ("name@"));
+ */
+ // -------------------------------------------------------------------------
+ bfm bmf0 (/*AUTOINST*/
+ // Inputs
+ .name ("name0")); // Templated
+ // -------------------------------------------------------------------------
+ bfm bmf1 (/*AUTOINST*/
+ // Inputs
+ .name ("name1")); // Templated
+ // -------------------------------------------------------------------------
+ bfm bmf2 (/*AUTOINST*/
+ // Inputs
+ .name ("name2")); // Templated
+ // -------------------------------------------------------------------------
+endmodule
diff --git a/tests/autoinst_lopaz.v b/tests/autoinst_lopaz.v
new file mode 100644
index 0000000..8039639
--- /dev/null
+++ b/tests/autoinst_lopaz.v
@@ -0,0 +1,52 @@
+module io1_sub(
+ /*AUTOARG*/);
+
+ wire [42:0] bscan_data; // boundary scan stitch
+ parameter bscan_count = 0;
+
+ assign bscan_data[0] = bscan_in;
+
+ /*
+ * Emacs template to auto instaniate MD[31:0] pads
+ */
+ /*
+ autoinst_lopaz_srpad AUTO_TEMPLATE (
+ .pin(MD[@]),
+ .pin_in({SDRAM_DQ_in[@],SDRAM_DQ_in[@]}),
+ .pin_out(SDRAM_DQ_out[@]),
+ .pin_outen(SDRAM_DQ_outen),
+ .sdrmode(SDRAM_single_rate),
+ .hw_enb(SDRAM_upper_word_enb),
+ .ff_rptr(SDRAM_ddr_inff_sel),
+ .ff_wptr(ddr_inff_enbH),
+ .clk(data_strobeH),
+ .bscan_so(bscan_data[@ + 1]),
+ .bscan_si(bscan_data[@]),
+ .bscan_shift(BScanShift),
+ .bscan_clock(BScanClock),
+ .bscan_mode(BScanMode),
+ .bscan_update(BScanUpdate),
+ .bscan_outen(SDRAM_DQ_bscan_outen),
+ );
+ */
+
+ autoinst_lopaz_srpad MD31_pad (/*AUTOINST*/);
+
+
+ /* autoinst_lopaz_srpad AUTO_TEMPLATE (
+ .pin(MD[@"num"]),
+ );
+ */
+
+ /*AUTO_LISP(setq num 1)*/
+ autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/);
+
+ /* autoinst_lopaz_srpad AUTO_TEMPLATE (
+ .pin(MD[@"num"]),
+ );
+ */
+
+ /*AUTO_LISP(setq num 2)*/
+ autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/);
+
+endmodule
diff --git a/tests/autoinst_lopaz_srpad.v b/tests/autoinst_lopaz_srpad.v
new file mode 100644
index 0000000..13efea5
--- /dev/null
+++ b/tests/autoinst_lopaz_srpad.v
@@ -0,0 +1,17 @@
+module autoinst_lopaz_srpad (/*AUTOARG*/
+ // Outputs
+ pin_in,
+ // Inouts
+ pin,
+ // Inputs
+ clk, pin_out, pin_outen
+ );
+ parameter w = 1;
+ input clk;
+
+ inout [w-1:0] pin;
+ output [2*w-1:0] pin_in;
+ input [w-1:0] pin_out;
+ input pin_outen;
+
+endmodule
diff --git a/tests/autoinst_ma_io_prefix.v b/tests/autoinst_ma_io_prefix.v
new file mode 100644
index 0000000..75bcbd3
--- /dev/null
+++ b/tests/autoinst_ma_io_prefix.v
@@ -0,0 +1,99 @@
+// From: "Ma, Zhenqiang" <Zhenqiang.Ma@caviumnetworks.com>
+
+module test (
+ // Ports for module A
+ input i_A_outsidei,
+ output o_A_outsideo,
+
+ // Ports for module B
+ input i_B_outsidei,
+ output o_B_outsideo );
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire A_internal; // From u0 of moduleA.v
+ wire B_internal; // From u1 of moduleB.v
+ // End of automatics
+
+ //-----------------------------------------------------------------------------
+ // instantiate module A
+ //-----------------------------------------------------------------------------
+
+ /* moduleA AUTO_TEMPLATE (
+ .[iot]_\(.*\) (@"(vl-prefix-i-o \\"\1\\")"\1[]),
+ ); */
+
+ moduleA u0(
+ /*AUTOINST*/
+ // Outputs
+ .o_A_outsideo (o_A_outsideo), // Templated
+ .o_A_internal (A_internal), // Templated
+ // Inputs
+ .i_A_outsidei (i_A_outsidei), // Templated
+ .i_B_internal (B_internal)); // Templated
+
+
+ //-----------------------------------------------------------------------------
+ // instantiate module B
+ //-----------------------------------------------------------------------------
+
+ /* moduleB AUTO_TEMPLATE (
+ .[iot]_\(.*\) (@"(vl-prefix-i-o \\"\1\\")"\1[]),
+ ); */
+
+ moduleB u1(
+ /*AUTOINST*/
+ // Outputs
+ .o_B_outsideo (o_B_outsideo), // Templated
+ .o_B_internal (B_internal), // Templated
+ // Inputs
+ .i_B_outsidei (i_B_outsidei), // Templated
+ .i_A_internal (A_internal)); // Templated
+
+
+endmodule
+
+module moduleA (
+ input i_A_outsidei,
+ output o_A_outsideo,
+
+ input i_B_internal,
+ output o_A_internal
+ );
+ /*AUTOTIEOFF*/
+ // Beginning of automatic tieoffs (for this module's unterminated outputs)
+ wire o_A_internal = 1'h0;
+ wire o_A_outsideo = 1'h0;
+ // End of automatics
+endmodule
+
+module moduleB (
+ input i_B_outsidei,
+ output o_B_outsideo,
+
+ input i_A_internal,
+ output o_B_internal
+ );
+ /*AUTOTIEOFF*/
+ // Beginning of automatic tieoffs (for this module's unterminated outputs)
+ wire o_B_internal = 1'h0;
+ wire o_B_outsideo = 1'h0;
+ // End of automatics
+endmodule
+
+/*
+ Local Variables:
+ eval:
+ (defun vl-prefix-i-o (basename)
+ (cond ((assoc (concat "i_" basename)
+ (verilog-decls-get-inputs moddecls))
+ "i_")
+ ((assoc (concat "o_" basename)
+ (verilog-decls-get-outputs moddecls))
+ "o_")
+ ((assoc (concat "t_" basename)
+ (verilog-decls-get-inouts moddecls))
+ "t_")
+ (t "")))
+ End:
+*/
diff --git a/tests/autoinst_mccoy.v b/tests/autoinst_mccoy.v
new file mode 100644
index 0000000..0d20658
--- /dev/null
+++ b/tests/autoinst_mccoy.v
@@ -0,0 +1,33 @@
+module top
+
+ // no-connecting unused outputs of an interface and tying only inputs to gnd.
+
+ // Requested:
+ //
+ // /* xx AUTO_TEMPLATE (
+ //.TWI_\(.*\) @"(vl-dir (input)" ({@"vl-width"{1'b0}}),
+ //.TWI_\(.*\) @"(vl-dir (output)" (),
+ //);
+ // */
+
+ /* xx AUTO_TEMPLATE (
+ .TWI_\(.*\) (@"(if (equal vl-dir \\"output\\") \\"\\" (concat vl-width \\"'b0\\"))"),
+ );
+ */
+
+ xx XX (/*AUTOINST*/
+ // Outputs
+ .TWI_qb (), // Templated
+ // Inputs
+ .clk (clk),
+ .TWI_ia (1'b0), // Templated
+ .TWI_iw (16'b0)); // Templated
+endmodule
+
+module xx
+ (input clk,
+
+ input TWI_ia,
+ input [15:0] TWI_iw,
+ output TWI_qb);
+endmodule
diff --git a/tests/autoinst_moddefine.v b/tests/autoinst_moddefine.v
new file mode 100644
index 0000000..de341bf
--- /dev/null
+++ b/tests/autoinst_moddefine.v
@@ -0,0 +1,38 @@
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008-2008 by Wilson Snyder.
+
+module autoinst_moddefine (/*AUTOARG*/);
+
+ /*AUTOWIRE*/
+
+`define SUBMOD_A submod_mod
+`define SUBNAME_B subname_b
+
+ `SUBMOD_A `SUBNAME_B
+ (/*AUTOINST*/);
+
+ `SUBMOD_UNDEFED subundefed
+ (/*AUTOINST*/);
+
+ submod_decl_from_def subundefed
+ (/*AUTOINST*/);
+
+endmodule
+
+module submod_mod (/*AUTOARG*/);
+ input a;
+ output q;
+endmodule
+
+module SUBMOD_UNDEFED (/*AUTOARG*/);
+ output q;
+endmodule
+
+`define SUBMOD_DECL submod_decl_from_def
+module `SUBMOD_DECL (/*AUTOARG*/);
+ output q;
+endmodule
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests/autoinst_modport_param.v b/tests/autoinst_modport_param.v
new file mode 100644
index 0000000..281377d
--- /dev/null
+++ b/tests/autoinst_modport_param.v
@@ -0,0 +1,38 @@
+//bug565
+
+module InstModule
+ (svi.master svi_modport,
+ input clk,
+ svi svi_nomodport);
+endmodule
+
+module InstModule1 #
+ (parameter TCQ = 100)
+ (svi.master svi_modport,
+ input clk,
+ svi svi_nomodport);
+endmodule
+
+module top;
+ InstModule instName
+ (/*AUTOINST*/
+ // Interfaces
+ .svi_modport (svi_modport.master),
+ .svi_nomodport (svi_nomodport),
+ // Inputs
+ .clk (clk));
+
+ InstModule1 instName1
+ (/*AUTOINST*/
+ // Interfaces
+ .svi_modport (svi_modport.master),
+ .svi_nomodport (svi_nomodport),
+ // Inputs
+ .clk (clk));
+
+endmodule
+
+// Local Variables:
+// verilog-library-directories:(".")
+// verilog-library-extensions:(".v" ".sv")
+// End:
diff --git a/tests/autoinst_mplist.sv b/tests/autoinst_mplist.sv
new file mode 100644
index 0000000..2fcebc2
--- /dev/null
+++ b/tests/autoinst_mplist.sv
@@ -0,0 +1,52 @@
+
+// Parent module
+// Specifies modport for interfaces in header.
+// Has child modules which do the same.
+
+module autoinst_mplist
+ (
+ // --------------------------------------------------------------------------
+ // Port Declarations
+ // --------------------------------------------------------------------------
+
+ input clk,
+ input reset_n,
+
+ // Top-level interfaces
+ mbl_if.master msg_resp_if
+
+ );
+
+ mbl_if msg_req_if; // Some internal interface
+
+ // --------------------------------------------------------------------------
+ // Packages and Local Declarations
+ // --------------------------------------------------------------------------
+
+ /*AUTOLOGIC*/
+
+
+ // --------------------------------------------------------------------------
+ // Module Body
+ // --------------------------------------------------------------------------
+
+ // For the module instance below, interface ports should be
+ // connected (per standard AUTOINST fashion) but *without*
+ // explicitly specifying the modport.
+ //
+ // VCS (and likely other Synopsys tools) don't expect to see a
+ // modport being "respecified" here.
+
+ autoinst_mplist_child child
+ (/*AUTOINST*/);
+
+
+endmodule
+
+/*
+ Local Variables:
+ verilog-typedef-regexp:"_t$"
+ verilog-library-directories:(".")
+ verilog-library-extensions:(".sv")
+ End:
+ */
diff --git a/tests/autoinst_mplist_child.sv b/tests/autoinst_mplist_child.sv
new file mode 100644
index 0000000..2ae7a3e
--- /dev/null
+++ b/tests/autoinst_mplist_child.sv
@@ -0,0 +1,33 @@
+// Child module
+// ... with interface modport specified in module header
+
+module autoinst_mplist_child
+ (
+ // --------------------------------------------------------------------------
+ // Port Declarations
+ // --------------------------------------------------------------------------
+
+ input clk,
+ input reset_n,
+
+ // Yeah, let's have an interface
+ autoinst_mplist_mbl_if.slave msg_req_if,
+ autoinst_mplist_mbl_if.master msg_resp_if,
+
+ // There are likely other signals present, too
+ output logic msg_busy,
+ output logic mem_rd_req,
+ input mem_rd_gnt
+ );
+
+ // Really snazzy RTL follows...
+
+endmodule
+
+/*
+ Local Variables:
+ verilog-typedef-regexp:"_t$"
+ verilog-library-directories:(".")
+ verilog-library-extensions:(".sv")
+ End:
+ */
diff --git a/tests/autoinst_mplist_mbl_if.sv b/tests/autoinst_mplist_mbl_if.sv
new file mode 100644
index 0000000..3810f0d
--- /dev/null
+++ b/tests/autoinst_mplist_mbl_if.sv
@@ -0,0 +1,27 @@
+// Example interface definition with at least one modport.
+
+interface autoinst_mplist_mbl_if ();
+
+ logic sof;
+ logic eof;
+ logic [31:0] data;
+ logic ready;
+ logic valid;
+
+ modport master(
+ output data,
+ output sof,
+ output eof,
+ output valid,
+ input ready
+ );
+
+ modport slave(
+ input data,
+ input sof,
+ input eof,
+ input valid,
+ output ready
+ );
+
+endinterface
diff --git a/tests/autoinst_multidim.v b/tests/autoinst_multidim.v
new file mode 100644
index 0000000..dab3038
--- /dev/null
+++ b/tests/autoinst_multidim.v
@@ -0,0 +1,58 @@
+module top;
+ /*AUTOLOGIC*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic sig1; // From u_x of x.v
+ logic [A-1:0] sig2; // From u_x of x.v
+ logic [A-1:0] [B-1:0] sig3; // From u_x of x.v
+ logic [A-1:0][B-1:0] [C-1:0] sig4; // From u_x of x.v
+ logic [A-1:0][B-1:0][C-1:0] [D-1:0] sig5; // From u_x of x.v
+ logic vsig1; // From u_x of x.v
+ logic vsig2 [W-1:0]; // From u_x of x.v
+ logic vsig3 [W-1:0][X-1:0]; // From u_x of x.v
+ logic vsig4 [W-1:0][X-1:0][Y-1:0];// From u_x of x.v
+ logic vsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];// From u_x of x.v
+ logic zsig1; // From u_x of x.v
+ logic [A-1:0] zsig2 [W-1:0]; // From u_x of x.v
+ logic [A-1:0] [B-1:0] zsig3 [W-1:0][X-1:0]; // From u_x of x.v
+ logic [A-1:0][B-1:0] [C-1:0] zsig4 [W-1:0][X-1:0][Y-1:0];// From u_x of x.v
+ logic [A-1:0][B-1:0][C-1:0] [D-1:0] zsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];// From u_x of x.v
+ // End of automatics
+
+ x u_x (/*AUTOINST*/
+ // Outputs
+ .sig1 (sig1),
+ .sig2 (sig2[A-1:0]),
+ .sig3 (sig3/*[A-1:0][B-1:0]*/),
+ .sig4 (sig4/*[A-1:0][B-1:0][C-1:0]*/),
+ .sig5 (sig5/*[A-1:0][B-1:0][C-1:0][D-1:0]*/),
+ .vsig1 (vsig1),
+ .vsig2 (vsig2/*.[W-1:0]*/),
+ .vsig3 (vsig3/*.[W-1:0][X-1:0]*/),
+ .vsig4 (vsig4/*.[W-1:0][X-1:0][Y-1:0]*/),
+ .vsig5 (vsig5/*.[W-1:0][X-1:0][Y-1:0][Z-1:0]*/),
+ .zsig1 (zsig1),
+ .zsig2 (zsig2/*[A-1:0].[W-1:0]*/),
+ .zsig3 (zsig3/*[A-1:0][B-1:0].[W-1:0][X-1:0]*/),
+ .zsig4 (zsig4/*[A-1:0][B-1:0][C-1:0].[W-1:0][X-1:0][Y-1:0]*/),
+ .zsig5 (zsig5/*[A-1:0][B-1:0][C-1:0][D-1:0].[W-1:0][X-1:0][Y-1:0][Z-1:0]*/));
+endmodule // top
+
+module x;
+ output sig1;
+ output [A-1:0] sig2;
+ output [A-1:0][B-1:0] sig3;
+ output [A-1:0][B-1:0][C-1:0] sig4;
+ output [A-1:0][B-1:0][C-1:0][D-1:0] sig5;
+
+ output vsig1;
+ output vsig2 [W-1:0];
+ output vsig3 [W-1:0][X-1:0];
+ output vsig4 [W-1:0][X-1:0][Y-1:0];
+ output vsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];
+
+ output zsig1;
+ output [A-1:0] zsig2 [W-1:0];
+ output [A-1:0][B-1:0] zsig3 [W-1:0][X-1:0];
+ output [A-1:0][B-1:0][C-1:0] zsig4 [W-1:0][X-1:0][Y-1:0];
+ output [A-1:0][B-1:0][C-1:0][D-1:0] zsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];
+endmodule
diff --git a/tests/autoinst_multitemplate.v b/tests/autoinst_multitemplate.v
new file mode 100644
index 0000000..8e45439
--- /dev/null
+++ b/tests/autoinst_multitemplate.v
@@ -0,0 +1,51 @@
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Wilson Snyder.
+
+// Reported by Julian Gorfajn <jig1@cornell.edu>
+
+module autoinst_multitemplate ();
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input Boo1; // To suba1 of SubA.v
+ input Boo2; // To suba2 of SubB.v
+ input Boo3; // To suba3 of SubC.v
+ input b; // To suba2 of SubB.v
+ input c; // To suba3 of SubC.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+
+ /*AUTOWIRE*/
+
+ wire [3:0] f4_dotnamed;
+
+ /*
+ SubA AUTO_TEMPLATE
+ SubB AUTO_TEMPLATE
+ SubC AUTO_TEMPLATE (
+ .a (Boo@),
+ );*/
+
+ SubA suba1 (/*AUTOINST*/
+ // Inputs
+ .a (Boo1)); // Templated
+ SubB suba2 (/*AUTOINST*/
+ // Inputs
+ .a (Boo2), // Templated
+ .b (b));
+ SubC suba3 (/*AUTOINST*/
+ // Inputs
+ .a (Boo3), // Templated
+ .c (c));
+
+endmodule
+
+module SubA (input a);
+endmodule
+
+module SubB (input a,input b);
+endmodule
+
+module SubC (input a,input c );
+endmodule
diff --git a/tests/autoinst_name_bug245.v b/tests/autoinst_name_bug245.v
new file mode 100644
index 0000000..84e48d9
--- /dev/null
+++ b/tests/autoinst_name_bug245.v
@@ -0,0 +1,126 @@
+module autoinst_name_bug245 (
+ );
+
+ /*AUTOINPUT*/
+
+ /*AUTOOUTPUT*/
+
+ /*AUTOWIRE*/
+
+ wire [3:0] f4_dotnamed;
+
+ /*Sub AUTO_TEMPLATE (
+ .dtmp_NO (d_NO),
+ .etmp_dotnamed (etmp_dotnamed),
+ );*/
+
+ Sub sub (
+ .bign1_dotnamed,
+ // Outputs
+ .bign2_dotnamed,
+ /*AUTOINST*/);
+
+endmodule
+
+module Sub
+ (
+ input logic clk,
+ output [2:0] a_NO,
+ output [3:0] f4_dotnamed,
+ output bign1_dotnamed,
+ output [1:0] bign2_dotnamed,
+ output c_dotnamed,
+ output dtmp_NO,
+ output etmp_dotnamed,
+ input \escaped*dot*named
+ );
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-dot-name: t
+// verilog-auto-inst-vector: nil
+// End:
+module autoinst_name_bug245 (
+ );
+
+ /*AUTOINPUT*/
+
+ /*AUTOOUTPUT*/
+
+ /*AUTOWIRE*/
+
+ wire [3:0] f4_dotnamed;
+
+ /*Sub AUTO_TEMPLATE (
+ .dtmp_NO (d_NO),
+ .etmp_dotnamed (etmp_dotnamed),
+ );*/
+
+ Sub sub (
+ .bign1_dotnamed,
+ // Outputs
+ .bign2_dotnamed,
+ /*AUTOINST*/);
+
+endmodule
+
+module Sub
+ (
+ input logic clk,
+ output [2:0] a_NO,
+ output [3:0] f4_dotnamed,
+ output bign1_dotnamed,
+ output [1:0] bign2_dotnamed,
+ output c_dotnamed,
+ output dtmp_NO,
+ output etmp_dotnamed,
+ input \escaped*dot*named
+ );
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-dot-name: t
+// verilog-auto-inst-vector: nil
+// End:
+module autoinst_name_bug245 (
+ );
+
+ /*AUTOINPUT*/
+
+ /*AUTOOUTPUT*/
+
+ /*AUTOWIRE*/
+
+ wire [3:0] f4_dotnamed;
+
+ /*Sub AUTO_TEMPLATE (
+ .dtmp_NO (d_NO),
+ .etmp_dotnamed (etmp_dotnamed),
+ );*/
+
+ Sub sub (
+ .bign1_dotnamed,
+ // Outputs
+ .bign2_dotnamed,
+ /*AUTOINST*/);
+
+endmodule
+
+module Sub
+ (
+ input logic clk,
+ output [2:0] a_NO,
+ output [3:0] f4_dotnamed,
+ output bign1_dotnamed,
+ output [1:0] bign2_dotnamed,
+ output c_dotnamed,
+ output dtmp_NO,
+ output etmp_dotnamed,
+ input \escaped*dot*named
+ );
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-dot-name: t
+// verilog-auto-inst-vector: nil
+// End:
diff --git a/tests/autoinst_nicholl.v b/tests/autoinst_nicholl.v
new file mode 100644
index 0000000..1cacd4f
--- /dev/null
+++ b/tests/autoinst_nicholl.v
@@ -0,0 +1,62 @@
+module sub1 (/*AUTOARG*/
+ // Inputs
+ bus1
+ );
+
+ input [0:3] bus1;
+
+endmodule
+
+module sub2 (/*AUTOARG*/
+ // Inputs
+ bus2
+ );
+
+ input [0:3] bus2;
+
+endmodule
+
+module sub3 (/*AUTOARG*/
+ // Outputs
+ bus1, bus2
+ );
+
+ output [0:3] bus1;
+ output [4:7] bus2;
+
+endmodule
+
+
+module top (/*AUTOARG*/);
+
+ wire [4:7] bus2; // From sub3 of sub3.v
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ // End of automatics
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [0:3] bus1; // From sub3 of sub3.v
+ // End of automatics
+
+ sub1 sub1 (/*AUTOINST*/
+ // Inputs
+ .bus1 (bus1[0:3]));
+
+ sub2 sub2 (/*AUTOINST*/
+ // Inputs
+ .bus2 (bus2[0:3]));
+
+ sub3 sub3 (/*AUTOINST*/
+ // Outputs
+ .bus1 (bus1[0:3]),
+ .bus2 (bus2));
+
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-vector:nil
+// End:
diff --git a/tests/autoinst_overflow_bug250.v b/tests/autoinst_overflow_bug250.v
new file mode 100644
index 0000000..74506be
--- /dev/null
+++ b/tests/autoinst_overflow_bug250.v
@@ -0,0 +1,429 @@
+module TEST_TOP (
+ );
+/*TEST AUTO_TEMPLATE
+ (
+
+ .abcd_efgh_ijklmno_f02_out_c(abcdefg_f02_clroilouull[5]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_be_2(abcdefg_f10_eg2_ab_cdefghijklm[49]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_fh_2(abcdefg_f08_eg0_ab_a_fghi[6]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ch(abcdefg_f09_eg1_ab_cdefghijklm[36]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ej_1(abcdefg_f10_eg2_ab_cdefghijklm[14]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ga_1(abcdefg_f10_eg2_ab_cdefghijklm[3]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_fe(abcdefg_f09_eg1_ab_cdefghijklm[9]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bi_2(abcdefg_f08_eg0_ab_cdefghijklm[45]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_24_1(abcdefg_f09_eg1_ab_fghijklm[24]),
+ .abcd_efgh_ijklmno_f01_oilouull_o_0_1(abcdefg_f01_oilouull[0]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_cc_2(abcdefg_f10_eg2_ab_cdefghijklm[41]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_e_2(abcdefg_f11_eg3_ab_cdefghijklm[59]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_54_1(abcdefg_f11_eg3_ab_fghijklm[54]),
+ .abcd_efgh_ijklmno_f03_oilouull_o_3_1(abcdefg_f03_oilouull[3]),
+ .abcd_efgh_ijklmno_f02_out_h_2(abcdefg_f02_a_zxdf[0]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_g_1(abcdefg_f11_eg3_ab_a_fghi[57]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_b_2(abcdefg_f08_eg0_ab_cdefghijklm[62]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_9_1(abcdefg_f11_eg3_ab_fghijklm[9]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_di_1(abcdefg_f09_eg1_ab_a_fghi[25]),
+ .abcd_efgh_ijklmno_f00_out_h_2(abcdefg_f00_a_zxdf[0]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_cg_2(abcdefg_f11_eg3_ab_cdefghijklm[37]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_eh_2(abcdefg_f10_eg2_ab_a_fghi[16]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_di_1(abcdefg_f08_eg0_ab_cdefghijklm[25]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ec_2(abcdefg_f11_eg3_ab_cdefghijklm[21]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_d_1(abcdefg_f11_eg3_ab_a_fghi[60]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_bh_1(abcdefg_f11_eg3_ab_a_fghi[46]),
+ .abcd_efgh_ijklmno_f00_out_f(abcdefg_f00_clroilouull[2]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_52_1(abcdefg_f11_eg3_ab_fghijklm[52]),
+ .abcd_efgh_ijklmno_f02_out_g(abcdefg_f02_clroilouull[1]),
+ .abcd_efgh_ijklmno_f07_out_e(abcdefg_f07_clroilouull[3]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ff_2(abcdefg_f10_eg2_ab_a_fghi[8]),
+ .abcd_efgh_ijklmno_f04_out_h(abcdefg_f04_clroilouull[0]),
+ .abcd_efgh_ijklmno_f04_out_g_2(abcdefg_f04_a_zxdf[1]),
+ .abcd_efgh_ijklmno_f02_out_c_2(abcdefg_f02_a_zxdf[5]),
+ .abcd_efgh_ijklmno_f04_out_a_3(abcdefg_f04_a_zxdf[7]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_fa_1(abcdefg_f08_eg0_ab_cdefghijklm[13]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_ed_2(abcdefg_f08_eg0_ab_a_fghi[20]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ea_2(abcdefg_f10_eg2_ab_a_fghi[23]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_c_2(abcdefg_f10_eg2_ab_cdefghijklm[61]),
+ .abcd_efgh_ijklmno_f03_oilouull_o_0_1(abcdefg_f03_oilouull[0]),
+ .abcd_efgh_ijklmno_f00_out_e_2(abcdefg_f00_a_zxdf[3]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bg_3(abcdefg_f10_eg2_ab_a_fghi[47]),
+ .abcd_efgh_ijklmno_f05_oilouull_o_2_1(abcdefg_f05_oilouull[2]),
+ .abcd_efgh_ijklmno_f01_out_h_2(abcdefg_f01_a_zxdf[0]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_44_1(abcdefg_f10_eg2_ab_fghijklm[44]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_j_3(abcdefg_f08_eg0_ab_a_fghi[54]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_39_1(abcdefg_f08_eg0_ab_fghijklm[39]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_fj_2(abcdefg_f08_eg0_ab_a_fghi[4]),
+ .abcd_efgh_ijklmno_f05_out_h(abcdefg_f05_clroilouull[0]),
+ .abcd_efgh_ijklmno_f05_out_d_2(abcdefg_f05_a_zxdf[4]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_gb_2(abcdefg_f10_eg2_ab_a_fghi[2]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_cb_3(abcdefg_f10_eg2_ab_a_fghi[42]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_52_1(abcdefg_f10_eg2_ab_fghijklm[52]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_be_2(abcdefg_f11_eg3_ab_cdefghijklm[49]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_42_1(abcdefg_f11_eg3_ab_fghijklm[42]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ci_1(abcdefg_f11_eg3_ab_a_fghi[35]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fh_1(abcdefg_f10_eg2_ab_cdefghijklm[6]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_24_1(abcdefg_f08_eg0_ab_fghijklm[24]),
+ .abcd_efgh_ijklmno_f02_out_g_2(abcdefg_f02_a_zxdf[1]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_d_2(abcdefg_f11_eg3_ab_cdefghijklm[60]),
+ .abcd_efgh_ijklmno_f06_out_d_2(abcdefg_f06_a_zxdf[4]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ea_1(abcdefg_f09_eg1_ab_a_fghi[23]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_dh_2(abcdefg_f11_eg3_ab_cdefghijklm[26]),
+ .abcd_efgh_ijklmno_f04_oilouull_o_7_2(abcdefg_f04_oilouull[7]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_dh_1(abcdefg_f09_eg1_ab_a_fghi[26]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_18_1(abcdefg_f08_eg0_ab_fghijklm[18]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ba_2(abcdefg_f11_eg3_ab_cdefghijklm[53]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ce_1(abcdefg_f11_eg3_ab_a_fghi[39]),
+ .abcd_efgh_ijklmno_f03_oilouull_o_5_1(abcdefg_f03_oilouull[5]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ef_1(abcdefg_f09_eg1_ab_a_fghi[18]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_cj_2(abcdefg_f08_eg0_ab_cdefghijklm[34]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_j_2(abcdefg_f08_eg0_ab_cdefghijklm[54]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bh_3(abcdefg_f08_eg0_ab_a_fghi[46]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_cb_1(abcdefg_f09_eg1_ab_a_fghi[42]),
+ .abcd_efgh_ijklmno_f01_oilouull_o_6_2(abcdefg_f01_oilouull[6]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ba_3(abcdefg_f10_eg2_ab_a_fghi[53]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_0_1(abcdefg_f11_eg3_ab_fghijklm[0]),
+ .abcd_efgh_ijklmno_f06_out_h_2(abcdefg_f06_a_zxdf[0]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_51_1(abcdefg_f08_eg0_ab_fghijklm[51]),
+ .abcd_efgh_ijklmno_f06_oilouull_o_4_1(abcdefg_f06_oilouull[4]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_10_1(abcdefg_f08_eg0_ab_fghijklm[10]),
+ .abcd_efgh_ijklmno_f01_oilouull_o_7_2(abcdefg_f01_oilouull[7]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_da_2(abcdefg_f11_eg3_ab_cdefghijklm[33]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_e_1(abcdefg_f09_eg1_ab_a_fghi[59]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_22_1(abcdefg_f08_eg0_ab_fghijklm[22]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_db_2(abcdefg_f11_eg3_ab_cdefghijklm[32]),
+ .abcd_efgh_ijklmno_f01_oilouull_o_2_1(abcdefg_f01_oilouull[2]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_ci_3(abcdefg_f08_eg0_ab_a_fghi[35]),
+ .abcd_efgh_ijklmno_f07_oilouull_o_6_2(abcdefg_f07_oilouull[6]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_62_1(abcdefg_f11_eg3_ab_fghijklm[62]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_34_1(abcdefg_f10_eg2_ab_fghijklm[34]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_9_1(abcdefg_f10_eg2_ab_fghijklm[9]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_13_1(abcdefg_f10_eg2_ab_fghijklm[13]),
+ .abcd_efgh_ijklmno_f05_oilouull_o_7_2(abcdefg_f05_oilouull[7]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ch_1(abcdefg_f11_eg3_ab_a_fghi[36]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fd_1(abcdefg_f10_eg2_ab_cdefghijklm[10]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fc_2(abcdefg_f10_eg2_ab_a_fghi[11]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ei_1(abcdefg_f09_eg1_ab_a_fghi[15]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_37_1(abcdefg_f08_eg0_ab_fghijklm[37]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_gb(abcdefg_f09_eg1_ab_cdefghijklm[2]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_7_1(abcdefg_f10_eg2_ab_fghijklm[7]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_dg_2(abcdefg_f11_eg3_ab_cdefghijklm[27]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ce(abcdefg_f09_eg1_ab_cdefghijklm[39]),
+ .abcd_efgh_ijklmno_f07_out_d_2(abcdefg_f07_a_zxdf[4]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_cd_2(abcdefg_f08_eg0_ab_cdefghijklm[40]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_57_1(abcdefg_f10_eg2_ab_fghijklm[57]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_63_1(abcdefg_f10_eg2_ab_fghijklm[63]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_j_1(abcdefg_f09_eg1_ab_a_fghi[54]),
+ .abcd_efgh_ijklmno_f00_out_a(abcdefg_f00_clroilouull[7]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_46_1(abcdefg_f09_eg1_ab_fghijklm[46]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_39_1(abcdefg_f10_eg2_ab_fghijklm[39]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_28_1(abcdefg_f08_eg0_ab_fghijklm[28]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_20_1(abcdefg_f08_eg0_ab_fghijklm[20]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_51_1(abcdefg_f11_eg3_ab_fghijklm[51]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ci_1(abcdefg_f09_eg1_ab_a_fghi[35]),
+ .abcd_efgh_ijklmno_f04_out_h_2(abcdefg_f04_a_zxdf[0]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_bd(abcdefg_f09_eg1_ab_cdefghijklm[50]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_dg_1(abcdefg_f10_eg2_ab_cdefghijklm[27]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_23_1(abcdefg_f09_eg1_ab_fghijklm[23]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_1_2(abcdefg_f09_eg1_ab_fghijklm[1]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bc_2(abcdefg_f08_eg0_ab_cdefghijklm[51]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bc_3(abcdefg_f10_eg2_ab_a_fghi[51]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_62_1(abcdefg_f08_eg0_ab_fghijklm[62]),
+ .abcd_efgh_ijklmno_f01_out_g_2(abcdefg_f01_a_zxdf[1]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_23_1(abcdefg_f11_eg3_ab_fghijklm[23]),
+ .abcd_efgh_ijklmno_f03_out_e_2(abcdefg_f03_a_zxdf[3]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_b_1(abcdefg_f09_eg1_ab_a_fghi[62]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_eh(abcdefg_f09_eg1_ab_cdefghijklm[16]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_dh_1(abcdefg_f10_eg2_ab_cdefghijklm[26]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_34_1(abcdefg_f09_eg1_ab_fghijklm[34]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_gc_1(abcdefg_f10_eg2_ab_cdefghijklm[1]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_cg_2(abcdefg_f08_eg0_ab_cdefghijklm[37]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_13_1(abcdefg_f11_eg3_ab_fghijklm[13]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_2_1(abcdefg_f08_eg0_ab_fghijklm[2]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_fb(abcdefg_f09_eg1_ab_cdefghijklm[12]),
+ .abcd_efgh_ijklmno_f00_oilouull_o_6_2(abcdefg_f00_oilouull[6]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_h_3(abcdefg_f08_eg0_ab_a_fghi[56]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_38_1(abcdefg_f09_eg1_ab_fghijklm[38]),
+ .abcd_efgh_ijklmno_f00_out_c(abcdefg_f00_clroilouull[5]),
+ .abcd_efgh_ijklmno_f06_out_a_3(abcdefg_f06_a_zxdf[7]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_60_1(abcdefg_f09_eg1_ab_fghijklm[60]),
+ .abcd_efgh_ijklmno_f06_oilouull_o_2_1(abcdefg_f06_oilouull[2]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_8_1(abcdefg_f09_eg1_ab_fghijklm[8]),
+ .abcd_efgh_ijklmno_f03_out_f(abcdefg_f03_clroilouull[2]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_dj_1(abcdefg_f08_eg0_ab_cdefghijklm[24]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bg_2(abcdefg_f08_eg0_ab_cdefghijklm[47]),
+ .abcd_efgh_ijklmno_f01_oilouull_o_4_1(abcdefg_f01_oilouull[4]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ef_2(abcdefg_f10_eg2_ab_a_fghi[18]),
+ .abcd_efgh_ijklmno_f01_out_a_3(abcdefg_f01_a_zxdf[7]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_12_1(abcdefg_f08_eg0_ab_fghijklm[12]),
+ .abcd_efgh_ijklmno_f07_out_c_2(abcdefg_f07_a_zxdf[5]),
+ .abcd_efgh_ijklmno_f00_out_e(abcdefg_f00_clroilouull[3]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ca_1(abcdefg_f09_eg1_ab_a_fghi[43]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_eg_2(abcdefg_f08_eg0_ab_a_fghi[17]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_be_1(abcdefg_f11_eg3_ab_a_fghi[49]),
+ .abcd_efgh_ijklmno_f06_out_d(abcdefg_f06_clroilouull[4]),
+ .abcd_efgh_ijklmno_f00_out_g(abcdefg_f00_clroilouull[1]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_b(abcdefg_f09_eg1_ab_cdefghijklm[62]),
+ .abcd_efgh_ijklmno_f00_out_f_2(abcdefg_f00_a_zxdf[2]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_gc_1(abcdefg_f09_eg1_ab_a_fghi[1]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ca_1(abcdefg_f11_eg3_ab_a_fghi[43]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ea(abcdefg_f09_eg1_ab_cdefghijklm[23]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_12_1(abcdefg_f10_eg2_ab_fghijklm[12]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_gd_2(abcdefg_f11_eg3_ab_cdefghijklm[0]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_i_1(abcdefg_f09_eg1_ab_a_fghi[55]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_e_2(abcdefg_f08_eg0_ab_cdefghijklm[59]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ff(abcdefg_f09_eg1_ab_cdefghijklm[8]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_17_1(abcdefg_f11_eg3_ab_fghijklm[17]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_be_3(abcdefg_f10_eg2_ab_a_fghi[49]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_20_1(abcdefg_f11_eg3_ab_fghijklm[20]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_bc_1(abcdefg_f11_eg3_ab_a_fghi[51]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_43_1(abcdefg_f09_eg1_ab_fghijklm[43]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_54_1(abcdefg_f09_eg1_ab_fghijklm[54]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_be_2(abcdefg_f08_eg0_ab_cdefghijklm[49]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_36_1(abcdefg_f10_eg2_ab_fghijklm[36]),
+ .abcd_efgh_ijklmno_f05_out_h_2(abcdefg_f05_a_zxdf[0]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_cc(abcdefg_f09_eg1_ab_cdefghijklm[41]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_3_1(abcdefg_f11_eg3_ab_fghijklm[3]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ff_1(abcdefg_f11_eg3_ab_a_fghi[8]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_19_2(abcdefg_f11_eg3_ab_fghijklm[19]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_bi_1(abcdefg_f11_eg3_ab_a_fghi[45]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_49_1(abcdefg_f08_eg0_ab_fghijklm[49]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ee_1(abcdefg_f10_eg2_ab_cdefghijklm[19]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_29_1(abcdefg_f08_eg0_ab_fghijklm[29]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_29_1(abcdefg_f09_eg1_ab_fghijklm[29]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ed(abcdefg_f09_eg1_ab_cdefghijklm[20]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_de(abcdefg_f09_eg1_ab_cdefghijklm[29]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_dg_2(abcdefg_f10_eg2_ab_a_fghi[27]),
+ .abcd_efgh_ijklmno_f04_oilouull_o_2_1(abcdefg_f04_oilouull[2]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_eb_2(abcdefg_f10_eg2_ab_a_fghi[22]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ea_2(abcdefg_f11_eg3_ab_cdefghijklm[23]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fc_1(abcdefg_f10_eg2_ab_cdefghijklm[11]),
+ .abcd_efgh_ijklmno_f06_out_g(abcdefg_f06_clroilouull[1]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_61_1(abcdefg_f09_eg1_ab_fghijklm[61]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ee_2(abcdefg_f10_eg2_ab_a_fghi[19]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_47_1(abcdefg_f11_eg3_ab_fghijklm[47]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_36_1(abcdefg_f08_eg0_ab_fghijklm[36]),
+ .abcd_efgh_ijklmno_f07_oilouull_o_0_1(abcdefg_f07_oilouull[0]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_j_1(abcdefg_f11_eg3_ab_a_fghi[54]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_52_1(abcdefg_f08_eg0_ab_fghijklm[52]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_gd_1(abcdefg_f11_eg3_ab_a_fghi[0]),
+ .abcd_efgh_ijklmno_f07_out_h_2(abcdefg_f07_a_zxdf[0]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_cg_1(abcdefg_f09_eg1_ab_a_fghi[37]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_8_1(abcdefg_f10_eg2_ab_fghijklm[8]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_fh_1(abcdefg_f11_eg3_ab_a_fghi[6]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_52_1(abcdefg_f09_eg1_ab_fghijklm[52]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ci_2(abcdefg_f11_eg3_ab_cdefghijklm[35]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_15_1(abcdefg_f10_eg2_ab_fghijklm[15]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_df(abcdefg_f09_eg1_ab_cdefghijklm[28]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ee(abcdefg_f09_eg1_ab_cdefghijklm[19]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_bd_1(abcdefg_f11_eg3_ab_a_fghi[50]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_fe_1(abcdefg_f11_eg3_ab_a_fghi[9]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_di_2(abcdefg_f08_eg0_ab_a_fghi[25]),
+ .abcd_efgh_ijklmno_f00_out_d(abcdefg_f00_clroilouull[4]),
+ .abcd_efgh_ijklmno_f07_oilouull_o_5_1(abcdefg_f07_oilouull[5]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_41_1(abcdefg_f09_eg1_ab_fghijklm[41]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_cf_2(abcdefg_f08_eg0_ab_cdefghijklm[38]),
+ .abcd_efgh_ijklmno_f05_out_b_3(abcdefg_f05_a_zxdf[6]),
+ .abcd_efgh_ijklmno_f03_oilouull_o_1_1(abcdefg_f03_oilouull[1]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_dg_1(abcdefg_f09_eg1_ab_a_fghi[27]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_eg(abcdefg_f09_eg1_ab_cdefghijklm[17]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ce_1(abcdefg_f09_eg1_ab_a_fghi[39]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_fi_2(abcdefg_f11_eg3_ab_cdefghijklm[5]),
+ .abcd_efgh_ijklmno_f05_out_g(abcdefg_f05_clroilouull[1]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bj_2(abcdefg_f10_eg2_ab_cdefghijklm[44]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_db(abcdefg_f09_eg1_ab_cdefghijklm[32]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_g_1(abcdefg_f09_eg1_ab_a_fghi[57]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bf_2(abcdefg_f08_eg0_ab_cdefghijklm[48]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bh_2(abcdefg_f08_eg0_ab_cdefghijklm[46]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_23_1(abcdefg_f10_eg2_ab_fghijklm[23]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_61_1(abcdefg_f10_eg2_ab_fghijklm[61]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_db_1(abcdefg_f09_eg1_ab_a_fghi[32]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_f(abcdefg_f09_eg1_ab_cdefghijklm[58]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_57_1(abcdefg_f09_eg1_ab_fghijklm[57]),
+ .abcd_efgh_ijklmno_f01_oilouull_o_1_1(abcdefg_f01_oilouull[1]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_eh_2(abcdefg_f08_eg0_ab_a_fghi[16]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_41_1(abcdefg_f11_eg3_ab_fghijklm[41]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_c_2(abcdefg_f08_eg0_ab_cdefghijklm[61]),
+ .abcd_efgh_ijklmno_f06_out_e(abcdefg_f06_clroilouull[3]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ej_1(abcdefg_f11_eg3_ab_a_fghi[14]),
+ .abcd_efgh_ijklmno_f02_oilouull_o_1_1(abcdefg_f02_oilouull[1]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_bd_2(abcdefg_f11_eg3_ab_cdefghijklm[50]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_6_1(abcdefg_f08_eg0_ab_fghijklm[6]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ee_1(abcdefg_f09_eg1_ab_a_fghi[19]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_fc_2(abcdefg_f11_eg3_ab_cdefghijklm[11]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bd_3(abcdefg_f10_eg2_ab_a_fghi[50]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_df_1(abcdefg_f08_eg0_ab_cdefghijklm[28]),
+ .abcd_efgh_ijklmno_f03_out_a(abcdefg_f03_clroilouull[7]),
+ .abcd_efgh_ijklmno_f02_oilouull_o_0_1(abcdefg_f02_oilouull[0]),
+ .abcd_efgh_ijklmno_f00_out_g_2(abcdefg_f00_a_zxdf[1]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_43_1(abcdefg_f08_eg0_ab_fghijklm[43]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_59_1(abcdefg_f08_eg0_ab_fghijklm[59]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ff_1(abcdefg_f09_eg1_ab_a_fghi[8]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bh_2(abcdefg_f10_eg2_ab_cdefghijklm[46]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_0_1(abcdefg_f09_eg1_ab_fghijklm[0]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_ec_2(abcdefg_f08_eg0_ab_a_fghi[21]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_33_1(abcdefg_f09_eg1_ab_fghijklm[33]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_fh_1(abcdefg_f09_eg1_ab_a_fghi[6]),
+ .abcd_efgh_ijklmno_f02_oilouull_o_4_1(abcdefg_f02_oilouull[4]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_31_1(abcdefg_f10_eg2_ab_fghijklm[31]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fa_1(abcdefg_f10_eg2_ab_cdefghijklm[13]),
+ .abcd_efgh_ijklmno_f05_out_f(abcdefg_f05_clroilouull[2]),
+ .abcd_efgh_ijklmno_f04_out_e_2(abcdefg_f04_a_zxdf[3]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_dd_1(abcdefg_f09_eg1_ab_a_fghi[30]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_12_1(abcdefg_f11_eg3_ab_fghijklm[12]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_bf_1(abcdefg_f09_eg1_ab_a_fghi[48]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_23_1(abcdefg_f08_eg0_ab_fghijklm[23]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_dj_2(abcdefg_f08_eg0_ab_a_fghi[24]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ci_3(abcdefg_f10_eg2_ab_a_fghi[35]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_17_1(abcdefg_f08_eg0_ab_fghijklm[17]),
+ .abcd_efgh_ijklmno_f02_out_f_2(abcdefg_f02_a_zxdf[2]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_bb_1(abcdefg_f11_eg3_ab_a_fghi[52]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_cc_1(abcdefg_f11_eg3_ab_a_fghi[41]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_f_1(abcdefg_f11_eg3_ab_a_fghi[58]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_fi(abcdefg_f09_eg1_ab_cdefghijklm[5]),
+ .abcd_efgh_ijklmno_f03_out_h(abcdefg_f03_clroilouull[0]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_e_1(abcdefg_f11_eg3_ab_a_fghi[59]),
+ .abcd_efgh_ijklmno_f01_out_b_3(abcdefg_f01_a_zxdf[6]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_55_1(abcdefg_f08_eg0_ab_fghijklm[55]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bj_3(abcdefg_f10_eg2_ab_a_fghi[44]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_d_2(abcdefg_f08_eg0_ab_cdefghijklm[60]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bi_3(abcdefg_f08_eg0_ab_a_fghi[45]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_fg_1(abcdefg_f09_eg1_ab_a_fghi[7]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ej_2(abcdefg_f10_eg2_ab_a_fghi[14]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_cb_2(abcdefg_f08_eg0_ab_cdefghijklm[42]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fi_1(abcdefg_f10_eg2_ab_cdefghijklm[5]),
+ .abcd_efgh_ijklmno_f01_out_c(abcdefg_f01_clroilouull[5]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_fa_2(abcdefg_f11_eg3_ab_cdefghijklm[13]),
+ .abcd_efgh_ijklmno_f07_out_b_3(abcdefg_f07_a_zxdf[6]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_2_1(abcdefg_f09_eg1_ab_fghijklm[2]),
+ .abcd_efgh_ijklmno_f07_oilouull_o_2_1(abcdefg_f07_oilouull[2]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ed_2(abcdefg_f10_eg2_ab_a_fghi[20]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_32_1(abcdefg_f08_eg0_ab_fghijklm[32]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_29_1(abcdefg_f10_eg2_ab_fghijklm[29]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ef_1(abcdefg_f11_eg3_ab_a_fghi[18]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_15_1(abcdefg_f09_eg1_ab_fghijklm[15]),
+ .abcd_efgh_ijklmno_f04_out_c_2(abcdefg_f04_a_zxdf[5]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_cd(abcdefg_f09_eg1_ab_cdefghijklm[40]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_57_1(abcdefg_f08_eg0_ab_fghijklm[57]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ee_2(abcdefg_f11_eg3_ab_cdefghijklm[19]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_3_1(abcdefg_f09_eg1_ab_fghijklm[3]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_20_1(abcdefg_f10_eg2_ab_fghijklm[20]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_16_1(abcdefg_f08_eg0_ab_fghijklm[16]),
+ .abcd_efgh_ijklmno_f06_oilouull_o_1_1(abcdefg_f06_oilouull[1]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_cg(abcdefg_f09_eg1_ab_cdefghijklm[37]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_cd_3(abcdefg_f10_eg2_ab_a_fghi[40]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_35_1(abcdefg_f10_eg2_ab_fghijklm[35]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_j_3(abcdefg_f10_eg2_ab_a_fghi[54]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_dc_2(abcdefg_f10_eg2_ab_a_fghi[31]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_34_1(abcdefg_f08_eg0_ab_fghijklm[34]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bi_2(abcdefg_f10_eg2_ab_cdefghijklm[45]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_48_1(abcdefg_f09_eg1_ab_fghijklm[48]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_1_2(abcdefg_f10_eg2_ab_fghijklm[1]),
+ .abcd_efgh_ijklmno_f07_out_g(abcdefg_f07_clroilouull[1]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_c_2(abcdefg_f11_eg3_ab_cdefghijklm[61]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_24_1(abcdefg_f10_eg2_ab_fghijklm[24]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fj_2(abcdefg_f10_eg2_ab_a_fghi[4]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_bi_1(abcdefg_f09_eg1_ab_a_fghi[45]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_eb_2(abcdefg_f11_eg3_ab_cdefghijklm[22]),
+ .abcd_efgh_ijklmno_f00_oilouull_o_5_1(abcdefg_f00_oilouull[5]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_30_1(abcdefg_f08_eg0_ab_fghijklm[30]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_11_1(abcdefg_f11_eg3_ab_fghijklm[11]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_26_1(abcdefg_f11_eg3_ab_fghijklm[26]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_45_1(abcdefg_f08_eg0_ab_fghijklm[45]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_dj_1(abcdefg_f10_eg2_ab_cdefghijklm[24]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_gd_1(abcdefg_f10_eg2_ab_cdefghijklm[0]),
+ .abcd_efgh_ijklmno_f05_out_b(abcdefg_f05_clroilouull[6]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_ef_2(abcdefg_f08_eg0_ab_a_fghi[18]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_dg(abcdefg_f09_eg1_ab_cdefghijklm[27]),
+ .abcd_efgh_ijklmno_f02_oilouull_o_6_2(abcdefg_f02_oilouull[6]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_39_1(abcdefg_f11_eg3_ab_fghijklm[39]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bh_3(abcdefg_f10_eg2_ab_a_fghi[46]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_fc_1(abcdefg_f08_eg0_ab_cdefghijklm[11]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_fa(abcdefg_f09_eg1_ab_cdefghijklm[13]),
+ .abcd_efgh_ijklmno_f04_out_b_3(abcdefg_f04_a_zxdf[6]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_21_1(abcdefg_f08_eg0_ab_fghijklm[21]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bc_3(abcdefg_f08_eg0_ab_a_fghi[51]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_dd_1(abcdefg_f08_eg0_ab_cdefghijklm[30]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_fc_1(abcdefg_f09_eg1_ab_a_fghi[11]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_22_1(abcdefg_f11_eg3_ab_fghijklm[22]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_14_1(abcdefg_f11_eg3_ab_fghijklm[14]),
+ .abcd_efgh_ijklmno_f02_out_d_2(abcdefg_f02_a_zxdf[4]),
+ .abcd_efgh_ijklmno_f06_out_h(abcdefg_f06_clroilouull[0]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_37_1(abcdefg_f09_eg1_ab_fghijklm[37]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_eh_1(abcdefg_f09_eg1_ab_a_fghi[16]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_12_1(abcdefg_f09_eg1_ab_fghijklm[12]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_cd_1(abcdefg_f09_eg1_ab_a_fghi[40]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_60_1(abcdefg_f11_eg3_ab_fghijklm[60]),
+ .abcd_efgh_ijklmno_f03_out_f_2(abcdefg_f03_a_zxdf[2]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_43_1(abcdefg_f11_eg3_ab_fghijklm[43]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_dc_2(abcdefg_f08_eg0_ab_a_fghi[31]),
+ .abcd_efgh_ijklmno_f07_out_b(abcdefg_f07_clroilouull[6]),
+ .abcd_efgh_ijklmno_f03_out_b_3(abcdefg_f03_a_zxdf[6]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ea_1(abcdefg_f10_eg2_ab_cdefghijklm[23]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_eg_1(abcdefg_f08_eg0_ab_cdefghijklm[17]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_fc_2(abcdefg_f08_eg0_ab_a_fghi[11]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_gc_1(abcdefg_f08_eg0_ab_cdefghijklm[1]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_da(abcdefg_f09_eg1_ab_cdefghijklm[33]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_gb_2(abcdefg_f11_eg3_ab_cdefghijklm[2]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ba_2(abcdefg_f10_eg2_ab_cdefghijklm[53]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fb_2(abcdefg_f10_eg2_ab_a_fghi[12]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ee_1(abcdefg_f11_eg3_ab_a_fghi[19]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_32_1(abcdefg_f09_eg1_ab_fghijklm[32]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_gc_2(abcdefg_f11_eg3_ab_cdefghijklm[1]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_ee_1(abcdefg_f08_eg0_ab_cdefghijklm[19]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_36_1(abcdefg_f09_eg1_ab_fghijklm[36]),
+ .abcd_efgh_ijklmno_f02_out_a(abcdefg_f02_clroilouull[7]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_9_1(abcdefg_f08_eg0_ab_fghijklm[9]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_5_1(abcdefg_f09_eg1_ab_fghijklm[5]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_bh_2(abcdefg_f11_eg3_ab_cdefghijklm[46]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_35_1(abcdefg_f09_eg1_ab_fghijklm[35]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ca(abcdefg_f09_eg1_ab_cdefghijklm[43]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_47_1(abcdefg_f08_eg0_ab_fghijklm[47]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_gc_1(abcdefg_f11_eg3_ab_a_fghi[1]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_ba_2(abcdefg_f08_eg0_ab_cdefghijklm[53]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_44_1(abcdefg_f11_eg3_ab_fghijklm[44]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_9_1(abcdefg_f09_eg1_ab_fghijklm[9]),
+ .abcd_efgh_ijklmno_f00_oilouull_o_3_1(abcdefg_f00_oilouull[3]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_fe_2(abcdefg_f11_eg3_ab_cdefghijklm[9]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ec_1(abcdefg_f09_eg1_ab_a_fghi[21]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_de_2(abcdefg_f10_eg2_ab_a_fghi[29]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_29_1(abcdefg_f11_eg3_ab_fghijklm[29]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_g_3(abcdefg_f08_eg0_ab_a_fghi[57]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fi_2(abcdefg_f10_eg2_ab_a_fghi[5]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_27_1(abcdefg_f08_eg0_ab_fghijklm[27]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_fc_1(abcdefg_f11_eg3_ab_a_fghi[11]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_42_1(abcdefg_f10_eg2_ab_fghijklm[42]),
+ .abcd_efgh_ijklmno_f04_oilouull_o_4_1(abcdefg_f04_oilouull[4]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_30_1(abcdefg_f09_eg1_ab_fghijklm[30]),
+ .abcd_efgh_ijklmno_f01_oilouull_o_3_1(abcdefg_f01_oilouull[3]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fj_1(abcdefg_f10_eg2_ab_cdefghijklm[4]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_55_1(abcdefg_f11_eg3_ab_fghijklm[55]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_42_1(abcdefg_f08_eg0_ab_fghijklm[42]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_gd(abcdefg_f09_eg1_ab_cdefghijklm[0]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_eg_1(abcdefg_f09_eg1_ab_a_fghi[17]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_8_1(abcdefg_f08_eg0_ab_fghijklm[8]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_50_1(abcdefg_f11_eg3_ab_fghijklm[50]),
+ .abcd_efgh_ijklmno_f06_out_f_2(abcdefg_f06_a_zxdf[2]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_26_1(abcdefg_f09_eg1_ab_fghijklm[26]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_30_1(abcdefg_f11_eg3_ab_fghijklm[30]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_55_1(abcdefg_f10_eg2_ab_fghijklm[55]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_df_2(abcdefg_f08_eg0_ab_a_fghi[28]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_28_1(abcdefg_f09_eg1_ab_fghijklm[28]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_22_1(abcdefg_f09_eg1_ab_fghijklm[22]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_45_1(abcdefg_f09_eg1_ab_fghijklm[45]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_46_1(abcdefg_f08_eg0_ab_fghijklm[46]),
+ .abcd_efgh_ijklmno_f01_out_f(abcdefg_f01_clroilouull[2]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_36_1(abcdefg_f11_eg3_ab_fghijklm[36]),
+ .abcd_efgh_ijklmno_f05_out_f_2(abcdefg_f05_a_zxdf[2]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_ch_2(abcdefg_f08_eg0_ab_cdefghijklm[36]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_cj_3(abcdefg_f10_eg2_ab_a_fghi[34]),
+ .abcd_efgh_ijklmno_f04_oilouull_o_3_1(abcdefg_f04_oilouull[3]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_cd_3(abcdefg_f08_eg0_ab_a_fghi[40]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_56_1(abcdefg_f08_eg0_ab_fghijklm[56]),
+
+
+ );*/
+TEST TEST (/*AUTOINST*/);
+
+endmodule
+
+module TEST (/*AUTOARG*/);
+ parameter NO = 6456;
+endmodule
diff --git a/tests/autoinst_param_2d.v b/tests/autoinst_param_2d.v
new file mode 100644
index 0000000..95ec595
--- /dev/null
+++ b/tests/autoinst_param_2d.v
@@ -0,0 +1,45 @@
+// bug981
+
+module a(
+ parameter AUM=80;
+ parameter BUM=70;
+ parameter VUM=1;
+ parameter V2=2;
+ input my_data_z;
+ input my_data_v[VUM];
+ input my_data_vv[VUM][V2];
+ input [AUM-1:0] my_data_av[VUM];
+ input [AUM-1:0][BUM-1:0] my_data_ab;
+ input [AUM-1:0][BUM-1:0] my_data_abv[VUM];
+
+ input [XUM-1:0][YUM-1:0] my_data_xyz[ZUM];
+
+ input PARAMS0__t params0 [1:0];
+ input PARAMS1__t params1 [1:0];
+ );
+endmodule
+
+module top (/*AUTOARG*/)
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ /*AUTOWIRE*/
+
+ /*
+ a AUTO_TEMPLATE
+ (
+ .\(.*\) (TEST@_\1[][]),
+ );
+ */
+ a #(/*AUTOINSTPARAM*/)
+ a_0 (/*AUTOINST*/);
+
+
+ a #(/*AUTOINSTPARAM*/)
+ a_1 (/*AUTOINST*/);
+
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-param-value:t
+// verilog-typedef-regexp: "_t$"
+// End:
diff --git a/tests/autoinst_param_cmt.v b/tests/autoinst_param_cmt.v
new file mode 100644
index 0000000..a31b464
--- /dev/null
+++ b/tests/autoinst_param_cmt.v
@@ -0,0 +1,24 @@
+module InstMod ( ins, outs );
+ output [INWIDTH-1:0] ins;
+endmodule
+
+module test (/*AUTOARG*/) ;
+ parameter foo=1;
+ /*
+ parameter foo=2;
+ */
+
+ //bug647
+
+ /* InstMod AUTO_TEMPLATE
+ (.ins (a@"vh-foo")); */
+
+ InstMod instName (/*AUTOINST*/
+ // Outputs
+ .ins (a1)); // Templated
+
+endmodule
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests/autoinst_param_type.v b/tests/autoinst_param_type.v
new file mode 100644
index 0000000..b5f494a
--- /dev/null
+++ b/tests/autoinst_param_type.v
@@ -0,0 +1,88 @@
+
+//bug1061
+
+//typedef logic [7:0] foo_t;
+module ptype
+ (
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input foo_t a, // To b0 of ptype_buf.v, ...
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output foo_t y0, // From b0 of ptype_buf.v
+ output logic [7:0] y1, // From b1 of ptype_buf.v
+ output TYPE_T y2 // From b2 of ptype_buf.v
+ // End of automatics
+ );
+
+ ptype_buf #(.TYPE_T(foo_t)) b0
+ (// Outputs
+ .y (y0),
+ /*AUTOINST*/
+ // Inputs
+ .a (a));
+
+ ptype_buf #(.TYPE_T(logic [7:0])) b1
+ (// Outputs
+ .y (y1),
+ /*AUTOINST*/
+ // Inputs
+ .a (a));
+
+ ptype_buf #(.WIDTH(8)) b2
+ (// Outputs
+ .y (y2),
+ /*AUTOINST*/
+ // Inputs
+ .a (a));
+
+endmodule
+
+module ptype_buf
+ #(parameter WIDTH = 1,
+ parameter type TYPE_T = logic [WIDTH-1:0])
+ (output TYPE_T y,
+ input TYPE_T a);
+ assign y = a;
+endmodule
+
+///--------------
+
+// Example in docs
+
+ module InstModule (o,i);
+ parameter WIDTH;
+ input [WIDTH-1:0] i;
+ parameter type OUT_t;
+ output OUT_t o;
+ endmodule
+
+ module ExampInst;
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input [9:0] i; // To instName of InstModule.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output upper_t o; // From instName of InstModule.v
+ // End of automatics
+
+ InstModule
+ #(.WIDTH(10),
+ ,.OUT_t(upper_t))
+ instName
+ (/*AUTOINST*/
+ // Outputs
+ .o (o),
+ // Inputs
+ .i (i[9:0]));
+ endmodule
+
+// Local Variables:
+// verilog-typedef-regexp: "_[tT]$"
+// verilog-auto-inst-param-value:t
+// verilog-auto-inst-param-value-type:t
+// End:
diff --git a/tests/autoinst_paramover.v b/tests/autoinst_paramover.v
new file mode 100644
index 0000000..0a880a3
--- /dev/null
+++ b/tests/autoinst_paramover.v
@@ -0,0 +1,22 @@
+module autoinst_paramover (/*AUTOARG*/
+ // Inouts
+ a, b
+ );
+
+ //======================================================================
+ // Inputs/Outputs
+ //======================================================================
+
+ parameter bitsa = 20;
+ parameter bitsb = 20;
+
+ inout [20:0] a; // SDRAM Channel 0 Row Address Strobe
+ inout [20:0] b; // SDRAM Channel 0 Row Address Strobe
+
+ autoinst_paramover_sub #(bitsa,bitsb ) mod
+ (/*AUTOINST*/
+ // Inouts
+ .a (a[bitsa:0]),
+ .b (b[bitsb:0]));
+
+endmodule
diff --git a/tests/autoinst_paramover_sub.v b/tests/autoinst_paramover_sub.v
new file mode 100644
index 0000000..87ab1a2
--- /dev/null
+++ b/tests/autoinst_paramover_sub.v
@@ -0,0 +1,16 @@
+module autoinst_paramover_sub (/*AUTOARG*/
+ // Inouts
+ a, b
+ );
+
+ //======================================================================
+ // Inputs/Outputs
+ //======================================================================
+
+ parameter bitsa;
+ parameter bitsb;
+
+ inout [bitsa:0] a; // SDRAM Channel 0 Row Address Strobe
+ inout [bitsb:0] b; // SDRAM Channel 0 Row Address Strobe
+
+endmodule
diff --git a/tests/autoinst_paramvalue.v b/tests/autoinst_paramvalue.v
new file mode 100644
index 0000000..0c1fcfd
--- /dev/null
+++ b/tests/autoinst_paramvalue.v
@@ -0,0 +1,68 @@
+module testmuxpv();
+ # (parameter WIDTH = 32)
+ (
+ input wire [2:0] /* synopsys enum cur_info */ sel,
+ input wire [WIDTH-1:0] a,
+ output reg [WIDTH-1:0] out
+ );
+endmodule
+
+module top_test();
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [WIDTH-1:0] out; // From testmuxpv_boo of testmuxpv.v, ..., Couldn't Merge
+ // End of automatics
+
+ //======================================================================
+
+ /* testmuxpv AUTO_TEMPLATE (
+ ) */
+
+ testmuxpv #(.IGNORE((1)),
+ .WIDTH( 16 ),
+ .IGNORE2(2))
+ testmuxpv_boo
+ (/*AUTOINST*/
+ // Outputs
+ .out (out[15:0]),
+ // Inputs
+ .sel (sel[2:0]),
+ .a (a[15:0]));
+
+ //======================================================================
+
+ testmuxpv #(.IGNORE((1)),
+ .WIDTH(WIDTH), // Make sure we don't recurse!
+ .IGNORE2(2))
+ testmuxpv_boo
+ (/*AUTOINST*/
+ // Outputs
+ .out (out[WIDTH-1:0]),
+ // Inputs
+ .sel (sel[2:0]),
+ .a (a[WIDTH-1:0]));
+
+ //======================================================================
+ // bug331: vl-width should correct when param values propagating
+
+ /* testmuxpv AUTO_TEMPLATE (
+ .a ({@"vl-width"{1'b0}}),
+ ) */
+
+ testmuxpv #(.IGNORE((1)),
+ .WIDTH(16),
+ .IGNORE2(2))
+ testmuxpv_boo
+ (/*AUTOINST*/
+ // Outputs
+ .out (out[15:0]),
+ // Inputs
+ .sel (sel[2:0]),
+ .a ({16{1'b0}})); // Templated
+
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-param-value:t
+// End:
diff --git a/tests/autoinst_podolsky.v b/tests/autoinst_podolsky.v
new file mode 100644
index 0000000..1e091b7
--- /dev/null
+++ b/tests/autoinst_podolsky.v
@@ -0,0 +1,21 @@
+module io1_sub(
+ /*AUTOARG*/);
+
+ /* autoinst_lopaz_srpad AUTO_TEMPLATE (
+ .pin_in(),
+ // Inputs
+ .pin_out (),
+ ); */
+
+ autoinst_lopaz_srpad i_ctrl
+ (/*AUTOINST*/
+ // Outputs
+ .pin_in (), // Templated
+ // Inouts
+ .pin (pin[w-1:0]),
+ // Inputs
+ .clk (clk),
+ .pin_out (), // Templated
+ .pin_outen (pin_outen));
+
+endmodule
diff --git a/tests/autoinst_precomment.v b/tests/autoinst_precomment.v
new file mode 100644
index 0000000..f37d8c1
--- /dev/null
+++ b/tests/autoinst_precomment.v
@@ -0,0 +1,40 @@
+module autoinst_precomment (
+ why,
+ /*AUTOARG*/
+ // Inputs
+ nnnot
+ );
+ input why;
+ input nnnot;
+
+ autoinst_wildcard_sub sub0
+ (
+ .sd_ras_ (foobar_ras_),
+ //.sd0_dqm7_l (dontdome),
+ /*AUTOINST*/
+ // Inouts
+ .sd0_dqm7_l (sd0_dqm7_l),
+ .sd0_dqm6_l (sd0_dqm6_l),
+ .sd0_dqm5_l (sd0_dqm5_l),
+ .sd0_dqm4_l (sd0_dqm4_l),
+ .sd0_dqm3_l (sd0_dqm3_l),
+ .sd0_dqm2_l (sd0_dqm2_l),
+ .sd0_dqm1_l (sd0_dqm1_l),
+ .sd0_dqm0_l (sd0_dqm0_l),
+ .sd0_ba1 (sd0_ba1),
+ .sd0_ba0 (sd0_ba0),
+ .sd0_adrs11 (sd0_adrs11),
+ .sd0_adrs10 (sd0_adrs10),
+ .sd0_adrs9 (sd0_adrs9),
+ .sd0_adrs8 (sd0_adrs8),
+ .sd0_adrs7 (sd0_adrs7),
+ .sd0_adrs6 (sd0_adrs6),
+ .sd0_adrs5 (sd0_adrs5),
+ .sd0_adrs4 (sd0_adrs4),
+ .sd0_adrs3 (sd0_adrs3),
+ .sd0_adrs2 (sd0_adrs2),
+ .sd0_adrs1 (sd0_adrs1),
+ .sd0_adrs0 (sd0_adrs0),
+ .sd0_clk (sd0_clk));
+
+endmodule
diff --git a/tests/autoinst_rao.v b/tests/autoinst_rao.v
new file mode 100644
index 0000000..73830b8
--- /dev/null
+++ b/tests/autoinst_rao.v
@@ -0,0 +1,29 @@
+module temp2(/*AUTOARG*/);
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [5:0] out; // From adc_3 of adc.v
+ // End of automatics
+
+ adc adc_3 (
+ // Outputs
+ .out (out[5:0]),
+ // Inputs
+ .Vi (Vi),
+ // Inputs
+ .evalClk (evalClk),
+ /*AUTOINST*/);
+
+endmodule // temp
+
+
+module adc(/*AUTOARG*/
+ // Outputs
+ out,
+ // Inputs
+ Vi, evalClk
+ );
+ output [5:0] out;
+ input Vi;
+ input evalClk;
+endmodule
diff --git a/tests/autoinst_regexp_match.v b/tests/autoinst_regexp_match.v
new file mode 100644
index 0000000..82b0149
--- /dev/null
+++ b/tests/autoinst_regexp_match.v
@@ -0,0 +1,27 @@
+module autoinst_wildcard;
+
+ /*AUTOINOUT*/
+
+ /* autoinst_wildcard_sub AUTO_TEMPLATE (
+ .sd\([0-9]\)_\(.*\)\([0-9]+\)\(.*\) (@"(uc \\"sd_\2\4[\1][\3]\\")"),
+ ); */
+
+ /*AUTOOUTPUT*/
+
+ autoinst_wildcard_sub sub0
+ (/*AUTOINST*/);
+
+ /* autoinst_wildcard_sub AUTO_TEMPLATE (
+ .sd\([0-9]\)_\(.*\)\([0-9]+\)\(.*\) (sd_\2\4[\1][\3]),
+ ); */
+
+ /*AUTOOUTPUT*/
+
+ autoinst_wildcard_sub sub1
+ (/*AUTOINST*/);
+
+endmodule
+
+// Local Variables:
+// eval:(defun uc (x) (upcase x))
+// End:
diff --git a/tests/autoinst_rogoff.v b/tests/autoinst_rogoff.v
new file mode 100644
index 0000000..4b1def9
--- /dev/null
+++ b/tests/autoinst_rogoff.v
@@ -0,0 +1,52 @@
+module testmux();
+ # (parameter WIDTH = 32)
+ (
+ input wire [2:0] /* synopsys enum cur_info */ sel,
+ input wire [WIDTH-1:0] a,
+ output reg [WIDTH-1:0] out
+ );
+endmodule
+
+module top_test();
+
+ /*AUTOWIRE*/
+
+ /*AUTO_LISP(setq verilog-auto-inst-param-value nil)*/
+
+ /* testmux AUTO_TEMPLATE "testmux_\(.*\)" (
+ .a (@_a_symbolic[]),
+ .out (@_out_symbolic[]),
+ );
+ */
+
+ testmux #(.WIDTH( 16 )) testmux_boo
+ (/*AUTOINST*/);
+
+ testmux testmux_defaultwidth
+ (/*AUTOINST*/);
+
+ //======================================================================
+
+ /*AUTO_LISP(setq verilog-auto-inst-param-value t)*/
+
+ /* testmux AUTO_TEMPLATE "testmux_\(.*\)" (
+ .a (@_a_value[]),
+ .out (@_out_value[]),
+ );
+ */
+
+ testmux #(.IGNORE((1)),
+ .WIDTH( 16 ),
+ .IGNORE2(2))
+ testmux_boo
+ (/*AUTOINST*/);
+
+ //======================================================================
+
+ testmux #(.IGNORE((1)),
+ .WIDTH(WIDTH), // Make sure we don't recurse!
+ .IGNORE2(2))
+ testmux_boo
+ (/*AUTOINST*/);
+
+endmodule
diff --git a/tests/autoinst_rons.v b/tests/autoinst_rons.v
new file mode 100644
index 0000000..ca7f57f
--- /dev/null
+++ b/tests/autoinst_rons.v
@@ -0,0 +1,16 @@
+module autoinst_rons;
+ dwrr dwrr_inst (/*AUTOINST*/);
+endmodule
+
+// module declaration
+module dwrr (
+ //Inputs
+ input [47:0] data_avail,
+ input [47:0] cell_eof,
+
+ //Outputs
+ output reg [6:0] dwell_count_out,
+ output reg [47:0] eligible_flag,
+ output [5:0] dwrr_state );
+
+endmodule
diff --git a/tests/autoinst_signed.v b/tests/autoinst_signed.v
new file mode 100644
index 0000000..a5e504f
--- /dev/null
+++ b/tests/autoinst_signed.v
@@ -0,0 +1,43 @@
+module autoinst_signed
+ (/*AUTOARG*/
+ // Outputs
+ another_output2, another_output, an_outputpre, an_output2
+ );
+
+ /*AUTOOUTPUTEVERY*/
+ // Beginning of automatic outputs (every signal)
+ output [1:0] an_output2; // From u_fubar2 of autoinst_signed_fubar2.v
+ output signed [1:0] an_outputpre; // From u_fubar of autoinst_signed_fubar.v
+ output signed [1:0] another_output; // From u_fubar of autoinst_signed_fubar.v
+ output [1:0] another_output2; // From u_fubar2 of autoinst_signed_fubar2.v
+ // End of automatics
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [1:0] an_output2; // From u_fubar2 of autoinst_signed_fubar2.v
+ wire signed [1:0] an_outputpre; // From u_fubar of autoinst_signed_fubar.v
+ wire signed [1:0] another_output; // From u_fubar of autoinst_signed_fubar.v
+ wire [1:0] another_output2; // From u_fubar2 of autoinst_signed_fubar2.v
+ // End of automatics
+
+ autoinst_signed_fubar u_fubar
+ (
+ // Outputs
+ .an_output (an_outputpre[1:0]),
+ .plover (plump),
+ /*AUTOINST*/
+ // Outputs
+ .another_output (another_output[1:0]),
+ // Inputs
+ .an_input (an_input[1:0]));
+
+ autoinst_signed_fubar2 u_fubar2
+ (
+ /*AUTOINST*/
+ // Outputs
+ .an_output2 (an_output2[1:0]),
+ .another_output2 (another_output2[1:0]),
+ // Inputs
+ .an_input2 (an_input2[1:0]));
+
+endmodule
diff --git a/tests/autoinst_signed_fubar.v b/tests/autoinst_signed_fubar.v
new file mode 100644
index 0000000..d28f7e3
--- /dev/null
+++ b/tests/autoinst_signed_fubar.v
@@ -0,0 +1,15 @@
+
+module autoinst_signed_fubar
+ (
+ input signed [1:0] an_input,
+ output signed [1:0] an_output
+ output signed [1:0] another_output
+ );
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg signed [1:0] an_output;
+ reg signed [1:0] another_output;
+ // End of automatics
+
+endmodule
diff --git a/tests/autoinst_signed_fubar2.v b/tests/autoinst_signed_fubar2.v
new file mode 100644
index 0000000..5b359b9
--- /dev/null
+++ b/tests/autoinst_signed_fubar2.v
@@ -0,0 +1,15 @@
+
+module autoinst_signed_fubar2
+ (
+ input [1:0] an_input2,
+ output [1:0] an_output2
+ output [1:0] another_output2
+ );
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg [1:0] an_output2;
+ reg [1:0] another_output2;
+ // End of automatics
+
+endmodule
diff --git a/tests/autoinst_star.v b/tests/autoinst_star.v
new file mode 100644
index 0000000..2f674a8
--- /dev/null
+++ b/tests/autoinst_star.v
@@ -0,0 +1,32 @@
+module io1_sub (/*AUTOARG*/);
+
+ /*AUTOWIRE*/
+
+ autoinst_lopaz_srpad MD31_pad
+ (.*,
+ .foo (touch_this_not_my_pretty));
+
+ /* autoinst_lopaz_srpad AUTO_TEMPLATE (
+ ); */
+
+ autoinst_lopaz_srpad MD31_pad
+ (.*);
+
+ /* autoinst_lopaz_srpad AUTO_TEMPLATE (
+ .pin (templated));
+ */
+
+ autoinst_lopaz_srpad MD31_pad
+ (.*);
+
+ // And .name with auto inst
+ autoinst_lopaz_srpad MD31_pad22
+ (.pin,
+ .clk,
+ /*AUTOINST*/);
+
+ always @(posedge clk) begin
+ $display ("This .* shouldn't expand.\n");
+ end
+
+endmodule
diff --git a/tests/autoinst_sv_kulkarni.v b/tests/autoinst_sv_kulkarni.v
new file mode 100644
index 0000000..f00b727
--- /dev/null
+++ b/tests/autoinst_sv_kulkarni.v
@@ -0,0 +1,69 @@
+`timescale 1ns/100ps
+
+// -----------------------------------------------------------------------------
+// One-level up Hierarchical module
+// -----------------------------------------------------------------------------
+module a_h
+ // Verilog 2001 style
+ #(parameter M=5, N=3)
+ (
+ // Outputs
+ output [N-1:0] [M-1:0]a_o1 // From Ia of autoinst_sv_kulkarni_base.v
+ // End of automatics
+ // AUTOINPUT*/
+ );
+
+ /*AUTOWIRE*/
+
+ autoinst_sv_kulkarni_base
+ #(/*AUTOINSTPARAM*/)
+ Ia
+ (/*AUTOINST*/); // <---- BUG?
+
+endmodule
+
+// -----------------------------------------------------------------------------
+// Top-level module or Testbench
+// -----------------------------------------------------------------------------
+module top;
+ parameter M=4;
+ parameter N=2;
+
+ wire [N-1:0] a_o1;
+ logic [N-1:0][M-1:0] a_i1;
+
+ logic temp;
+
+ /*AUTOWIRE*/
+
+ // Workaround to fix multi-dimensional port problem
+ // a) Set "verilog-auto-inst-vector = nil"
+ // b) ----> a_h AUTO_TEMPLATE ( .\(.*\) (\1), ); */
+
+ a_h #(/*AUTOINSTPARAM*/)
+ Ua_h
+ (/*AUTOINST*/); // <---- BUG?
+
+ // Stimulus
+ initial begin
+ a_i1 = { 4'h0, 4'h2 };
+ #5;
+ $display("Loop Init: a_i1 = { %h, %h } a_o1 = %h\n",
+ a_i1[1], a_i1[0], a_o1);
+ #5;
+ for (int i=0; i<1; i++) begin
+ for (int j=0; j<N; j++) begin
+ temp = 1'b0;
+ for (int k=0; k<M; k++) begin
+ a_i1[j][k] = temp;
+ temp = ~temp;
+ end
+ end
+ #5;
+ $display("Loop %0d: a_i1 = { %h, %h } a_o1 = %h\n",
+ i, a_i1[1], a_i1[0], a_o1);
+ #5;
+ end
+ end
+
+endmodule
diff --git a/tests/autoinst_sv_kulkarni_base.v b/tests/autoinst_sv_kulkarni_base.v
new file mode 100644
index 0000000..a47bff9
--- /dev/null
+++ b/tests/autoinst_sv_kulkarni_base.v
@@ -0,0 +1,21 @@
+`timescale 1ns/100ps
+
+// -----------------------------------------------------------------------------
+// Leaf module using multi-dimensional array ports
+// -----------------------------------------------------------------------------
+module autoinst_sv_kulkarni_base
+ // Verilog 2001 style
+ #(parameter M=5, N=3)
+ (
+ output logic [N-1:0][M-1:0] a_o1,
+ input [N-1:0][M-1:0] a_i1
+ );
+
+ // -----------------------------------------------------------------------------
+ // Main Code
+ always_comb begin
+ for (int i=0; i<N; i++)
+ a_o1[i] = ^(a_i1[i]);
+ end
+
+endmodule
diff --git a/tests/autoinst_sv_kulkarni_wire.v b/tests/autoinst_sv_kulkarni_wire.v
new file mode 100644
index 0000000..8c1fed4
--- /dev/null
+++ b/tests/autoinst_sv_kulkarni_wire.v
@@ -0,0 +1,14 @@
+`timescale 1ns/100ps
+
+module a_h
+ #(parameter M=5, N=3)
+ ();
+
+ /*AUTOWIRE*/
+
+ autoinst_sv_kulkarni_base
+ #(/*AUTOINSTPARAM*/)
+ Ia
+ (/*AUTOINST*/); // <---- BUG?
+
+endmodule
diff --git a/tests/autoinst_sv_shaw.v b/tests/autoinst_sv_shaw.v
new file mode 100644
index 0000000..9fce8bd
--- /dev/null
+++ b/tests/autoinst_sv_shaw.v
@@ -0,0 +1,16 @@
+module autoinst_sv_shaw
+ (
+ /*AUTOINOUTMODULE("Example_mod")*/
+ );
+
+ Example_mod Ex1 (/*AUTOINST*/);
+
+endmodule
+
+module Example_mod
+ (
+ input logic clk,
+ input logic reset_b,
+ );
+endmodule
+
diff --git a/tests/autoinst_template_lint.v b/tests/autoinst_template_lint.v
new file mode 100644
index 0000000..38062f4
--- /dev/null
+++ b/tests/autoinst_template_lint.v
@@ -0,0 +1,55 @@
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Wilson Snyder.
+
+// Reported by Julian Gorfajn <jig1@cornell.edu>
+
+module autoinst_multitemplate ();
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input Boo2; // To suba2 of SubB.v
+ input Boo3; // To suba3 of SubB.v
+ input a; // To suba2 of SubB.v
+ input b; // To suba3 of SubB.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+
+ /*AUTOWIRE*/
+
+ wire [3:0] f4_dotnamed;
+
+ /*
+ SubB AUTO_TEMPLATE (
+ .b (Boo@),
+ );*/
+
+ SubB suba2 (/*AUTOINST*/
+ // Inputs
+ .a (a),
+ .b (Boo2)); // Templated
+
+ /*
+ SubB AUTO_TEMPLATE (
+ .a (Boo@),
+ );*/
+
+ SubB suba3 (/*AUTOINST*/
+ // Inputs
+ .a (Boo3), // Templated
+ .b (b));
+
+// Test harness doesn't support expected errors
+// /*
+// SubUnused AUTO_TEMPLATE (
+// .subunused (Boo@),
+// );*/
+
+endmodule
+
+module SubB (input a,input b);
+endmodule
+
+// Local Variables:
+// verilog-auto-template-warn-unused: t
+// End:
diff --git a/tests/autoinst_tennant.v b/tests/autoinst_tennant.v
new file mode 100644
index 0000000..21fd704
--- /dev/null
+++ b/tests/autoinst_tennant.v
@@ -0,0 +1,103 @@
+typedef logic [3:0][1:0] sometype_t;
+
+module top
+ #(parameter X=4,
+ parameter Y=1)
+
+ (input clk,
+ input rstb,
+
+ /*AUTOINPUT("^x.*\|v.*")*/
+ /*AUTOOUTPUT("^c.*\|k.*")*/
+
+ /*AUTOOUTPUT("^y.*")*/
+
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output foobar, // From XX of xx.v
+ output [4:0] [2:0] foobar2 // From YY of yy.v
+ // End of automatics
+ );
+
+ xx (/*AUTOINSTPARAM*/
+ // Parameters
+ .X (X),
+ .Y (Y))
+ XX(/*AUTOINST*/
+ // Outputs
+ .st (st[1:0]),
+ .foobar (foobar),
+ // Inputs
+ .clk (clk),
+ .rstb (rstb),
+ .xc (xc/*[X-1:0][1:0]*/),
+ .xa (xa[X-1:0]),
+ .xb (xb[X-1:0]),
+ .cb (cb[X-1:0]),
+ .yb (yb[X*Y-1:0]));
+
+ yy (/*AUTOINSTPARAM*/
+ // Parameters
+ .X (X),
+ .Y (Y))
+ YY(/*AUTOINST*/
+ // Outputs
+ .xc (xc/*[X-1:0][1:0]*/),
+ .xa (xa[X-1:0]),
+ .yb (yb[X*Y-1:0]),
+ .foobar2 (foobar2/*[4:0][2:0]*/),
+ // Inputs
+ .clk (clk),
+ .rstb (rstb),
+ .xb (xb[X-1:0]),
+ .cb (cb[X-1:0]),
+ .st (st[1:0]));
+
+endmodule // top
+
+module xx
+ #(parameter X=4,
+ parameter Y=1)
+ (input clk,
+ input rstb,
+
+ input [X-1:0][1:0] xc,
+ input [X-1:0] xa,
+ input [X-1:0] xb,
+
+ input [X-1:0] cb,
+ output sometype_t [1:0] st,
+
+ input [X*Y-1:0] yb,
+
+ output foobar
+ );
+
+endmodule // xx
+
+module yy
+ #(parameter X=4,
+ parameter Y=1)
+ (input clk,
+ input rstb,
+
+ output [X-1:0][1:0] xc,
+ output [X-1:0] xa,
+ input [X-1:0] xb,
+
+ input [X-1:0] cb,
+ input sometype_t [1:0] st,
+
+ output [X*Y-1:0] yb,
+
+ output [4:0][2:0] foobar2
+ );
+
+endmodule // xx
+
+// Local Variables:
+// verilog-typedef-regexp:"_t$"
+// verilog-library-directories:("." )
+// verilog-library-extensions:(".v" ".sv" ".h" ".vr" ".vm")
+// End:
diff --git a/tests/autoinst_unsigned_bug302.v b/tests/autoinst_unsigned_bug302.v
new file mode 100644
index 0000000..a61d6f6
--- /dev/null
+++ b/tests/autoinst_unsigned_bug302.v
@@ -0,0 +1,23 @@
+module autoinst_unsigned_bug302;
+
+ Sub #(/*AUTOINSTPARAM*/) u_Abc
+ (/*AUTOINST*/);
+
+endmodule
+
+module Sub
+ #(
+ parameter No1 = 6,
+ parameter int unsigned No2 // Parameter no. 2
+ = pa_Abc::No2,
+ parameter bit No3 [No1:0][No2-1:0] // Parameter no. 3
+ = pa_Abc::No3
+ )
+
+ (
+ input logic ck,
+ input logic [No1-1:0][31:0] abc
+ input logic [No1-1:0][31:0] abc
+ );
+
+endmodule
diff --git a/tests/autoinst_vertrees.v b/tests/autoinst_vertrees.v
new file mode 100644
index 0000000..bbf81fd
--- /dev/null
+++ b/tests/autoinst_vertrees.v
@@ -0,0 +1,23 @@
+module autoinst_vertrees
+ (/*AUTOARG*/);
+
+ /*AUTOINPUT*/
+
+ /*AUTOOUTPUT*/
+
+ /*AUTOWIRE*/
+
+ /*
+ autoinst_vertrees_slv AUTO_TEMPLATE "u_slv_\([a-z]\)"
+ (.i2c_\(.*\) (i2c_@_\1),
+ .slv_\(.*\) (slv_@_\1),
+ .rpt_\(.*\) (rpt_@_\1),
+ )
+ */
+ autoinst_vertrees_slv u_slv_a
+ (/*AUTOINST*/);
+
+ autoinst_vertrees_slv u_slv_b
+ (/*AUTOINST*/);
+
+endmodule // ddc
diff --git a/tests/autoinst_vertrees_slv.v b/tests/autoinst_vertrees_slv.v
new file mode 100644
index 0000000..315f5df
--- /dev/null
+++ b/tests/autoinst_vertrees_slv.v
@@ -0,0 +1,37 @@
+
+module autoinst_vertrees_slv
+ (/*AUTOARG*/
+ // Outputs
+ i2c_mst_data, i2c_read, i2c_slv_scl_out, i2c_slv_sda_out, i2c_spc_scl_state, i2c_start,
+ i2c_strobe, slv_bit_st, slv_put, i2c_spc_scl_fall, i2c_spc_sda_state, i2c_spc_start,
+ i2c_spc_stop,
+ // Inputs
+ ck_ref, i2c_slv_data, i2c_slv_scl_in, i2c_slv_sda_in, r_i2c_spc_scl_low, rpt_hold, rpt_sda,
+ rst_ref, test_mode
+ );
+
+ input ck_ref; // To u_spc of i2c_slv_pin_ctrl.v, ...
+ input [7:0] i2c_slv_data; // To u_misc of ddc_slv_misc.v
+ input i2c_slv_scl_in; // To u_spc of i2c_slv_pin_ctrl.v
+ input i2c_slv_sda_in; // To u_spc of i2c_slv_pin_ctrl.v
+ input [4:0] r_i2c_spc_scl_low; // To u_spc of i2c_slv_pin_ctrl.v
+ input rpt_hold; // To u_misc of ddc_slv_misc.v
+ input rpt_sda; // To u_misc of ddc_slv_misc.v
+ input rst_ref; // To u_spc of i2c_slv_pin_ctrl.v, ...
+ input test_mode; // To u_spc of i2c_slv_pin_ctrl.v
+
+ output [7:0] i2c_mst_data; // From u_misc of ddc_slv_misc.v
+ output i2c_read; // From u_misc of ddc_slv_misc.v
+ output i2c_slv_scl_out; // From u_spc of i2c_slv_pin_ctrl.v
+ output i2c_slv_sda_out; // From u_spc of i2c_slv_pin_ctrl.v
+ output i2c_spc_scl_state; // From u_spc of i2c_slv_pin_ctrl.v
+ output i2c_start; // From u_misc of ddc_slv_misc.v
+ output i2c_strobe; // From u_misc of ddc_slv_misc.v
+ output slv_bit_st; // From u_misc of ddc_slv_misc.v
+ output slv_put; // From u_misc of ddc_slv_misc.v
+ output i2c_spc_scl_fall; // From u_spc of i2c_slv_pin_ctrl.v
+ output i2c_spc_sda_state; // From u_spc of i2c_slv_pin_ctrl.v
+ output i2c_spc_start; // From u_spc of i2c_slv_pin_ctrl.v
+ output i2c_spc_stop; // From u_spc of i2c_slv_pin_ctrl.v
+
+endmodule // ddc_slv
diff --git a/tests/autoinst_vkadamby.v b/tests/autoinst_vkadamby.v
new file mode 100644
index 0000000..4620da0
--- /dev/null
+++ b/tests/autoinst_vkadamby.v
@@ -0,0 +1,18 @@
+module autoinst_vkadamby ( /*AUTOARG*/);
+
+ child1 #(.lengthM2(100)) I34 (/*AUTOINST*/
+ // Inputs
+ .x (x));
+
+endmodule
+
+module child1 (/*AUTOARG*/
+ // Inputs
+ x
+ );
+
+ input x;
+ parameter lengthM2;
+
+endmodule
+
diff --git a/tests/autoinst_width.v b/tests/autoinst_width.v
new file mode 100644
index 0000000..65a1a6f
--- /dev/null
+++ b/tests/autoinst_width.v
@@ -0,0 +1,32 @@
+module ex;
+
+ /* subwidth AUTO_TEMPLATE (
+ .bus1a(@"vl-width"'b0),
+ .bus1b(@"vl-width"'b0),
+ .bus4a(@"vl-width"'b0),
+ .bus4b(@"vl-width"'b0),
+ .busdef(@"vl-width"'b0),
+ );*/
+
+ subwidth u_a2(/*AUTOINST*/
+ // Outputs
+ .bus4a (4'b0), // Templated
+ .bus4b (4'b0), // Templated
+ .bus1a (1'b0), // Templated
+ .bus1b (1'b0), // Templated
+ .busdef ((1+(`defa)-(`defb))'b0)); // Templated
+
+endmodule
+
+module subwidth (/*AUTOARG*/
+ // Outputs
+ bus4a, bus4b, bus1a, bus1b, busdef
+ );
+
+ output [0:3] bus4a;
+ output [7:4] bus4b;
+ output bus1a;
+ output [0:0] bus1b;
+ output [`defa:`defb] busdef;
+
+endmodule
diff --git a/tests/autoinst_wildcard.v b/tests/autoinst_wildcard.v
new file mode 100644
index 0000000..6325375
--- /dev/null
+++ b/tests/autoinst_wildcard.v
@@ -0,0 +1,53 @@
+module autoinst_wildcard;
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ // End of automatics
+
+ // Newline between AUTO_TEMPLATE and ( gave a templated line number bug
+ /* autoinst_wildcard_sub AUTO_TEMPLATE
+ (
+ .sd0_clk (sd_clk),
+ .sd0_dqm\(.*\)_l (c@_sd_dqm_[\1]),
+ .sd0_ba\([0-9]+\) (c@_sd_ba[\1]),
+ .sd0_adrs@ (c@_sd_adrs[\1]),
+ .ics@ (c@_ics[\1]),
+ ); */
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ // End of automatics
+
+ autoinst_wildcard_sub sub0
+ (/*AUTOINST*/
+ // Inouts
+ .sd_ras_ (sd_ras_),
+ .sd0_dqm7_l (c0_sd_dqm_[7]), // Templated 9
+ .sd0_dqm6_l (c0_sd_dqm_[6]), // Templated 9
+ .sd0_dqm5_l (c0_sd_dqm_[5]), // Templated 9
+ .sd0_dqm4_l (c0_sd_dqm_[4]), // Templated 9
+ .sd0_dqm3_l (c0_sd_dqm_[3]), // Templated 9
+ .sd0_dqm2_l (c0_sd_dqm_[2]), // Templated 9
+ .sd0_dqm1_l (c0_sd_dqm_[1]), // Templated 9
+ .sd0_dqm0_l (c0_sd_dqm_[0]), // Templated 9
+ .sd0_ba1 (c0_sd_ba[1]), // Templated 10
+ .sd0_ba0 (c0_sd_ba[0]), // Templated 10
+ .sd0_adrs11 (c0_sd_adrs[11]), // Templated 11
+ .sd0_adrs10 (c0_sd_adrs[10]), // Templated 11
+ .sd0_adrs9 (c0_sd_adrs[9]), // Templated 11
+ .sd0_adrs8 (c0_sd_adrs[8]), // Templated 11
+ .sd0_adrs7 (c0_sd_adrs[7]), // Templated 11
+ .sd0_adrs6 (c0_sd_adrs[6]), // Templated 11
+ .sd0_adrs5 (c0_sd_adrs[5]), // Templated 11
+ .sd0_adrs4 (c0_sd_adrs[4]), // Templated 11
+ .sd0_adrs3 (c0_sd_adrs[3]), // Templated 11
+ .sd0_adrs2 (c0_sd_adrs[2]), // Templated 11
+ .sd0_adrs1 (c0_sd_adrs[1]), // Templated 11
+ .sd0_adrs0 (c0_sd_adrs[0]), // Templated 11
+ .sd0_clk (sd_clk)); // Templated 8
+
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-template-numbers: t
+// End:
diff --git a/tests/autoinst_wildcard_sub.v b/tests/autoinst_wildcard_sub.v
new file mode 100644
index 0000000..9951127
--- /dev/null
+++ b/tests/autoinst_wildcard_sub.v
@@ -0,0 +1,42 @@
+module autoinst_wildcard_sub (/*AUTOARG*/
+ // Inouts
+ sd_ras_, sd0_dqm7_l, sd0_dqm6_l, sd0_dqm5_l, sd0_dqm4_l, sd0_dqm3_l,
+ sd0_dqm2_l, sd0_dqm1_l, sd0_dqm0_l, sd0_ba1, sd0_ba0, sd0_adrs11,
+ sd0_adrs10, sd0_adrs9, sd0_adrs8, sd0_adrs7, sd0_adrs6, sd0_adrs5,
+ sd0_adrs4, sd0_adrs3, sd0_adrs2, sd0_adrs1, sd0_adrs0, sd0_clk
+ );
+
+ //======================================================================
+ // Inputs/Outputs
+ //======================================================================
+
+ inout sd_ras_; // SDRAM Channel 0 Row Address Strobe
+ inout sd0_dqm7_l; // SDRAM Channel 0 DQM Mask Bits
+ inout sd0_dqm6_l;
+ inout sd0_dqm5_l;
+ inout sd0_dqm4_l;
+ inout sd0_dqm3_l;
+ inout sd0_dqm2_l;
+ inout sd0_dqm1_l;
+ inout sd0_dqm0_l;
+ inout sd0_ba1;
+ inout sd0_ba0;
+ inout sd0_adrs11; // SDRAM Channel 0 Address
+ inout sd0_adrs10;
+ inout sd0_adrs9;
+ inout sd0_adrs8;
+ inout sd0_adrs7;
+ inout sd0_adrs6;
+ inout sd0_adrs5;
+ inout sd0_adrs4;
+ inout sd0_adrs3;
+ inout sd0_adrs2;
+ inout sd0_adrs1;
+ inout sd0_adrs0;
+ inout sd0_clk; // SDRAM Channel 0 Clocks
+
+endmodule
+
+// Local Variables:
+// fill-column: 79
+// End:
diff --git a/tests/autoinst_wildcell.v b/tests/autoinst_wildcell.v
new file mode 100644
index 0000000..d3d6d3d
--- /dev/null
+++ b/tests/autoinst_wildcell.v
@@ -0,0 +1,29 @@
+module autoinst_wildcard;
+
+ /* sub AUTO_TEMPLATE (
+ .a\(.\)\(.\) (@"(substring vl-cell-name 4 5)"_@"(substring vl-cell-name 6 7)"_a_\1_\2),
+ ); */
+
+ sub sub_0_0 (/*AUTOINST*/);
+ sub sub_0_1 (/*AUTOINST*/);
+ sub sub_1_0 (/*AUTOINST*/);
+ sub sub_1_1 (/*AUTOINST*/);
+
+ /* sub AUTO_TEMPLATE (
+ .a\(.\)\(.\) (b_\1_\2),
+ ); */
+
+ sub sub_0_0 (/*AUTOINST*/);
+ sub sub_0_1 (/*AUTOINST*/);
+ sub sub_1_0 (/*AUTOINST*/);
+ sub sub_1_1 (/*AUTOINST*/);
+
+endmodule
+
+module sub;
+ input a33, a34, a44, a43;
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-template-numbers: t
+// End:
diff --git a/tests/autoinstparam_belkind.v-dontrun b/tests/autoinstparam_belkind.v-dontrun
new file mode 100644
index 0000000..7c089e7
--- /dev/null
+++ b/tests/autoinstparam_belkind.v-dontrun
@@ -0,0 +1,19 @@
+module autoinstparam_belkind (/*AUTOARG*/) ;
+
+ parameter X = 8;
+ /*
+ autoinstparam_belkind_leaf AUTO_TEMPLATE (
+ .P (X),
+ .a (b[]),
+ );
+ */
+
+ autoinstparam_belkind_leaf (/*AUTOINSTPARAM*/)
+ leaf(/*AUTOINST*/);
+
+endmodule // tree
+
+// Local Variables:
+// eval:(verilog-read-defines)
+// eval:(verilog-read-defines "autoinstparam_belkind_leaf.v")
+// End:
diff --git a/tests/autoinstparam_belkind_leaf.v b/tests/autoinstparam_belkind_leaf.v
new file mode 100644
index 0000000..e674ea3
--- /dev/null
+++ b/tests/autoinstparam_belkind_leaf.v
@@ -0,0 +1,9 @@
+module autoinstparam_belkind_leaf (/*AUTOARG*/) ;
+
+ parameter P =3D 4;
+ input [P-1:0] a;
+
+endmodule // leaf
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests/autoinstparam_bug287.v b/tests/autoinstparam_bug287.v
new file mode 100644
index 0000000..3548086
--- /dev/null
+++ b/tests/autoinstparam_bug287.v
@@ -0,0 +1,15 @@
+module Ptest #(
+ parameter I_CONTROL = 8'h 00, R_CONTROL = 8'h00)
+ (
+ input scanTest,
+ input scanArst);
+endmodule
+
+module t;
+
+ Ptest
+ #(/*AUTOINSTPARAM*/)
+ u_Ptest
+ (/*AUTOINST*/);
+
+endmodule
diff --git a/tests/autoinstparam_first.v b/tests/autoinstparam_first.v
new file mode 100644
index 0000000..24f4362
--- /dev/null
+++ b/tests/autoinstparam_first.v
@@ -0,0 +1,43 @@
+module autoinstparam_first ();
+
+ parameter BITSCHANGED;
+ parameter BITSA;
+ parameter type BITSB_t;
+ typedef [2:0] my_bitsb_t;
+
+ /* autoinstparam_first_sub AUTO_TEMPLATE (
+ .BITSA (BITSCHANGED),
+ ); */
+
+ autoinstparam_first_sub
+ #(/*AUTOINSTPARAM*/)
+ sub
+ (/*AUTOINST*/);
+
+ autoinstparam_first_sub
+ #(
+ .BITSB_t (my_bitsb_t),
+ /*AUTOINSTPARAM*/)
+ sub1
+ (/*AUTOINST*/);
+
+ autoinstparam_first_sub
+ #(
+ .BITSA (1),
+ .BITSB_t (my_bitsb_t)
+ /*AUTOINSTPARAM*/)
+ sub2
+ (/*AUTOINST*/);
+
+ autoinstparam_first_sub
+ #(
+ /*AUTOINSTPARAM*/)
+ sub3
+ (/*AUTOINST*/);
+
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-param-value:nil
+// verilog-typedef-regexp: "_t$"
+// End:
diff --git a/tests/autoinstparam_first_sub.v b/tests/autoinstparam_first_sub.v
new file mode 100644
index 0000000..76be3cf
--- /dev/null
+++ b/tests/autoinstparam_first_sub.v
@@ -0,0 +1,21 @@
+module autoinstparam_first_sub (/*AUTOARG*/
+ // Inouts
+ a, b
+ );
+
+ //======================================================================
+ // Inputs/Outputs
+ //======================================================================
+
+ localparam IGNORED;
+ parameter BITSA;
+ parameter type BITSB_t = bit; // See bug340
+
+ inout [BITSA:0] a;
+ inout BITSB_t b;
+
+endmodule
+
+// Local Variables:
+// verilog-typedef-regexp: "_t$"
+// End:
diff --git a/tests/autoinstparam_iface_bruce.v b/tests/autoinstparam_iface_bruce.v
new file mode 100644
index 0000000..781f370
--- /dev/null
+++ b/tests/autoinstparam_iface_bruce.v
@@ -0,0 +1,17 @@
+module top;
+ /*AUTOWIRE*/
+ sub0 #(/*AUTOINSTPARAM*/)
+ s0 (/*AUTOINST*/);
+endmodule
+
+module sub0
+ #(
+ parameter string testit2 = 0,
+ int TESTIT = 0
+ ) (
+ // clk and resets
+ input logic side_clk,
+ input logic side_rst_b,
+ );
+
+endmodule
diff --git a/tests/autoinstparam_int.v b/tests/autoinstparam_int.v
new file mode 100644
index 0000000..d6b3c03
--- /dev/null
+++ b/tests/autoinstparam_int.v
@@ -0,0 +1,24 @@
+module xyz
+ #(parameter int FOO=1, BAR=2,
+ parameter logic [5:0] BLUP=3, ZOT=4,
+ parameter LDWRDS=5)
+ ( input x1, x2,
+ input int i1, i2,
+ input logic [5:0] i3, i4,
+ input i5,
+ output y);
+endmodule
+
+module pdq;
+ input x; output y;
+ parameter int FOO=1;
+endmodule
+
+module abc;
+ xyz XYZ
+ #(/*AUTOINSTPARAM*/)
+ (/*AUTOINST*/);
+ pdq PDQ
+ #(/*AUTOINSTPARAM*/)
+ (/*AUTOINST*/);
+endmodule
diff --git a/tests/autoinstparam_local.v b/tests/autoinstparam_local.v
new file mode 100644
index 0000000..7032432
--- /dev/null
+++ b/tests/autoinstparam_local.v
@@ -0,0 +1,24 @@
+//bug889
+
+module leaf #(
+ parameter DATA_WIDTH = 256,
+ localparam STRB_WIDTH_SHOULD_BE_HIDDEN = DATA_WIDTH/8 )
+ ();
+endmodule
+
+module test;
+ parameter integer DATA_WIDTH = 256;
+ parameter integer STRB_WIDTH = DATA_WIDTH/8;
+
+ /* leaf AUTO_TEMPLATE (
+ .DATA_WIDTH( DATA_WIDTH ),
+ .STRB_WIDTH_SHOULD_BE_HIDDEN ( STRB_WIDTH ),
+ .\(.*\) ( \1 ),
+ );*/
+
+ leaf
+ #( /*AUTOINSTPARAM*/)
+ u_leaf
+ ( /*AUTOINST*/);
+
+endmodule
diff --git a/tests/autolisp_include.v b/tests/autolisp_include.v
new file mode 100644
index 0000000..88dfef1
--- /dev/null
+++ b/tests/autolisp_include.v
@@ -0,0 +1,21 @@
+// See forum topic 176
+module autolisp_include (/*AUTOARG*/
+ // Outputs
+ foo,
+ // Inputs
+ bar
+ );
+
+ //`include "autolisp_include_inc.vh"
+ /*AUTOINSERTLISP(verilog-library-filenames (insert-file "autolisp_include_inc.vh"))*/
+ // Beginning of automatic insert lisp
+ input bar;
+ output foo;
+ // End of automatics
+
+ assign foo = bar;
+
+ // This doesn't need commentary
+ /*AUTOINSERTLISP(when nil)*/
+
+endmodule
diff --git a/tests/autolisp_include_inc.vh b/tests/autolisp_include_inc.vh
new file mode 100644
index 0000000..bc32ff1
--- /dev/null
+++ b/tests/autolisp_include_inc.vh
@@ -0,0 +1,2 @@
+ input bar;
+ output foo;
diff --git a/tests/autolisp_order_bug356.v b/tests/autolisp_order_bug356.v
new file mode 100644
index 0000000..1ab7eb2
--- /dev/null
+++ b/tests/autolisp_order_bug356.v
@@ -0,0 +1,47 @@
+module autolisp_top (/*AUTOARG*/);
+
+/* autolisp_inst AUTO_TEMPLATE (
+ .\(.*\)A (\1_@"(eval tense)"_A),
+ .\(.*\)B (\1_@"(eval tense)"_B),
+ );
+*/
+ /* AUTO_LISP(setq tense "is") */
+ autolisp_inst AUTOLISP_INST_I0
+ (/*AUTOINST*/
+ // Outputs
+ .result (result),
+ // Inputs
+ .portA (port_is_A), // Templated
+ .busA (bus_is_A), // Templated
+ .portB (port_is_B), // Templated
+ .busB (bus_is_B)); // Templated
+
+ /* AUTO_LISP(setq tense "was") */
+ autolisp_inst AUTOLISP_INST_I1
+ (/*AUTOINST*/
+ // Outputs
+ .result (result),
+ // Inputs
+ .portA (port_was_A), // Templated
+ .busA (bus_was_A), // Templated
+ .portB (port_was_B), // Templated
+ .busB (bus_was_B)); // Templated
+
+endmodule
+
+
+module autolisp_inst (/*AUTOARG*/
+ // Outputs
+ result,
+ // Inputs
+ portA, busA, portB, busB
+ );
+
+ input portA;
+ input [3:0] busA;
+ input portB;
+ input [1:0] busB;
+
+ output result;
+
+endmodule
diff --git a/tests/autolisp_truex.v b/tests/autolisp_truex.v
new file mode 100644
index 0000000..0a39184
--- /dev/null
+++ b/tests/autolisp_truex.v
@@ -0,0 +1,18 @@
+module ExampInsertLisp;
+
+ /*AUTOINSERTLISP(my-verilog-insert-hello "world")*/
+
+ // Try an empty insert
+ /*AUTOINSERTLISP(+ 1)*/
+
+ // Try a shell command
+ /*AUTOINSERTLISP(insert (shell-command-to-string "echo //hello"))*/
+
+endmodule
+/*
+ Local Variables:
+ eval:
+ (defun my-verilog-insert-hello (who)
+ (insert (concat "initial $write(\"hello " who "\");\n")))
+ End:
+*/
diff --git a/tests/autologic.sv b/tests/autologic.sv
new file mode 100644
index 0000000..6f67267
--- /dev/null
+++ b/tests/autologic.sv
@@ -0,0 +1,94 @@
+module top
+ #(parameter COLS = 4
+ )
+ ( input logic clk,
+ input logic rstb,
+ input logic [COLS-1:0] ival,
+ input logic [COLS-1:0][1:0] idata_some_extra_sig_length,
+ output logic reg_assigned
+ );
+
+ // Request: AUTOLOGIC instead of AUTOWIRE
+ // Request: AUTOLOGIC would substitute all 3 existing macros AUTOWIRE/AUTOREG/AUTOREGINPUT, one would use AUTOLOGIC instead of AUTOWIRE/AUTOREG or AUTOWIRE/AUTOREGINPUT.
+
+ // Could use AU-TOLOGIC
+ // Or AU-TOWIRE(logic)
+ // And-or (setq verilog-auto-sv t)
+ // And-or (setq verilog-auto-wire-type 'logic')
+
+ /*AUTOOUTPUTEVERY*/
+ // Beginning of automatic outputs (every signal)
+ output logic COLS;
+ output logic in1a; // To isub2 of sub2.v, ...
+ output logic in1b; // To isub1 of sub1.v
+ output logic in2b; // To isub2 of sub2.v
+ output logic out1a; // From isub1 of sub1.v
+ output logic [1:0] out1b; // From isub1 of sub1.v
+ output logic [1:0] out2b; // From isub2 of sub2.v
+ // End of automatics
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ logic reg_assigned;
+ // End of automatics
+
+ /*AUTOREGINPUT*/
+ // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+ logic in1a; // To isub2 of sub2.v, ...
+ logic in1b; // To isub1 of sub1.v
+ logic in2b; // To isub2 of sub2.v
+ // End of automatics
+
+ /*AUTOLOGIC*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic out1a; // From isub1 of sub1.v
+ logic [1:0] out1b; // From isub1 of sub1.v
+ logic [1:0] out2b; // From isub2 of sub2.v
+ // End of automatics
+
+ /* sub2 AUTO_TEMPLATE(
+ .idata_some_extra_sig_length ( s1_odata),
+ .ival ( s1_oval),
+ );*/
+ sub2 isub2 (/*AUTOINST*/
+ // Outputs
+ .out2b (out2b[1:0]),
+ // Inputs
+ .in1a (in1a),
+ .in2b (in2b),
+ .out1a (out1a));
+
+
+ sub1 isub1(/*AUTOINST*/
+ // Outputs
+ .out1a (out1a),
+ .out1b (out1b[1:0]),
+ // Inputs
+ .in1a (in1a),
+ .in1b (in1b));
+
+ always @(posedge clk) begin
+ reg_assigned <= 1;
+ end
+
+endmodule
+
+module sub1
+ ( input logic in1a,
+ input logic in1b,
+ output logic out1a,
+ output logic [1:0] out1b
+ );
+endmodule
+
+module sub2
+ ( input logic in1a,
+ input logic in2b,
+ input logic out1a,
+ output logic [1:0] out2b
+ );
+endmodule
+
+// Local Variables:
+// verilog-auto-wire-type: "logic"
+// End:
diff --git a/tests/automodport_ex.v b/tests/automodport_ex.v
new file mode 100644
index 0000000..b67d47f
--- /dev/null
+++ b/tests/automodport_ex.v
@@ -0,0 +1,27 @@
+interface ExampIf
+ ( input logic clk );
+ logic req_val;
+ logic [7:0] req_dat;
+ clocking mon_clkblk @(posedge clk);
+ input req_val;
+ input req_dat;
+ endclocking
+ modport mp(clocking mon_clkblk);
+endinterface
+
+module ExampMain
+( input clk,
+ /*AUTOINOUTMODPORT("ExampIf" "mp")*/
+ // Beginning of automatic in/out/inouts (from modport)
+ input req_val,
+ input [7:0] req_dat
+ // End of automatics
+);
+
+ /*AUTOASSIGNMODPORT("ExampIf" "mp" "inst")*/
+ // Beginning of automatic assignments from modport
+ assign inst.req_dat = req_dat;
+ assign inst.req_val = req_val;
+ // End of automatics
+
+endmodule
diff --git a/tests/automodport_full.v b/tests/automodport_full.v
new file mode 100755
index 0000000..ee609d6
--- /dev/null
+++ b/tests/automodport_full.v
@@ -0,0 +1,47 @@
+
+module auto_module
+( input my_clk,
+ input my_rst_n,
+
+
+ output manually_listed,
+
+ /*AUTOINOUTMODPORT("automodport_if" "pure_mp")*/
+ //ex: input in_pure;
+ //ex: output out_pure;
+
+ /*AUTOINOUTMODPORT("automodport_if" "req_mon_mp")*/
+ //ex: input req_credit, // To auto_i of auto_intf.sv
+ //ex: input [63:0] req_data, // To auto_i of auto_intf.sv
+ //ex: input req_val, // To auto_i of auto_intf.sv
+
+ /*AUTOINOUTMODPORT("automodport_if" "rsp_drv_mp")*/
+ //ex: output [1:0] rsp_cmd, // From auto_i of auto_intf.sv
+ //ex: input rsp_credit, // To auto_i of auto_intf.sv
+ //ex: output [63:0] rsp_data // From auto_i of auto_intf.sv
+);
+
+ auto_intf auto_i
+ (// Inputs
+ .clk (my_clk),
+ .rst_n (my_rst_n));
+
+ /*AUTOASSIGNMODPORT("automodport_if" "req_mon_mp" "auto_i" )*/
+ //ex: assign auto_i.req_credit = req_credit;
+ //ex: assign auto_i.req_data = req_data;
+ //ex: assign auto_i.req_val = req_val;
+
+ /*AUTOASSIGNMODPORT("automodport_if" "rsp_drv_mp" "auto_i" )*/
+ //ex: assign rsp_cmd = auto_i.rsp_cmd;
+ //ex: assign rsp_data = auto_i.rsp_data;
+ //ex: assign auto_i.rsp_credit = rsp_credit;
+
+ /*AUTOASSIGNMODPORT("automodport_if" "r.*" "auto_i" )*/
+
+
+ initial begin
+ `cn_set_intf(virtual auto_intf.req_mon_mp, "auto_pkg::auto_intf", "req_mon_vi", auto_i.req_mon_mp );
+ `cn_set_intf(virtual auto_intf.rsp_drv_mp, "auto_pkg::auto_intf", "rsp_drv_vi", auto_i.rsp_drv_mp );
+ end
+
+endmodule
diff --git a/tests/automodport_if.v b/tests/automodport_if.v
new file mode 100644
index 0000000..b0acca1
--- /dev/null
+++ b/tests/automodport_if.v
@@ -0,0 +1,67 @@
+interface automodport_if
+( input logic clk,
+ input logic rst_n
+);
+
+ //----------------------------------------------------------------------------------------
+ // Group: Signals
+ logic req_val;
+ logic [63:0] req_dat;
+ logic req_credit;
+
+ logic [1:0] rsp_cmd;
+ logic [63:0] rsp_data;
+ logic rsp_credit;
+
+ logic in_pure;
+ logic out_pure;
+ logic manually_listed;
+
+ //----------------------------------------------------------------------------------------
+ // Group: Clocking blocks
+ clocking req_mon_cb @(posedge clk);
+ input rst_n;
+ input req_val;
+ input req_dat;
+ input req_credit;
+ input manually_listed;
+ endclocking : req_mon_cb
+
+ clocking rsp_drv_cb @(posedge clk);
+ input rst_n;
+ output rsp_cmd;
+ output rsp_data;
+ input rsp_credit;
+ endclocking : rsp_drv_cb
+
+ //----------------------------------------------------------------------------------------
+ // Group: Modports
+ modport req_mon_mp(clocking req_mon_cb);
+ modport rsp_drv_mp(clocking rsp_drv_cb, import rsp_reset);
+ modport pure_mp(input in_pure, output out_pure);
+
+ //----------------------------------------------------------------------------------------
+ // Group: Methods
+ function void rsp_reset();
+ rsp_cmd = 2'b0;
+ rsp_data = 64'b0;
+ endfunction : rsp_reset
+
+ //----------------------------------------------------------------------------------------
+ // Group: Assertions
+ logic [1:0] cmd_m1;
+
+ always @(posedge clk) begin
+ cmd_m1 <= rsp_cmd;
+ if(rst_n) begin
+ if($isunknown(req_val)) `cn_err_intf(("Signal req_data_cycle is an X."));
+ if(req_val==1'b1 & $isunknown(req_data)) `cn_err_intf(("Signal req_data is an X."));
+ if($isunknown(req_credit)) `cn_err_intf(("Signal req_credit is an X."));
+
+ if($isunknown(rsp_cmd)) `cn_err_intf(("Signal rsp_cmd is an X."));
+ if(cmd_m1!=2'b0 & $isunknown(rsp_data)) `cn_err_intf(("Signal rsp_data is an X."));
+ if($isunknown(rsp_credit)) `cn_err_intf(("Signal rsp_credit is an X."));
+ end
+ end
+
+endinterface
diff --git a/tests/autooutput_comma.v b/tests/autooutput_comma.v
new file mode 100644
index 0000000..6c26078
--- /dev/null
+++ b/tests/autooutput_comma.v
@@ -0,0 +1,40 @@
+module top
+ (input [(`WIDTH):0] a, /* This comma gets deleted */
+ /*AUTOOUTPUT*/
+ /*AUTOINPUT*/
+ );
+
+ child child(/*AUTOINST*/);
+endmodule
+
+module nocomma
+ (/*AUTOOUTPUT*/
+ /*AUTOINPUT*/
+ );
+ child child(/*AUTOINST*/);
+endmodule
+
+module ifdefcomma
+ (
+`ifdef a
+ input foo,
+`endif
+ /*AUTOOUTPUT*/
+ /*AUTOINPUT*/
+ );
+ child child(/*AUTOINST*/);
+endmodule
+
+module ifdefnocomma
+ (
+`ifdef a
+ // It's up to the user to deal with the , themself
+ input foo,
+`endif
+ /*AUTOOUTPUT*/
+ );
+ child child(/*AUTOINST*/);
+endmodule
+
+module child(input b);
+endmodule
diff --git a/tests/autooutput_regexp.v b/tests/autooutput_regexp.v
new file mode 100644
index 0000000..2b82bd4
--- /dev/null
+++ b/tests/autooutput_regexp.v
@@ -0,0 +1,26 @@
+module ex_output_every (/*AUTOARG*/
+ // Outputs
+ sub1_out_pixel
+ )
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output pixel24_t sub1_out_pixel; // From i1 of v2k_typedef_yee_sub1.v
+ // End of automatics
+
+ v2k_typedef_yee_sub1 i1
+ (/*AUTOINST*/
+ // Outputs
+ .sub1_out_pixel (sub1_out_pixel),
+ .sub1_to_sub2 (sub1_to_sub2),
+ .sub1_to_sub2_and_top (sub1_to_sub2_and_top),
+ // Inputs
+ .sub1_in_pixel (sub1_in_pixel),
+ .cp (cp),
+ .reset (reset));
+
+endmodule
+
+// Local Variables:
+// verilog-auto-output-ignore-regexp:"^sub1_to_sub2"
+// End:
diff --git a/tests/autooutputevery_assign.v b/tests/autooutputevery_assign.v
new file mode 100644
index 0000000..f4d4a1e
--- /dev/null
+++ b/tests/autooutputevery_assign.v
@@ -0,0 +1,18 @@
+module ex_output_every (o,i,tempa,tempb)
+ output o;
+ input i;
+
+ /*AUTOOUTPUTEVERY*/
+ // Beginning of automatic outputs (every signal)
+ output tempa;
+ output tempb;
+ // End of automatics
+
+ wire tempa;
+ wire tempb;
+ wire o;
+
+ assign tempa = i;
+ assign tempb = tempa;
+ assign o = tempb;
+endmodule
diff --git a/tests/autooutputevery_example.v b/tests/autooutputevery_example.v
new file mode 100644
index 0000000..0abd702
--- /dev/null
+++ b/tests/autooutputevery_example.v
@@ -0,0 +1,15 @@
+module ex_output_every (o,i,tempa,tempb)
+ output o;
+ input i;
+
+ /*AUTOOUTPUTEVERY*/
+ // Beginning of automatic outputs (every signal)
+ output tempa;
+ output tempb;
+ // End of automatics
+
+ wire tempa = i;
+ wire tempb = tempa;
+ wire o = tempb;
+
+endmodule
diff --git a/tests/autooutputevery_regexp.v b/tests/autooutputevery_regexp.v
new file mode 100644
index 0000000..82ed893
--- /dev/null
+++ b/tests/autooutputevery_regexp.v
@@ -0,0 +1,9 @@
+module top
+ (
+ /*AUTOOUTPUTEVERY("^a")*/
+ );
+
+ wire aa;
+ wire ab;
+ wire cc;
+endmodule
diff --git a/tests/autooutputevery_wire.v b/tests/autooutputevery_wire.v
new file mode 100644
index 0000000..2730943
--- /dev/null
+++ b/tests/autooutputevery_wire.v
@@ -0,0 +1,62 @@
+module test (/*AUTOARG*/
+ // Outputs
+ stage3_bus,
+ // Inputs
+ stage1_bus
+ );
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output logic [7:0] stage3_bus; // From i_second of sub_module.v
+ // End of automatics
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input logic [7:0] stage1_bus; // To i_first of sub_module.v
+ // End of automatics
+ /*AUTOOUTPUTEVERY("^stage")*/
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic [7:0] stage2_bus; // From i_first of sub_module.v
+ // End of automatics
+ /*AUTOREG*/
+
+ /* sub_module AUTO_TEMPLATE
+ (
+ .i_\(.*\) (stage1_\1[]),
+ .o_\(.*\) (stage2_\1[]),
+ ); */
+
+ sub_module i_first (/*AUTOINST*/
+ // Outputs
+ .o_bus (stage2_bus[7:0]), // Templated
+ // Inputs
+ .i_bus (stage1_bus[7:0])); // Templated
+
+ /* sub_module AUTO_TEMPLATE
+ (
+ .i_\(.*\) (stage2_\1[]),
+ .o_\(.*\) (stage3_\1[]),
+ ); */
+
+ sub_module i_second (/*AUTOINST*/
+ // Outputs
+ .o_bus (stage3_bus[7:0]), // Templated
+ // Inputs
+ .i_bus (stage2_bus[7:0])); // Templated
+
+endmodule // test
+
+module sub_module (/*AUTOARG*/
+ // Outputs
+ o_bus,
+ // Inputs
+ i_bus
+ );
+
+ input logic [7:0] i_bus ;
+ output logic [7:0] o_bus ;
+
+ assign o_bus = i_bus;
+
+endmodule // sub_module
diff --git a/tests/autoreg_outreg.v b/tests/autoreg_outreg.v
new file mode 100644
index 0000000..9260bba
--- /dev/null
+++ b/tests/autoreg_outreg.v
@@ -0,0 +1,19 @@
+module foo
+ #(parameter
+ PARAM3_P=99)
+(
+ output sig3,// Here, I've hit "tab" twice and this line is correct
+ output reg [PARAM2_P-1:0] s4, // Comment here which should be at "comment-column"
+ output wire [PARAM2_P-1:0] sig5,// Comment here which should be at "comment-column"
+ input reset_L// module reset: global register
+ );
+
+ /*AUTOWIRE*/
+
+ // AUTOREG here is somewhat illegal, as outputs when a type is declared
+ // in a V2K decl list are automatically "reg'ed".
+ // However some simulators take it, so be sane and only do undeclared ones...
+
+ /*AUTOREG*/
+
+endmodule
diff --git a/tests/autoreg_smith_multiassign.v b/tests/autoreg_smith_multiassign.v
new file mode 100644
index 0000000..af3e015
--- /dev/null
+++ b/tests/autoreg_smith_multiassign.v
@@ -0,0 +1,19 @@
+module test(/*AUTOARG*/
+ // Outputs
+ a1, b1, c1, one
+ );
+
+ output [5:0] a1;
+ output [5:0] b1;
+ output [5:0] c1;
+
+ /*AUTOREG*/
+
+ //wire [5:0] a2,b2,c2;
+
+ assign {a1,b1,c1} = {a2,b2,c2};
+
+ output [1:0] one;
+ assign one = a2[0];
+
+endmodule
diff --git a/tests/autoreginput.v b/tests/autoreginput.v
new file mode 100644
index 0000000..054fbe6
--- /dev/null
+++ b/tests/autoreginput.v
@@ -0,0 +1,21 @@
+module autoreginput;
+
+ /*AUTOREGINPUT*/
+ // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+ reg lower_ina; // To inst of inst.v
+ reg lower_inb; // To inst of inst.v
+ // End of automatics
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire lower_out; // From inst of inst.v
+ // End of automatics
+
+ inst inst (/*AUTOINST*/
+ // Outputs
+ .lower_out (lower_out),
+ // Inputs
+ .lower_inb (lower_inb),
+ .lower_ina (lower_ina));
+
+endmodule
+
diff --git a/tests/autoreset_assert.v b/tests/autoreset_assert.v
new file mode 100644
index 0000000..7eaa898
--- /dev/null
+++ b/tests/autoreset_assert.v
@@ -0,0 +1,22 @@
+module foo;
+
+ reg [1:0] a;
+
+ assert property (@(posedge clk) e |-> f);
+
+ reg [1:0] b;
+
+ always @(posedge clk, negedge rst)
+ if (~rst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ a <= 2'h0;
+ b <= 2'h0;
+ // End of automatics
+ end
+ else begin
+ a<=b;
+ b<=a;
+ end
+
+endmodule
diff --git a/tests/autoreset_cond.v b/tests/autoreset_cond.v
new file mode 100644
index 0000000..1475b4e
--- /dev/null
+++ b/tests/autoreset_cond.v
@@ -0,0 +1,16 @@
+module x;
+ reg [1:0] idx_sel_2a;
+ always @(posedge usclk or negedge srst_0a_n) begin
+ if (~srst_0a_n) begin
+ /*AUTORESET*/
+ end
+ else begin
+ foo <= idx_adr_1a[1:0];
+ bar <= (idx_sel_2a == 2'h0 ? idx_rd_dat0_2a[12:0] :
+ idx_sel_2a == 2'h1 ? idx_rd_dat1_2a[12:0] :
+ idx_sel_2a == 2'h2 ? idx_rd_dat2_2a[12:0] :
+ /**/ idx_rd_dat3_2a[12:0]);
+ end
+ end
+
+endmodule
diff --git a/tests/autoreset_define_colon.v b/tests/autoreset_define_colon.v
new file mode 100644
index 0000000..ec0f385
--- /dev/null
+++ b/tests/autoreset_define_colon.v
@@ -0,0 +1,33 @@
+// bug594
+`define TABADR_EGR_MOD_MAP 7:0
+
+module test (
+/*AUTOARG*/
+ // Inputs
+ clk, rst, addr
+ );
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+
+ input clk;
+ input rst;
+ input[`TABADR_EGR_MOD_MAP] addr;
+
+
+reg [`TABADR_EGR_MOD_MAP] addrD1;
+reg [`TABADR_EGR_MOD_MAP] addrD2;
+
+always @(posedge clk or posedge rst) begin
+ if (rst_l) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ addrD1 <= `0/*NOWIDTH*/;
+ addrD2 <= `0/*NOWIDTH*/;
+ // End of automatics
+ end
+ else begin
+ addrD1 <= addr ;
+ addrD2 <= addrD1;
+ end
+end
+endmodule
diff --git a/tests/autoreset_dever.v b/tests/autoreset_dever.v
new file mode 100644
index 0000000..342937d
--- /dev/null
+++ b/tests/autoreset_dever.v
@@ -0,0 +1,41 @@
+module x;
+ always @(posedge piclk) begin
+ if (k_i_reset) begin
+ /*AUTORESET*/
+ end
+ else begin
+ idat_ICErrData_i3 <= idat_way0_i2[1*OPCWID-1:0*OPCWID];
+ end
+ end
+
+ // 2010-04-08
+ localparam MPND = 5;
+ always @(posedge usclk)
+ if (~sso_srst_n) begin
+ /*AUTORESET*/
+ end
+ else begin
+ sel_s3 <= adr_s2[MIDX];
+ rd_dat_s4 <= (sel_s3 == 1'h0 ? rd_dat0_s3[MPND:0]
+ : rd_dat1_s3[MPND:0]);
+ end
+
+ // 2010-04-15
+ integer i;
+ always @(posedge usclk)
+ if (~sso_srst_n) begin
+ for (int j=0; j<10; j++) blob[j] <= 0;
+ /*AUTORESET*/
+ end
+ else begin
+ for (i=0; i<10; i++) blob[i] <= blob[i+1];
+ for (i=0; i<10; i++) zz <= 1;
+ for (int isv=0; isv<10; isv++) zsv <= 1;
+ end
+
+ always @(/*AS*/) begin
+ for (i=0; i<10; i++) zz <= in;
+ for (int isv=0; isv<10; isv++) zsv <= in;
+ end
+
+endmodule
diff --git a/tests/autoreset_eq_bug381.v b/tests/autoreset_eq_bug381.v
new file mode 100644
index 0000000..a8ea973
--- /dev/null
+++ b/tests/autoreset_eq_bug381.v
@@ -0,0 +1,29 @@
+module t();
+
+ logic [31:0] sum;
+ logic [31:0] a;
+ logic [31:0] b;
+ reg [32:0] tmp;
+
+ always @(posedge clk or negedge rst) begin
+ if (!rst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ sum <= 32'h0;
+ // End of automatics
+ end
+ else begin
+ //reg [32:0] tmp;
+ tmp = a + b;
+ if (tmp[32])
+ sum <= 32'hffffffff;
+ else
+ sum <= tmp[31:0];
+ end
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-reset-blocking-in-non: nil
+// End:
diff --git a/tests/autoreset_eq_bug381_non.v b/tests/autoreset_eq_bug381_non.v
new file mode 100644
index 0000000..981eb93
--- /dev/null
+++ b/tests/autoreset_eq_bug381_non.v
@@ -0,0 +1,30 @@
+module t();
+
+ logic [31:0] sum;
+ logic [31:0] a;
+ logic [31:0] b;
+ reg [32:0] tmp;
+
+ always @(posedge clk or negedge rst) begin
+ if (!rst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ sum <= 32'h0;
+ tmp = 33'h0;
+ // End of automatics
+ end
+ else begin
+ //reg [32:0] tmp;
+ tmp = a + b;
+ if (tmp[32])
+ sum <= 32'hffffffff;
+ else
+ sum <= tmp[31:0];
+ end
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-reset-blocking-in-non: t
+// End:
diff --git a/tests/autoreset_equal_extra.v b/tests/autoreset_equal_extra.v
new file mode 100644
index 0000000..c646186
--- /dev/null
+++ b/tests/autoreset_equal_extra.v
@@ -0,0 +1,33 @@
+module autoreset_equal_extra ();
+
+ always_ff @(posedge csclk) begin
+ if( ~srst_n | !val_tx_to_csi ) begin
+ csi.cmd <= ncbo_cmd_t'('0);
+ // vvvvvv fifo.data.cb_req.req.cmd = '0; should not be below
+ /*AUTORESET*/
+ end
+ else begin
+ if (fifo.sot) begin
+ csi.src <= fifo.src;
+ csi.wr <= (fifo.data.cb_req.req.cmd == ncb_defs::NCBO_RSVD_LMTST
+ | fifo.data.cb_req.req.cmd == ncb_defs::NCBO_IOBST
+ );
+ csi.cmd <= fifo.data.cb_req.req.cmd;
+ end
+ end
+ end
+
+ always_ff @(posedge csclk) begin
+ if (~srst_n) begin
+ /*AUTORESET*/
+ end
+ else begin
+ sdp__x2p.err <= (x2p_fifo_rdat.err & x2p_fifo_pop_d3_sk)
+ ? x2p_p2x_roc_rtl_pkg::X2P_PKT_ERR_RCVERR
+ : x2p_p2x_roc_rtl_pkg::X2P_PKT_ERR_NONE;
+ sdp__x2p.bval <= x2p_fifo_rdat.bval & {4{x2p_fifo_pop_d3_sk}};
+ //FOO::bar <= 1; // Legal, though not typically used in RTL
+ end
+ end
+
+endmodule
diff --git a/tests/autoreset_if.v b/tests/autoreset_if.v
new file mode 100644
index 0000000..c4e5651
--- /dev/null
+++ b/tests/autoreset_if.v
@@ -0,0 +1,74 @@
+//From: "Chris Kappler" <ckappler@hhnetwk.com>
+
+//Verilint 440 off // WARNING: Clock is used as a reset
+//Verilint 394 off // WARNING: Multiple clocks in the always block
+//Verilint 71 off // WARNING: Case statement without default clause
+
+module x (/*AUTOARG*/
+ // Outputs
+ a, b, c,
+ // Inputs
+ clk, reset_l, in_a, in_b, in_c
+ );
+
+ input clk, reset_l, in_a,in_b,in_c;
+ output a,b,c;
+ reg a,b,c;
+
+ always @(posedge clk or negedge reset_l) begin
+ if (!reset_l) begin
+ c <= 1;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ a <= #1 0;
+ b <= #1 0;
+ // End of automatics
+ end
+ else begin
+ a <= in_a;
+ b <= in_b;
+ c <= in_c;
+ end
+ end
+
+ always @(posedge clk or negedge reset_l) begin
+ casex ({reset_l,in_a})
+ 2'b1_x: begin
+ a <= in_a;
+ b <= in_b;
+ c <= in_c;
+ end
+ 2'b0_x: begin
+ c <= 1;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ a <= #1 0;
+ b <= #1 0;
+ // End of automatics
+ end
+ endcase
+ end
+
+ always @(/*AS*/in_a or in_b or reset_l) begin
+ casex ({reset_l,in_a})
+ 2'b1_x: begin
+ a = in_a;
+ b = in_b;
+ end
+ 2'b0_x: begin
+ c = 1;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ a = 0;
+ b = 0;
+ // End of automatics
+ end
+ endcase
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-reset-widths: nil
+// verilog-assignment-delay: "#1 "
+// End:
diff --git a/tests/autoreset_ifndef_dc.v b/tests/autoreset_ifndef_dc.v
new file mode 100644
index 0000000..479da18
--- /dev/null
+++ b/tests/autoreset_ifndef_dc.v
@@ -0,0 +1,16 @@
+module x;
+ always @(posedge clk or negedge reset_l) begin
+ if (!reset_l) begin
+ c <= 1;
+ /*AUTORESET*/
+ end
+ else begin
+ a <= in_a;
+ b <= in_b;
+ c <= in_c;
+`ifndef DC
+ x <= 1'b1;
+`endif
+ end
+ end
+endmodule
diff --git a/tests/autoreset_inf_bug325.v b/tests/autoreset_inf_bug325.v
new file mode 100644
index 0000000..332cb32
--- /dev/null
+++ b/tests/autoreset_inf_bug325.v
@@ -0,0 +1,9 @@
+module aaa();
+ always @(a) begin
+ if (a) begin
+ /*AUTORESET*/
+ end
+ // note missing e-n-d
+ always @(*) begin
+ end
+endmodule
diff --git a/tests/autoreset_label_gorfajn.v b/tests/autoreset_label_gorfajn.v
new file mode 100644
index 0000000..3098b9e
--- /dev/null
+++ b/tests/autoreset_label_gorfajn.v
@@ -0,0 +1,12 @@
+module autoreset_label_gorfajn;
+
+ always_ff @(posedge clk or negedge reset)
+ if (~reset) begin
+ /*AUTORESET*/
+ end else begin
+ a<=b;
+ foo: assert (b==4);
+ bar: z<=1;
+ end
+
+endmodule
diff --git a/tests/autoreset_latch.v b/tests/autoreset_latch.v
new file mode 100644
index 0000000..04b3eb9
--- /dev/null
+++ b/tests/autoreset_latch.v
@@ -0,0 +1,63 @@
+//bug844
+module device(
+ input clk,
+ output logic [7:0] Q, out0,
+ output logic pass, fail
+ input [7:0] D, in0,in1 );
+
+ enum logic [2:0] {IDLE, START, RUN, PASS, FAIL } state, next_state;
+ logic ready, next_ready;
+ logic next_pass, next_fail;
+
+ always_ff @(posedge clk, negedge rstn)
+ if (!rstn) begin
+ state <= IDLE;
+ /*AUTORESET*/
+ end
+ else begin
+ state <= next_state;
+ ready <= next_ready;
+ pass <= next_pass;
+ fail <= next_fail;
+ end
+
+ always @* begin
+ if (!ready) begin
+ /*AUTORESET*/
+ end
+ else begin
+ out0 = sel ? in1 : in0;
+ end
+ end
+
+ always_comb begin
+ next_state = state;
+ /*AUTORESET*/
+ case (state)
+ IDLE : begin
+ // stuff ...
+ end
+ /* Other states */
+ PASS: begin
+ next_state = IDLE;
+ // stuff ...
+ next_pass = 1'b1;
+ next_ready = 1'b1;
+ end
+ FAIL: begin
+ next_state = IDLE;
+ // stuff ...
+ next_fail = 1'b1;
+ end
+ endcase
+ end
+
+ always_latch begin
+ if (!rstn) begin
+ /*AUTORESET*/
+ end
+ else if (clk) begin
+ Q <= D;
+ end
+ end
+endmodule
diff --git a/tests/autoreset_reed.v b/tests/autoreset_reed.v
new file mode 100644
index 0000000..ac91c3b
--- /dev/null
+++ b/tests/autoreset_reed.v
@@ -0,0 +1,28 @@
+module x;
+ reg a;
+ reg b;
+ reg c;
+ always @(/*AUTOSENSE*/) begin
+ if ( rst ) begin
+ /*AUTORESET*/
+ end
+ else begin
+ if ( a <= b ) begin
+ c = a;
+ end
+ else begin
+ c = b;
+ end
+ end
+ end
+
+ always @ (posedge a) begin
+ if ( rst ) begin
+ /*AUTORESET*/
+ end
+ else if ( a <= b ) begin
+ c <= a;
+ end
+ end
+
+endmodule
diff --git a/tests/autoreset_struct.v b/tests/autoreset_struct.v
new file mode 100644
index 0000000..b602e0c
--- /dev/null
+++ b/tests/autoreset_struct.v
@@ -0,0 +1,57 @@
+//bug906
+
+import gmcupkg::*;
+
+module gminstdecode
+ (
+ output instClassType instClass
+ /*blah blah blah*/);
+
+ always_comb begin
+ /*AUTORESET*/
+
+ if (ldBitFromIo | stBitToIo) begin
+ instClass.isBool = 1'b1;
+ instClass.iFunc = IFUNC_BOOL;
+ instClass.sub.bool = 1'b1;
+ instClass.sub2.sub3.bool = 1'b1;
+ end
+ end
+
+ always_comb begin
+ instClass = '{default:0}; // #1 (see below)
+ /*AUTORESET*/
+
+ if (ldBitFromIo | stBitToIo) begin
+ instClass.isBool = 1'b1;
+ instClass.iFunc = IFUNC_BOOL;
+ end
+ end
+
+ always_comb begin
+ instClass.iFunc = IFUNC_ADD; // #2
+ /*AUTORESET*/
+
+ if (ldBitFromIo | stBitToIo) begin
+ instClass.isBool = 1'b1;
+ instClass.iFunc = IFUNC_BOOL;
+ end
+ end
+
+ always_comb begin
+ instClass.sub = '0;
+ instClass.sub2 = '0;
+ /*AUTORESET*/
+
+ if (ldBitFromIo | stBitToIo) begin
+ instClass.sub.bool = 1'b1;
+ instClass.sub2.sub3.bool = 1'b1;
+ instClass.sub3.sub4.bool = 1'b1;
+ end
+ end
+endmodule
+
+// Local Variables:
+// verilog-auto-reset-widths: unbased
+// verilog-typedef-regexp: "Type$"
+// End:
diff --git a/tests/autoreset_widths.v b/tests/autoreset_widths.v
new file mode 100644
index 0000000..539621a
--- /dev/null
+++ b/tests/autoreset_widths.v
@@ -0,0 +1,60 @@
+// $Revision: #70 $$Date: 2002/10/19 $$Author: wsnyder $ -*- Verilog -*-
+//====================================================================
+
+module CmpEng (/*AUTOARG*/);
+
+ input clk;
+ input reset_l;
+
+ // ****************************************************************
+
+ /*AUTOREG*/
+ /*AUTOWIRE*/
+
+ // ********* Prefetch FSM definitions ****************************
+
+ reg [3:0] m_cac_state_r;
+
+ reg [2:0] m_cac_sel_r, m_dat_sel_r, m_cac_rw_sel_r;
+
+ reg m_wid1_r;
+ reg [2:0] m_wid3_r;
+ reg [5:2] m_wid4_r_l;
+
+ logic [4:1] logic_four;
+
+ logic [PARAM-1:0] paramed;
+
+`define M 2
+`define L 1
+ parameter MS = 2;
+ parameter LS = 1;
+
+ reg [MS:LS] m_param_r;
+ reg [`M:`L] m_def2_r;
+
+ always @ (posedge clk) begin
+ if (~reset_l) begin
+ m_cac_state_r <= CAC_IDLE;
+ m_cac_sel_r <= CSEL_PF;
+ /*AUTORESET*/
+ end
+ else begin
+ m_wid1_r <= 0;
+ m_wid3_r <= 0;
+ m_wid4_r_l <= 0;
+ m_param_r <= 0;
+ m_def2_r <= 0;
+ logic_four <= 4;
+ paramed <= 1;
+ end
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// verilog-auto-sense-defines-constant: t
+// verilog-auto-reset-widths: t
+// verilog-active-low-regexp: "_l$"
+// End:
diff --git a/tests/autoreset_widths_unbased.v b/tests/autoreset_widths_unbased.v
new file mode 100644
index 0000000..e9e07c6
--- /dev/null
+++ b/tests/autoreset_widths_unbased.v
@@ -0,0 +1,60 @@
+// $Revision: #70 $$Date: 2002/10/19 $$Author: wsnyder $ -*- Verilog -*-
+//====================================================================
+
+module CmpEng (/*AUTOARG*/);
+
+ input clk;
+ input reset_l;
+
+ // ****************************************************************
+
+ /*AUTOREG*/
+ /*AUTOWIRE*/
+
+ // ********* Prefetch FSM definitions ****************************
+
+ reg [3:0] m_cac_state_r;
+
+ reg [2:0] m_cac_sel_r, m_dat_sel_r, m_cac_rw_sel_r;
+
+ reg m_wid1_r;
+ reg [2:0] m_wid3_r;
+ reg [5:2] m_wid4_r_l;
+
+ logic [4:1] logic_four;
+
+ logic [PARAM-1:0] paramed;
+
+`define M 2
+`define L 1
+ parameter MS = 2;
+ parameter LS = 1;
+
+ reg [MS:LS] m_param_r;
+ reg [`M:`L] m_def2_r;
+
+ always @ (posedge clk) begin
+ if (~reset_l) begin
+ m_cac_state_r <= CAC_IDLE;
+ m_cac_sel_r <= CSEL_PF;
+ /*AUTORESET*/
+ end
+ else begin
+ m_wid1_r <= 0;
+ m_wid3_r <= 0;
+ m_wid4_r_l <= 0;
+ m_param_r <= 0;
+ m_def2_r <= 0;
+ logic_four <= 4;
+ paramed <= 1;
+ end
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// verilog-auto-sense-defines-constant: t
+// verilog-auto-reset-widths: unbased
+// verilog-active-low-regexp: "_l$"
+// End:
diff --git a/tests/autosense.v b/tests/autosense.v
new file mode 100644
index 0000000..f2e99a9
--- /dev/null
+++ b/tests/autosense.v
@@ -0,0 +1,39 @@
+module autosense (/*AUTOARG*/);
+
+ input ina;
+ input inb;
+ input inc;
+ output [1:0] out;
+ output out2;
+
+ /*AUTOREG*/
+
+`include "autosense_inc_param.v"
+`include "autosense_one.v"
+`define Input ina
+
+ always @(/*AUTOSENSE*/) begin
+ case (inc)
+ 1'b1: out = {`Input ? `one : 1'b0, `Input};
+ default: out = {2{inb}};
+ endcase
+ end
+
+
+ always @(/*AUTOSENSE*/) begin
+ out2 = `Input | PARAM_TWO | PARAM_THREE | PARAM_FOUR;
+ end
+
+ always @(*) begin
+ // @ (/*AS*/)
+ out3 = ina;
+ end
+
+ always @* begin
+ out3 = ina;
+ end
+
+endmodule
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests/autosense_aas_ifdef.v b/tests/autosense_aas_ifdef.v
new file mode 100644
index 0000000..a60f150
--- /dev/null
+++ b/tests/autosense_aas_ifdef.v
@@ -0,0 +1,54 @@
+module dummy;
+
+ parameter [TSTBITS-1:0] // synopsys enum tstate_info
+ TIDLE = 3'b000,
+ TCN1 = 3'b001,
+ TCN2 = TCN1+1, // must be numbered consecutively
+ TCN3 = TCN2+1,
+ TCN4 = TCN3+1,
+ TCN5 = TCN4+1,
+ IOCLR = TCN5+1,
+ TUNU1 = 3'b111;
+
+ // state and output logic
+ always @ (`ifdef SIMFSM
+ ireset or
+ `endif
+ /*AUTOSENSE*/fooc2_qual or foocr_we or ioclrinst or tstate) begin
+ ioclrtmout = 1'b0;
+ case (tstate)
+ TIDLE: begin
+ if (foocr_we)
+ ntstate = TCN1;
+ else
+ ntstate = TIDLE;
+ end
+ TCN1,TCN2,TCN3,TCN4,TCN5: begin
+ if (ioclrinst | fooc2_qual)
+ ntstate = TIDLE;
+ else
+ ntstate = tstate + 1;
+ end
+ IOCLR: begin
+ ntstate = TIDLE;
+ ioclrtmout = 1'b1;
+ end
+ TUNU1: begin
+ ntstate = TIDLE;
+ `ifdef SIMFSM
+ if (~ireset)
+ $display("ERROR: entered unused state at %t",$time);
+ `endif
+ end
+ default: begin
+ ntstate = 'bx;
+ ioclrtmout = 1'bx;
+ `ifdef SIMFSM
+ if (~ireset)
+ $display("ERROR: entered unknown state at %t",$time);
+ `endif
+ end
+ endcase // case(tstate)
+ end // always @ (...
+
+endmodule // dummy
diff --git a/tests/autosense_add_or.v b/tests/autosense_add_or.v
new file mode 100644
index 0000000..95c90f5
--- /dev/null
+++ b/tests/autosense_add_or.v
@@ -0,0 +1,24 @@
+module autosense_or(/*AUTOARG*/
+ // Outputs
+ x, y,
+ // Inputs
+ a, c
+ );
+
+ input a;
+ input c;
+ output x;
+ output y;
+
+ always @(a/*AUTOSENSE*/) begin
+ x = a;
+ end
+ always @(a/*AUTOSENSE*/ or c) begin
+ x = a | c;
+ end
+ // always @(a or/*AUTOSENSE*/c) begin
+ // x = a | c;
+ // end
+
+endmodule
+
diff --git a/tests/autosense_chadha.v b/tests/autosense_chadha.v
new file mode 100644
index 0000000..b5ea4d8
--- /dev/null
+++ b/tests/autosense_chadha.v
@@ -0,0 +1,37 @@
+module test (/*AUTOARG*/
+ // Outputs
+ out1, out2,
+ // Inputs
+ sel, in0, in1, in2
+ );
+
+ input [1:0] sel;
+ input in0, in1, in2;
+
+ output out1;
+ output out2;
+
+ reg out1;
+ reg out2;
+
+ // Missing in2
+ always @ (/*AS*/in0 or in1 or in2 or sel)
+ if (sel == 2'b00)
+ begin
+ out1 = in1;
+ out2 = in0;
+ end
+ else
+ begin
+ out1 = in2;
+ out2 = in1;
+ end
+
+ // OK
+ always @ (/*AS*/in1 or in2 or sel)
+ if (sel == 2'b00)
+ out1 = in1;
+ else
+ out1 = in2;
+
+endmodule // test
diff --git a/tests/autosense_define_hang.v b/tests/autosense_define_hang.v
new file mode 100644
index 0000000..c0ec076
--- /dev/null
+++ b/tests/autosense_define_hang.v
@@ -0,0 +1,8 @@
+//From: Anup Sharma <asharma@Eng.Sun.COM>
+
+module x;
+
+ always @ (/*AS*/`EC_EXCLU or `EC_SHARE or jpack_share) begin
+ jb_mc_xact_state_a1[2:0] <= #1 jpack_share[7] ? `EC_SHARE : `EC_EXCLU;
+ end
+endmodule
diff --git a/tests/autosense_dittrich.v b/tests/autosense_dittrich.v
new file mode 100644
index 0000000..3c974ec
--- /dev/null
+++ b/tests/autosense_dittrich.v
@@ -0,0 +1,29 @@
+module testcase
+ (/*AUTOARG*/
+ // Outputs
+ Z,
+ // Inputs
+ A, B, C, D, SEL
+ );
+
+ input A, B, C, D;
+ input [1:0] SEL;
+ output Z;
+
+`include autosense_dittrich_inc.v
+
+ always @(/*AS*/A or B or C or D or SEL) begin
+ case (SEL)
+ sel_a: Z = A;
+ sel_b: Z = B;
+ sel_c: Z = C;
+ sel_d: Z = D;
+ default: Z = D;
+ endcase // case(SEL)
+ end // always @ (...
+
+endmodule // testcase
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests/autosense_dittrich_inc.v b/tests/autosense_dittrich_inc.v
new file mode 100644
index 0000000..228bc29
--- /dev/null
+++ b/tests/autosense_dittrich_inc.v
@@ -0,0 +1,9 @@
+parameter sel_a = {1'b 0, 1'b 0}; // 2'd 0 works fine
+parameter sel_b = {1'b 0, 1'b 1}; // 2'd 1 works fine
+parameter sel_c = 2'd 2,
+ sel_d = 2'd 3;
+
+//parameter sel_a = {1'b 0, 1'b 0}, // 2'd 0 works fine
+// sel_b = {1'b 0, 1'b 1}, // 2'd 1 works fine
+// sel_c = 2'd 2,
+// sel_d = 2'd 3;
diff --git a/tests/autosense_gifford.v b/tests/autosense_gifford.v
new file mode 100644
index 0000000..6dba181
--- /dev/null
+++ b/tests/autosense_gifford.v
@@ -0,0 +1,32 @@
+module x (/*AUTOARG*/);
+
+ // Which Internal Bank
+`define DMC_AG_HADDR_BADDR_BST2_RNG 1:0 // Bank Address Range within Hexabyte Address for 2-Burst
+`define DMC_AG_HADDR_BADDR_BST4_RNG 2:1 // Bank Address Range within Hexabyte Address for 4-Burst
+`define DMC_AG_HADDR_BADDR_BST8_RNG 3:2 // Bank Address Range within Hexabyte Address for 8-Burst
+
+ reg [NumBnks-1:0] ibnk_sel_s; // Muxed internal bank address subfield of
+ command address
+ always @(/*AUTOSENSE*/lio_buscfg_brstlen2_sr or lio_buscfg_brstlen4_sr or m_cdq_haddr_sr)
+ begin : PeelIntBnkAddr
+ case ({lio_buscfg_brstlen4_sr,lio_buscfg_brstlen2_sr})
+ 2'b01: // 2-burst
+ begin
+ ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST2_RNG];
+ end
+ 2'b10: // 4-burst
+ begin
+ ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST4_RNG];
+ end
+ default: // 8-burst
+ begin
+ ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST8_RNG];
+ end
+ endcase
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests/autosense_if_else.v b/tests/autosense_if_else.v
new file mode 100644
index 0000000..a712319
--- /dev/null
+++ b/tests/autosense_if_else.v
@@ -0,0 +1,13 @@
+module x;
+
+ always @ (/*AS*/a or b or c)
+ if (a) q = b;
+ else r = c;
+
+ always @ (/*AS*/a or b or c or d or e)
+ if (a) q = b;
+ else if (c) r = d;
+ /* skip comments as usual */
+ else r = e;
+
+endmodule
diff --git a/tests/autosense_inandout.v b/tests/autosense_inandout.v
new file mode 100644
index 0000000..478a9af
--- /dev/null
+++ b/tests/autosense_inandout.v
@@ -0,0 +1,14 @@
+module autosense_inandout(a,b);
+
+ input a;
+ output b;
+ reg b;
+ reg c;
+
+ always @(/*AUTOSENSE*/a) begin
+ c=a;
+ b=c;
+ end
+
+endmodule
+
diff --git a/tests/autosense_inc_param.v b/tests/autosense_inc_param.v
new file mode 100644
index 0000000..528ca40
--- /dev/null
+++ b/tests/autosense_inc_param.v
@@ -0,0 +1,6 @@
+
+parameter [2:0] PARAM_TWO = 2,
+ PARAM_THREE = 3;
+parameter PARAM_FOUR = 4;
+
+
diff --git a/tests/autosense_jbrown.v b/tests/autosense_jbrown.v
new file mode 100644
index 0000000..50ad221
--- /dev/null
+++ b/tests/autosense_jbrown.v
@@ -0,0 +1,31 @@
+`define LCH_GSWDATWID 3
+`define COM_CLDATWID 2
+
+module autosense_jbrown(/*AUTOARG*/
+ // Outputs
+ lch_gswdata,
+ // Inputs
+ com_cldata
+ );
+
+ output [`LCH_GSWDATWID-1:0] lch_gswdata; // data to switch
+ input [`COM_CLDATWID-1:0] com_cldata; // data bus to clusters
+
+ /*autowire*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ // End of automatics
+
+ reg tmp;
+`define TEST_DEFINE 1'b0
+ always @ (/*AUTOSENSE*/)
+ begin
+ /* AUTO_CONSTANT (`TEST_DEFINE) */
+ tmp <= `TEST_DEFINE; // test defines
+ end
+
+ // Local Variables:
+ // verilog-library-directories:("." "../cdp/")
+ // verilog-library-extensions:(".v" ".vh")
+ // End:
+
+endmodule
diff --git a/tests/autosense_lavinge.v b/tests/autosense_lavinge.v
new file mode 100644
index 0000000..663447b
--- /dev/null
+++ b/tests/autosense_lavinge.v
@@ -0,0 +1,15 @@
+module test
+ #(parameter FOO=1)
+ ( a, b );
+input a;
+input b;
+
+reg c;
+wire d;
+
+always @(/*AUTOSENSE*/)
+ begin
+ c=0;
+ if (d) c = b;
+ end
+endmodule
diff --git a/tests/autosense_mcardle_onehot.v b/tests/autosense_mcardle_onehot.v
new file mode 100644
index 0000000..fd0b784
--- /dev/null
+++ b/tests/autosense_mcardle_onehot.v
@@ -0,0 +1,28 @@
+module x;
+
+ input [5:0] state;
+ output [5:0] next;
+
+ parameter CYCLEA = 1;
+ parameter CYCLEC = 2;
+ parameter MSTRA = 3;
+ parameter MSTRB = 4;
+ parameter MSTRC = 5;
+
+ // make sure 'state' is listed
+ always @ (/*AUTOSENSE*/done or nREQA or nREQB or nREQC or state) begin
+ next = 6'b0;
+ case (1'b1)
+ state[CYCLEC] : begin
+ if (!nREQA && done) next[MSTRA] = 1'b1;
+ else if (!nREQB && nREQA && done)next[MSTRB] = 1'b1;
+ else if (!nREQC && nREQA && nREQB && done) next[MSTRC] = 1'b1;
+ else next[CYCLEC] = 1'b1;
+ end
+ state[MSTRA] : begin
+ if (!nREQB || !nREQC) next[CYCLEA] = 1'b1;
+ else next[MSTRA] = 1'b1;
+ end
+ endcase
+ end
+endmodule
diff --git a/tests/autosense_metzger_space.v b/tests/autosense_metzger_space.v
new file mode 100644
index 0000000..674d9a9
--- /dev/null
+++ b/tests/autosense_metzger_space.v
@@ -0,0 +1,21 @@
+module x (/*AUTOARG*/
+ // Outputs
+ rmsk0, rmsk1, rmsk2,
+ // Inputs
+ endbyte0, endbyte1, endbyte2, strtbyte0, strtbyte1, strtbyte2
+ );
+ input endbyte0;
+ input endbyte1;
+ input endbyte2;
+ input strtbyte0;
+ input strtbyte1;
+ input strtbyte2;
+ output rmsk0;
+ output rmsk1;
+ output rmsk2;
+
+ always @ (/*AS*/endbyte0 or strtbyte0) rmsk0 = maskcalc(strtbyte0,endbyte0);
+ always @ (/*AS*/endbyte1 or strtbyte1) rmsk1 = maskcalc(strtbyte1,endbyte1);
+ always @ (/*AS*/endbyte2 or strtbyte2) rmsk2 = maskcalc(strtbyte2,endbyte2);
+
+endmodule
diff --git a/tests/autosense_one.v b/tests/autosense_one.v
new file mode 100644
index 0000000..b6cfcb0
--- /dev/null
+++ b/tests/autosense_one.v
@@ -0,0 +1,2 @@
+`define one 1'b1
+
diff --git a/tests/autosense_peers_func.v b/tests/autosense_peers_func.v
new file mode 100644
index 0000000..13469e0
--- /dev/null
+++ b/tests/autosense_peers_func.v
@@ -0,0 +1,39 @@
+module x;
+
+ always @(/*AUTOSENSE*/arb_select_f or octet_idx) begin
+ octet_flag[0] = |arb_select_f[ 7: 0];
+ octet_flag[1] = |arb_select_f[15: 8];
+ octet_flag[2] = |arb_select_f[23:16];
+ octet_flag[3] = |arb_select_f[31:24];
+ octet_flag[4] = |arb_select_f[39:32];
+ octet_flag[5] = |arb_select_f[47:40];
+ octet_flag[6] = |arb_select_f[55:48];
+ octet_flag[7] = |arb_select_f[63:56];
+
+ octet_available = |octet_flag;
+
+ shifted8_64 = barrel_shifter(octet_flag, octet_idx[5:3]);
+ end // always @ (arb_select_f)
+
+endmodule
+
+function [7:0] barrel_shifter;
+
+ input [7:0] source;
+ input [2:0] shift_amt;
+
+ begin
+ case (shift_amt) //synopsys parallel_case full_case
+ 3'b0: barrel_shifter = source;
+ 3'b1: barrel_shifter = {source[0], source[7:1]};
+ 3'b2: barrel_shifter = {source[1:0], source[7:2]};
+ 3'b3: barrel_shifter = {source[2:0], source[7:3]};
+ 3'b4: barrel_shifter = {source[3:0], source[7:4]};
+ 3'b5: barrel_shifter = {source[4:0], source[7:5]};
+ 3'b6: barrel_shifter = {source[5:0], source[7:6]};
+ 3'b7: barrel_shifter = {source[6:0], source[7]};
+ endcase // case(shift_amt)
+ end
+
+endfunction // barrel_shifter
+
diff --git a/tests/autosense_rogoff.v b/tests/autosense_rogoff.v
new file mode 100644
index 0000000..9679a37
--- /dev/null
+++ b/tests/autosense_rogoff.v
@@ -0,0 +1,10 @@
+
+module x;
+ always @ (/*as*/a or ff)
+ case (a)
+ 1: if (ff[3:0] == 4'd3)
+ sadfsdff;
+ endcase
+
+
+endmodule
diff --git a/tests/autosense_smith.v b/tests/autosense_smith.v
new file mode 100644
index 0000000..a29ab51
--- /dev/null
+++ b/tests/autosense_smith.v
@@ -0,0 +1,56 @@
+module x;
+
+ reg [31:0] mb_reg_output;
+
+ // 16 registers max, register 15 is always the version number, so 15 are useable
+ // NOTE: number_interface_regs must be the maximum (or 16 in this case) to get the version register
+ parameter NUMBER_INTERFACE_REGS = 16;
+ parameter MB_REG_START = 3; // start at 4th register location 'h0010
+ parameter CMD_REG_0_ADDR = MB_REG_START;
+ parameter CMD_REG_1_ADDR = MB_REG_START+1;
+ parameter CMD_REG_2_ADDR = MB_REG_START+2;
+ parameter CMD_REG_3_ADDR = MB_REG_START+3;
+ parameter CMD_REG_4_ADDR = MB_REG_START+4;
+ parameter CMD_REG_5_ADDR = MB_REG_START+5;
+ parameter CMD_REG_6_ADDR = MB_REG_START+6;
+ parameter CMD_REG_7_ADDR = MB_REG_START+7;
+ parameter CMD_REG_8_ADDR = MB_REG_START+8;
+ parameter CMD_REG_9_ADDR = MB_REG_START+9;
+ parameter CMD_REG_10_ADDR = MB_REG_START+10;
+ // mode regs
+ parameter MODE_REG_0_ADDR = CMD_REG_8_ADDR;
+
+ // Absolute register 14 is Error counter
+ parameter CMD_REG_14_ADDR = 14;
+ parameter CRC_ERROR_REG_ADDR = CMD_REG_14_ADDR;
+ // ------------ VERSION register is 15
+ parameter VERSION_REG_ADDR = 15;
+
+ reg [NUMBER_INTERFACE_REGS-1:MB_REG_START] mb_reg_wr;
+ reg [NUMBER_INTERFACE_REGS-1:MB_REG_START] mb_reg_rd;
+ wire [31:0] mb_reg_out_w [NUMBER_INTERFACE_REGS-1:MB_REG_START];
+ wire [31:0] interface_from_core_fp;
+
+ assign
+ mb_reg_out_w[VERSION_REG_ADDR] = BUILD_VERSION;
+
+ integer mb_loop;
+ always @(/*AUTOSENSE*/)
+
+ begin: MB_READ_WRITE_SEL_P
+
+ mb_reg_wr = 'h0;
+ mb_reg_rd = 'h0;
+ mb_reg_output = interface_from_core_fp;
+
+ for(mb_loop = MB_REG_START; mb_loop < NUMBER_INTERFACE_REGS; mb_loop=mb_loop+1)
+ begin
+ if(mb_reg_select[mb_loop] == 1'b1)
+ begin
+ mb_reg_rd[mb_loop] = mb_reg_select[mb_loop] & mb_reg_rwn;
+ mb_reg_wr[mb_loop] = mb_reg_select[mb_loop] & !mb_reg_rwn;
+ mb_reg_output = mb_reg_out_w[mb_loop];
+ end
+ end
+ end
+endmodule // x
diff --git a/tests/autosense_venkataramanan_begin.v b/tests/autosense_venkataramanan_begin.v
new file mode 100644
index 0000000..4e121f4
--- /dev/null
+++ b/tests/autosense_venkataramanan_begin.v
@@ -0,0 +1,18 @@
+
+module autosense_venkataramanan_begin(/*AUTOARG*/);
+
+ reg a,b;
+
+ always @(/*AUTOSENSE*/b or i) // I didn't expect to get "i" in AUTOSENSE
+ begin : label
+ integer i, j;
+ for (i=0; i<= 3; i = i + 1)
+ vec[i] = b;
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-sense-defines-constant: t
+// verilog-auto-sense-include-inputs: t
+// End:
diff --git a/tests/autotieoff_assign.v b/tests/autotieoff_assign.v
new file mode 100644
index 0000000..d94b35a
--- /dev/null
+++ b/tests/autotieoff_assign.v
@@ -0,0 +1,19 @@
+module autotieoff_signed (/*AUTOARG*/);
+
+ output [2:0] ExtraOut;
+ output [2:0] SubOut;
+ output [3:0] active_low_l;
+ output [3:0] ignored_by_regexp;
+
+ /*AUTOTIEOFF*/
+
+endmodule
+
+module sub;
+ input SubIn;
+ output SubOut;
+endmodule
+
+// Local Variables:
+// verilog-auto-tieoff-declaration: "assign"
+// End:
diff --git a/tests/autotieoff_signed.v b/tests/autotieoff_signed.v
new file mode 100644
index 0000000..4e82ff2
--- /dev/null
+++ b/tests/autotieoff_signed.v
@@ -0,0 +1,49 @@
+module autotieoff_signed (/*AUTOARG*/);
+
+ input [2:0] ExtraIn;
+ input [2:0] SubIn;
+ output [2:0] ExtraOut;
+ output [2:0] SubOut;
+ output [3:0] active_low_l;
+ output [3:0] ignored_by_regexp;
+
+ /*AUTOINOUTMODULE("autoinst_signed")*/
+
+ // =============================
+ // Auto Wires/Regs
+ // =============================
+
+ /*AUTOWIRE*/
+ /*AUTOREG*/
+
+ // =============================
+ // Tieoffs
+ // =============================
+
+ /*AUTOTIEOFF*/
+
+ // =============================
+
+ sub sub (/*AUTOINST*/);
+
+ // =============================
+ // Unused signals
+ // =============================
+
+ // lint_checking SCX_UNUSED OFF
+ wire _unused_ok = &{1'b0,
+ /*AUTOUNUSED*/
+ 1'b0};
+ // lint_checking SCX_UNUSED OFF
+
+endmodule
+
+module sub;
+ input SubIn;
+ output SubOut;
+endmodule
+
+// Local Variables:
+// verilog-active-low-regexp: "_l$"
+// verilog-auto-tieoff-ignore-regexp: "ignored"
+// End:
diff --git a/tests/autoundef.v b/tests/autoundef.v
new file mode 100644
index 0000000..9564355
--- /dev/null
+++ b/tests/autoundef.v
@@ -0,0 +1,28 @@
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+module temp;
+
+`define FOO(a)
+`define BAR
+`define BAZ
+
+.....
+
+`undef BAR
+`define BAR
+`define BAZ // AGAIN
+
+/*AUTOUNDEF*/
+
+// Make sure this list is empty
+/*AUTOUNDEF*/
+
+//======================================================================
+
+`define M_A
+`define X_B
+
+/*AUTOUNDEF("^M_")*/
+
+endmodule
diff --git a/tests/autounused.v b/tests/autounused.v
new file mode 100644
index 0000000..2695ae1
--- /dev/null
+++ b/tests/autounused.v
@@ -0,0 +1,28 @@
+module wbuf
+ #(parameter width=1)
+ (output [width-1:0] q,
+ input [width-1:0] d);
+endmodule
+
+module autounused
+ #(parameter width=3)
+ (/*AUTOARG*/) ;
+
+ /*AUTOOUTPUT*/
+ input da, db, dc, dd;
+ /*AUTOINPUT*/
+
+ wire _unused_ok = &{/*AUTOUNUSED*/
+ 1'b0};
+
+ defparam partbuf.width = width;
+ wbuf wbuf
+ (// Inputs
+ .d ({da,db,dc}),
+ /*AUTOINST*/);
+
+endmodule // abuf
+
+// Local Variables:
+// verilog-auto-unused-ignore-regexp: "^db$"
+// End:
diff --git a/tests/autowire_godiwala.v b/tests/autowire_godiwala.v
new file mode 100644
index 0000000..d8b8681
--- /dev/null
+++ b/tests/autowire_godiwala.v
@@ -0,0 +1,346 @@
+module FswArbiter (/*AUTOARG*/) ;
+
+
+ // ========================
+ // Include parameter File
+ // ========================
+ parameter DMAO = 0;
+
+`include "chip_fsw_spec_param.v"
+
+ // ===============
+ // Physical Pins
+ // ===============
+
+ input sclk; // Fabric switch clock
+ input lreset_l;
+
+ input csr_insert_idle;
+ input csr_arb_enable;
+
+ input [3:0] csr_bypass3_enable;
+ input [3:0] csr_bypass2_enable;
+ input [3:0] csr_bypass1_enable;
+
+ input csr_xb_ecc_enable;
+
+ output [3:0] xb_ecc_error_dbit;
+ output [3:0] xb_ecc_error_1bit;
+
+ output insert_idle_ack;
+
+ output [2:0] bp_performance_count;
+
+ input xb0_obx_ReqPst_s2a;
+ input [3:0] xb0_obx_NextVc_s2a;
+ input [1:0] xb0_obx_NextPort_s2a;
+ input [3:0] xb0_obx_NextXbe_s2a;
+ input [3:0] xb0_obx_NextXbe_s3a;
+ input [71:0] xb0_obx_OutDat_s4a;
+
+ output obx_xb0_GntPst_s3a;
+ output obx_xb0_GntByp_s3a;
+
+ input xb0_obx_ReqBypS3_s2a;
+ input xb0_obx_ReqBypS2_s2a;
+
+ input xb1_obx_ReqPst_s2a;
+ input [3:0] xb1_obx_NextVc_s2a;
+ input [1:0] xb1_obx_NextPort_s2a;
+ input [3:0] xb1_obx_NextXbe_s2a;
+ input [3:0] xb1_obx_NextXbe_s3a;
+ input [71:0] xb1_obx_OutDat_s4a;
+
+ output obx_xb1_GntPst_s3a;
+ output obx_xb1_GntByp_s3a;
+
+ input xb1_obx_ReqBypS3_s2a;
+ input xb1_obx_ReqBypS2_s2a;
+
+ input xb2_obx_ReqPst_s2a;
+ input [3:0] xb2_obx_NextVc_s2a;
+ input [1:0] xb2_obx_NextPort_s2a;
+ input [3:0] xb2_obx_NextXbe_s2a;
+ input [3:0] xb2_obx_NextXbe_s3a;
+ input [71:0] xb2_obx_OutDat_s4a;
+
+ output obx_xb2_GntPst_s3a;
+ output obx_xb2_GntByp_s3a;
+
+ input xb2_obx_ReqBypS3_s2a;
+ input xb2_obx_ReqBypS2_s2a;
+
+ input xb3_obx_ReqPst_s2a;
+ input [3:0] xb3_obx_NextVc_s2a;
+ input [1:0] xb3_obx_NextPort_s2a;
+ input [3:0] xb3_obx_NextXbe_s2a;
+ input [3:0] xb3_obx_NextXbe_s3a;
+ input [71:0] xb3_obx_OutDat_s4a;
+
+ output obx_xb3_GntPst_s3a;
+ output obx_xb3_GntByp_s3a;
+
+ input xb3_obx_ReqBypS3_s2a;
+ input xb3_obx_ReqBypS2_s2a;
+
+ input ib0_obx_PortSel_s1a;
+ input [63:0] ib0_obx_InDat_s1a;
+ input [1:0] ib0_obx_NextPort_s1a;
+ input [3:0] ib0_obx_NextVc_s1a;
+
+ input ib1_obx_PortSel_s1a;
+ input [63:0] ib1_obx_InDat_s1a;
+ input [1:0] ib1_obx_NextPort_s1a;
+ input [3:0] ib1_obx_NextVc_s1a;
+
+ input ib2_obx_PortSel_s1a;
+ input [63:0] ib2_obx_InDat_s1a;
+ input [1:0] ib2_obx_NextPort_s1a;
+ input [3:0] ib2_obx_NextVc_s1a;
+
+ input ib3_obx_PortSel_s1a;
+ input [63:0] ib3_obx_InDat_s1a;
+ input [1:0] ib3_obx_NextPort_s1a;
+ input [3:0] ib3_obx_NextVc_s1a;
+
+ input rp_is_full;
+ input rp_in_progress;
+
+ input [15:0] rp_arb_poolmask;
+ input [63:0] rp_arb_bufbusy_mask;
+
+ output xbx_grant_cycle;
+ output bp1_grant_cycle;
+ output set_arbitration_enable_d1;
+
+ output [63:0] reset_ackbuf;
+ output [63:0] wait_for_ack;
+
+ output [63:0] ice9_databus;
+
+ // =============================
+ // Auto Wires/Regs
+ // =============================
+
+ /*AUTOWIRE*/
+ /*AUTOREG*/
+
+/* FswBypassArbiter AUTO_TEMPLATE (
+ // Outputs
+ .bp_grant3 (bp@_grant3),
+ .bp_grant2 (bp@_grant2),
+ .bp_grant1 (bp@_grant1),
+ .bp_grant0 (bp@_grant0),
+ .bp_grant_cycle (bp@_grant_cycle),
+ .bp_grant_cycle_d1 (bp@_grant_cycle_d1),
+ .bp_grant_cycle_d2 (bp@_grant_cycle_d2),
+ .bp_next_winner (bp@_next_winner[1:0]),
+ .bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
+ .bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
+ .bp_nextxbe (bp@_nextxbe[3:0]),
+ .bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
+ .bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
+ .bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
+ .bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
+ .bp_select (bp@_select),
+ .bp_select_d1 (bp@_select_d1),
+ .bp_select_d2 (bp@_select_d2),
+ .bp_header (bp@_header),
+ .bp_header_d1 (bp@_header_d1),
+ .bp_header_d2 (bp@_header_d2),
+ // Inputs
+ .lreset_l (bp@_lreset_l),
+ .bp_arb_enable (bp@_arb_enable),
+ .sop3 (sop3 & xbx_bp3_enable_3),
+ .sop2 (sop2 & xbx_bp3_enable_2),
+ .sop1 (sop1 & xbx_bp3_enable_1),
+ .sop0 (sop0 & xbx_bp3_enable_0),
+ ); */
+
+
+ FswBypassArbiter bp3 (/*AUTOINST*/);
+
+
+/* FswBypassArbiter AUTO_TEMPLATE (
+ // Outputs
+ .bp_grant3 (bp@_grant3),
+ .bp_grant2 (bp@_grant2),
+ .bp_grant1 (bp@_grant1),
+ .bp_grant0 (bp@_grant0),
+ .bp_grant_cycle (bp@_grant_cycle),
+ .bp_grant_cycle_d1 (bp@_grant_cycle_d1),
+ .bp_grant_cycle_d2 (bp@_grant_cycle_d2),
+ .bp_next_winner (bp@_next_winner[1:0]),
+ .bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
+ .bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
+ .bp_nextxbe (bp@_nextxbe[3:0]),
+ .bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
+ .bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
+ .bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
+ .bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
+ .bp_select (bp@_select),
+ .bp_select_d1 (bp@_select_d1),
+ .bp_select_d2 (bp@_select_d2),
+ .bp_header (bp@_header),
+ .bp_header_d1 (bp@_header_d1),
+ .bp_header_d2 (bp@_header_d2),
+ // Inputs
+ .lreset_l (bp@_lreset_l),
+ .bp_arb_enable (bp@_arb_enable),
+ .sop3 (sop3 & xbx_bp2_enable_3),
+ .sop2 (sop2 & xbx_bp2_enable_2),
+ .sop1 (sop1 & xbx_bp2_enable_1),
+ .sop0 (sop0 & xbx_bp2_enable_0),
+ ); */
+
+
+ FswBypassArbiter bp2 (/*AUTOINST*/);
+
+
+/* FswBypassArbiter AUTO_TEMPLATE (
+ // Outputs
+ .bp_grant3 (bp@_grant3),
+ .bp_grant2 (bp@_grant2),
+ .bp_grant1 (bp@_grant1),
+ .bp_grant0 (bp@_grant0),
+ .bp_grant_cycle (bp@_grant_cycle),
+ .bp_grant_cycle_d1 (bp@_grant_cycle_d1),
+ .bp_grant_cycle_d2 (bp@_grant_cycle_d2),
+ .bp_next_winner (bp@_next_winner[1:0]),
+ .bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
+ .bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
+ .bp_nextxbe (bp@_nextxbe[3:0]),
+ .bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
+ .bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
+ .bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
+ .bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
+ .bp_select (bp@_select),
+ .bp_select_d1 (bp@_select_d1),
+ .bp_select_d2 (bp@_select_d2),
+ .bp_header (bp@_header),
+ .bp_header_d1 (bp@_header_d1),
+ .bp_header_d2 (bp@_header_d2),
+ // Inputs
+ .lreset_l (bp@_lreset_l),
+ .bp_arb_enable (bp@_arb_enable),
+ .sop3 (sop3 & csr_bp1_enable_3),
+ .sop2 (sop2 & csr_bp1_enable_2),
+ .sop1 (sop1 & csr_bp1_enable_1),
+ .sop0 (sop0 & csr_bp1_enable_0),
+ ); */
+
+
+ FswBypassArbiter bp1 (/*AUTOINST*/);
+
+
+ // =======================================
+ // Coverage
+ // =======================================
+
+ // psl default clock = negedge sclk;
+ generate if (DMAO == 0)
+ begin
+ // psl cover {lreset_l & (bp1_grant0 |bp1_grant1 |bp1_grant2 |bp1_grant3 )} report "FswPerfRtl::byp1Taken";
+ // psl cover {lreset_l & (bp2_grant0 |bp2_grant1 |bp2_grant2 |bp2_grant3)} report "FswPerfRtl::byp2Taken";
+ // psl cover {lreset_l & (bp3_grant0 |bp3_grant1 |bp3_grant2 |bp3_grant3)} report "FswPerfRtl::byp3Taken";
+ end
+ endgenerate
+
+ // ================
+ // Unused signals
+ // ================
+
+ // lint_checking SCX_UNUSED off
+ wire _unused_ok = &{1'b0,
+
+ bp_select,
+
+ bp3_hold_wait_vector,
+ bp2_hold_wait_vector_d1,
+ bp1_hold_wait_vector_d1,
+
+ bp3_header,
+ bp3_header_d1,
+ bp3_select,
+ bp3_select_d1,
+ bp3_next_winner[1:0],
+ bp3_next_winner_d1[1:0],
+ bp3_nextxbe[3:0],
+ bp3_nextxbe_d1[3:0],
+
+
+ bp2_grant_cycle_d2,
+ bp2_header,
+ bp2_header_d2,
+ bp2_select,
+ bp2_select_d2,
+ bp2_next_winner[1:0],
+ bp2_next_winner_d2[1:0],
+ bp2_nextxbe[3:0],
+ bp2_nextxbe_d2[3:0],
+
+ bp1_header_d1,
+ bp1_header_d2,
+ bp1_select_d1,
+ bp1_select_d2,
+ bp1_next_winner_d1[1:0],
+ bp1_next_winner_d2[1:0],
+ bp1_nextxbe_d1[3:0],
+ bp1_nextxbe_d2[3:0],
+
+ xb0_obx_NextXbe_s3a, // This is unused signal now.
+ xb1_obx_NextXbe_s3a,
+ xb2_obx_NextXbe_s3a,
+ xb3_obx_NextXbe_s3a,
+
+ syn64,
+ dataout64,
+
+ 1'b0
+ };
+ // lint_checking SCX_UNUSED on
+
+
+endmodule
+
+module FswBypassArbiter (/*AUTOARG*/) ;
+
+ input lreset_l;
+ input sclk;
+ input bp_arb_enable;
+ output bp_grant3;
+ output bp_grant2;
+ output bp_grant1;
+ output bp_grant0;
+ output bp_grant_cycle;
+ output bp_grant_cycle_d1;
+ output bp_grant_cycle_d2;
+ output [1:0] bp_next_winner;
+ output [1:0] bp_next_winner_d1;
+ output [1:0] bp_next_winner_d2;
+ output [3:0] bp_nextxbe;
+ output [3:0] bp_nextxbe_d1;
+ output [3:0] bp_nextxbe_d2;
+ output [5:0] bp_hold_wait_vector;
+ output [5:0] bp_hold_wait_vector_d1;
+ output bp_header;
+ output bp_header_d1;
+ output bp_header_d2;
+ output bp_select;
+ output bp_select_d1;
+ output bp_select_d2;
+ input sop3;
+ input [63:0] sop3_data;
+ input [5:0] sop3_bpcontext;
+ input sop2;
+ input [63:0] sop2_data;
+ input [5:0] sop2_bpcontext;
+ input sop1;
+ input [63:0] sop1_data;
+ input [5:0] sop1_bpcontext;
+ input sop0;
+ input [63:0] sop0_data;
+ input [5:0] sop0_bpcontext;
+ input [15:0] poolmask;
+ input [63:0] bufbusy_mask;
+endmodule
diff --git a/tests/autowire_import_bug317.v b/tests/autowire_import_bug317.v
new file mode 100644
index 0000000..337087e
--- /dev/null
+++ b/tests/autowire_import_bug317.v
@@ -0,0 +1,30 @@
+package pkg;
+ typedef logic [1:0] my_type;
+endpackage
+
+module top;
+ import pkg::*;
+ /*AUTOWIRE*/
+ sub_1 sub_1 (.*);
+ sub_2 sub_2 (.*);
+endmodule
+
+module sub_1
+ import pkg::*; // bug317
+ (
+ input pkg::my_type_t a,
+ output pkg::my_type_t z
+ );
+endmodule
+
+module sub_2
+ (
+ input pkg::my_type_t z,
+ output pkg::my_type_t a
+ );
+endmodule
+
+// Local Variables:
+// verilog-typedef-regexp: "_t$"
+// verilog-auto-star-save: t
+// End:
diff --git a/tests/autowire_isaacson.v b/tests/autowire_isaacson.v
new file mode 100644
index 0000000..5744e55
--- /dev/null
+++ b/tests/autowire_isaacson.v
@@ -0,0 +1,44 @@
+module t;
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire w11; // From bp3 of FswBypassArbiter.v
+ wire w12; // From bp3 of FswBypassArbiter.v
+ // End of automatics
+ /*AUTOREG*/
+
+ wand w0;
+ wor w1;
+ tri0 w2;
+ tri1 w3;
+ triand w4;
+ trior w5;
+ trireg w6;
+ tri w7;
+ wire w8;
+ supply0 w9;
+ supply1 w10;
+
+ FswBypassArbiter bp3 (/*AUTOINST*/
+ // Outputs
+ .w0 (w0),
+ .w1 (w1),
+ .w2 (w2),
+ .w3 (w3),
+ .w4 (w4),
+ .w5 (w5),
+ .w6 (w6),
+ .w7 (w7),
+ .w8 (w8),
+ .w9 (w9),
+ .w10 (w10),
+ .w11 (w11),
+ .w12 (w12));
+
+endmodule
+
+module FswBypassArbiter (/*AUTOARG*/
+ // Outputs
+ w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12
+ ) ;
+ output w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12;
+endmodule
diff --git a/tests/autowire_long_yaohung.v b/tests/autowire_long_yaohung.v
new file mode 100644
index 0000000..bac7986
--- /dev/null
+++ b/tests/autowire_long_yaohung.v
@@ -0,0 +1,16 @@
+module autowire_long_yaohung(/*AUTOARG*/);
+
+ /*AUTOOUTPUT*/
+ /*AUTOWIRE*/
+ /*AUTOREG*/
+
+ top top
+ (/*AUTOINST*/);
+
+endmodule
+
+module top(/*AUTOARG*/);
+
+ output [`LONGNAMELONGNAMELONGNAMELONGNAMELONGNAMELONGNAME] data_out;
+
+endmodule
diff --git a/tests/autowire_lovell_hiear.v b/tests/autowire_lovell_hiear.v
new file mode 100644
index 0000000..81c2408
--- /dev/null
+++ b/tests/autowire_lovell_hiear.v
@@ -0,0 +1,32 @@
+module foo
+ (/*AUTOARG*/
+ // Outputs
+ another_output2
+ );
+
+ /*AUTOOUTPUTEVERY*/
+ // Beginning of automatic outputs (every signal)
+ output [1:0] another_output2; // From inst of autoinst_signed_fubar2.v
+ // End of automatics
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [1:0] another_output2; // From inst of autoinst_signed_fubar2.v
+ // End of automatics
+
+
+ /* autoinst_signed_fubar2 AUTO_TEMPLATE (
+ .an_output2 (hi.ear.ial),
+ );
+ */
+
+ autoinst_signed_fubar2 inst
+ (
+ /*AUTOINST*/
+ // Outputs
+ .an_output2 (hi.ear.ial), // Templated
+ .another_output2 (another_output2[1:0]),
+ // Inputs
+ .an_input2 (an_input2[1:0]));
+
+endmodule
diff --git a/tests/autowire_merge_bug303.v b/tests/autowire_merge_bug303.v
new file mode 100644
index 0000000..efb14d3
--- /dev/null
+++ b/tests/autowire_merge_bug303.v
@@ -0,0 +1,48 @@
+module TOP (/*AUTOARG*/
+ // Outputs
+ SIG_NAMEB, SIG_NAMEA
+ )
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [223:0] SIG_NAMEA; // From A of A.v, ...
+ output [FOO*2:0] SIG_NAMEB; // From C of C.v
+ // End of automatics
+ /*AUTOINPUT*/
+ /*AUTOWIRE*/
+
+ A A(/*AUTOINST*/
+ // Outputs
+ .SIG_NAMEA (SIG_NAMEA[224*1-1:128*1]));
+ B B(/*AUTOINST*/
+ // Outputs
+ .SIG_NAMEA (SIG_NAMEA[127:0]));
+ C C(/*AUTOINST*/
+ // Outputs
+ .SIG_NAMEB (SIG_NAMEB[FOO*4-2*1:0]));
+endmodule
+
+module A(/*AUTOARG*/
+ // Outputs
+ SIG_NAMEA
+ );
+ output [224*1-1:128*1] SIG_NAMEA;
+ //output [223:128] SIG_NAMEA;
+endmodule
+
+
+module B(/*AUTOARG*/
+ // Outputs
+ SIG_NAMEA
+ );
+ output [127:0] SIG_NAMEA;
+endmodule
+
+
+module C(/*AUTOARG*/
+ // Outputs
+ SIG_NAMEB
+ );
+ output [FOO*4-2*1:0] SIG_NAMEB;
+endmodule
+
+
diff --git a/tests/autowire_misalias_bug295.v b/tests/autowire_misalias_bug295.v
new file mode 100644
index 0000000..cd388f9
--- /dev/null
+++ b/tests/autowire_misalias_bug295.v
@@ -0,0 +1,21 @@
+interface my_interface ();
+ logic [2:0] out2;
+ logic [2:0] out3;
+endinterface: my_interface
+
+module foobar (input [2:0] in2, output [2:0] out2);
+endmodule
+
+module foo_autowire_fails (my_interface itf);
+ /*AUTOWIRE*/
+ assign itf.out2 = out2; // perhaps a namespace collision?
+ foobar foobar0
+ (/*AUTOINST*/);
+endmodule
+
+module foo_autowire_works (my_interface itf);
+ /*AUTOWIRE*/
+ assign itf.out3 = out2;
+ foobar foobar0
+ (/*AUTOINST*/);
+endmodule
diff --git a/tests/autowire_myers.v b/tests/autowire_myers.v
new file mode 100644
index 0000000..618fa92
--- /dev/null
+++ b/tests/autowire_myers.v
@@ -0,0 +1,18 @@
+module test1 ( wireA, wireB );
+ output [3:0] wireA;
+ output [16:0] wireB;
+endmodule
+
+module test_top;
+
+ /*AUTOWIRE*/
+
+ generate
+ if (1) begin
+ test1 t1 (/*AUTOINST*/);
+ end
+ else begin
+ assign wireA = 0;
+ end
+ endgenerate
+endmodule
diff --git a/tests/autowire_nocomment.v b/tests/autowire_nocomment.v
new file mode 100644
index 0000000..4cf35b6
--- /dev/null
+++ b/tests/autowire_nocomment.v
@@ -0,0 +1,37 @@
+module top;
+
+ /*AUTOOUTPUTEVERY*/
+ // Beginning of automatic outputs (every signal)
+ output logic out1a;
+ output logic [1:0] out1b;
+ // End of automatics
+ /*AUTOREG*/
+
+ /*AUTOLOGIC*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic out1a;
+ logic [1:0] out1b;
+ // End of automatics
+
+
+ sub2 isub2 (/*AUTOINST*/
+ // Outputs
+ .out1a (out1a),
+ .out1b (out1b[1:0]),
+ // Inputs
+ .in1a (in1a),
+ .in1b (in1b));
+
+endmodule
+
+module sub2
+ ( input logic in1a,
+ input logic in1b,
+ output logic out1a,
+ output logic [1:0] out1b
+ );
+endmodule
+
+// Local Variables:
+// verilog-auto-wire-comment: nil
+// End:
diff --git a/tests/autowire_paramvec_bug302.v b/tests/autowire_paramvec_bug302.v
new file mode 100644
index 0000000..bca36da
--- /dev/null
+++ b/tests/autowire_paramvec_bug302.v
@@ -0,0 +1,49 @@
+module Abc_TEST ();
+
+/*AUTOWIRE*/
+
+ Abc #(
+ .No1 (6),
+ /*AUTOINSTPARAM*/) u_Abc
+ (
+ /*AUTOINST*/);
+
+ Def #(
+ .No1 (6)) u_Def
+ (
+ // Outputs
+ .ck (ck),
+ /*AUTOINST*/);
+
+endmodule
+
+
+module Abc
+ #(
+ parameter No1 = 6,
+ parameter int unsigned No2 // Parameter no. 2
+ = pa_Abc::No2,
+ parameter bit No3 [No1:0][No2-1:0] // Parameter no. 3
+ = pa_Abc::No3
+ )
+ (
+ input logic ck,
+ input logic [No1-1:0][31:0] abc
+ input logic [No1-1:0][31:0] abc
+ );
+endmodule
+
+module Def
+ #(
+ parameter No1 = 6
+ )
+ (
+ input logic ck,
+ output logic [No1-1:0][31:0] abc
+ );
+endmodule
+
+// Local Variables:
+// verilog-library-extensions:(".v" ".sv")
+// verilog-auto-inst-param-value:t
+// End:
diff --git a/tests/autowire_pkg_bug195.v b/tests/autowire_pkg_bug195.v
new file mode 100644
index 0000000..df3f7c7
--- /dev/null
+++ b/tests/autowire_pkg_bug195.v
@@ -0,0 +1,56 @@
+`default_nettype none
+
+package testcase_pkg;
+
+ typedef int unsigned uint;
+
+ localparam uint SIZE = 8;
+
+ typedef enum {ENUM1, ENUM2} enum_t;
+
+endpackage
+
+module testcase_top
+ (
+ input testcase_pkg::enum_t top_enum,
+ input logic [testcase_pkg::SIZE-1:0] top_in,
+ output logic [testcase_pkg::SIZE-1:0] top_out
+ );
+ import testcase_pkg::*;
+ //enum_t sub_enum; // is not declared by AUTOWIRE
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ testcase_pkg::enum_t sub_enum; // From testcase_sub1 of testcase_sub1.v
+ wire [testcase_pkg::SIZE-1:0] sub_in; // From testcase_sub1 of testcase_sub1.v
+ wire [testcase_pkg::SIZE-1:0] sub_out; // From testcase_sub2 of testcase_sub2.v
+ // End of automatics
+ assign top_out = sub_out;
+ testcase_sub1 testcase_sub1 (.*);
+ testcase_sub2 testcase_sub2 (.*);
+endmodule
+
+module testcase_sub1
+ (
+ input testcase_pkg::enum_t top_enum,
+ output testcase_pkg::enum_t sub_enum,
+ output logic [testcase_pkg::SIZE-1:0] sub_in
+ );
+ import testcase_pkg::*;
+ assign sub_enum = top_enum;
+ assign sub_in = '1;
+endmodule
+
+module testcase_sub2
+ (
+ input testcase_pkg::enum_t sub_enum,
+ input logic [testcase_pkg::SIZE-1:0] sub_in,
+ output logic [testcase_pkg::SIZE-1:0] sub_out
+ );
+ import testcase_pkg::*;
+ assign sub_out = (sub_enum==ENUM1) ? ~sub_in : sub_in;
+endmodule
+
+// Local Variables:
+// verilog-typedef-regexp: "_t$"
+// verilog-auto-star-save: t
+// End:
diff --git a/tests/autowire_real.v b/tests/autowire_real.v
new file mode 100644
index 0000000..addf74f
--- /dev/null
+++ b/tests/autowire_real.v
@@ -0,0 +1,29 @@
+module sc_top (
+ input var real Tx_vcm,
+ input var real i_DAC_in,
+ input i_Tx_SC_en,
+ output var real Tx_vsc
+);
+
+endmodule
+
+
+module cm_top (
+ input i_Tx_CM_en,
+ output var real Tx_vcm
+);
+
+endmodule
+
+module top (
+/*AUTOOUTPUT*/
+/*AUTOINPUT*/
+);
+
+/*AUTOWIRE*/
+
+cm_top cm_buf (/*AUTOINST*/);
+
+sc_top sc_buf (/*AUTOINST*/);
+
+endmodule
diff --git a/tests/autowire_req.v b/tests/autowire_req.v
new file mode 100644
index 0000000..299e8cd
--- /dev/null
+++ b/tests/autowire_req.v
@@ -0,0 +1,20 @@
+
+module autowire_req ();
+
+reqcmd_t AReq;
+reqcmd_t BReq;
+
+/*AUTOWIRE*/
+
+autowire_req_sw autowire_req_sw (/*AUTOINST*/
+ // Outputs
+ .BReq (BReq),
+ // Inputs
+ .AReq (AReq));
+
+endmodule
+
+// Local Variables:
+// verilog-library-directories:(".")
+// verilog-typedef-regexp:"_t$"
+// End:
diff --git a/tests/autowire_req_sw.v b/tests/autowire_req_sw.v
new file mode 100644
index 0000000..73302b1
--- /dev/null
+++ b/tests/autowire_req_sw.v
@@ -0,0 +1,19 @@
+`include "pf_sc.vh"
+
+module autowire_req_sw
+(
+ input reqcmd_t AReq,
+ output reqcmd_t BReq
+/*AUTOINPUT*/
+);
+
+assign Bnk0Req = Cpu0Req;
+
+
+endmodule
+
+
+// Local Variables:
+// verilog-library-directories:(".")
+// verilog-typedef-regexp:"_t$"
+// End:
diff --git a/tests/autowire_thon_selects.v b/tests/autowire_thon_selects.v
new file mode 100644
index 0000000..196e0cd
--- /dev/null
+++ b/tests/autowire_thon_selects.v
@@ -0,0 +1,29 @@
+module foo
+ (/*AUTOARG*/);
+
+ /*AUTOOUTPUTEVERY*/
+
+ /*AUTOWIRE*/
+
+
+ // Check that if aa is connected differently in a input, it doesn't make conflicts.
+
+ autoinst_signed_fubar2 inst
+ (
+ // Outputs
+ .an_output2 (hi.ear.ial),
+ .another_output2 (aa[FOO:0]),
+ // Inputs
+ .an_input2 (an_input2[1:0])
+ /*AUTOINST*/);
+
+ autoinst_signed_fubar2 instx
+ (
+ // Outputs
+ .an_output2 (hi.ear.ial),
+ // Inputs
+ .an_input2 (an_input2[1:0]),
+ .another_output2 (aa[Y:X]),
+ /*AUTOINST*/);
+
+endmodule
diff --git a/tests/autowire_totte.v b/tests/autowire_totte.v
new file mode 100644
index 0000000..0bea859
--- /dev/null
+++ b/tests/autowire_totte.v
@@ -0,0 +1,41 @@
+module test1 ( wire2, wire4 );
+ output [3:0] wire2;
+ output [16:0] wire4;
+endmodule
+
+module test2 ( wire6, wire12 );
+ input [3:0] wire6;
+ input [16:0] wire12;
+endmodule
+
+module test3 ( wireA, wireB );
+ input [3:0] wireA;
+ input [16:0] wireB;
+endmodule
+
+module test4 ( wireA, wireB );
+ output [3:0] wireA;
+ output [16:0] wireB;
+endmodule
+
+module test_top;
+
+ /*AUTOWIRE*/
+
+ /* test1 AUTO_TEMPLATE (
+ .wire@(wire_\1_to_@"(* \1 3)"[]),
+ ); */
+
+ test1 t1 (/*AUTOINST*/);
+
+ /* test2 AUTO_TEMPLATE (
+ .wire@(wire@"(/ \1 3)"_to_\1[]),
+ ); */
+
+ test2 t2 (/*AUTOINST*/);
+
+ test3 t3 (/*AUTOINST*/);
+
+ test4 t4 (/*AUTOINST*/);
+
+endmodule
diff --git a/tests/batch_li_child.v b/tests/batch_li_child.v
new file mode 100644
index 0000000..731bee4
--- /dev/null
+++ b/tests/batch_li_child.v
@@ -0,0 +1,27 @@
+module batch_li_child
+#(parameter
+
+ WIDTH_0= 'h8,
+ WIDTH_1 = 'h4
+ )
+(
+ input rst,
+ input clk
+ );
+
+ reg [WIDTH_0-1:0] counter_0;
+ reg [WIDTH_1-1:0] counter_1;
+
+ always @(posedge clk) begin
+ if (rst) begin
+ counter_0 <= #1 0;
+ counter_1 <= #1 0;
+ end
+ else begin
+ counter_0 <= #1 counter_0 + 1'b1;
+ counter_1 <= #1 counter_1 + 1'b1;
+ end
+ end
+
+endmodule
+
diff --git a/tests/batch_li_parent.v b/tests/batch_li_parent.v
new file mode 100644
index 0000000..feba72d
--- /dev/null
+++ b/tests/batch_li_parent.v
@@ -0,0 +1,19 @@
+module batch_li_parent (/*AUTOARG*/);
+
+ input rst;
+ input clk;
+
+ parameter WIDTH_0 = 8;
+ parameter WIDTH_1 = 16;
+
+ batch_li_child
+ #(.WIDTH_1 (WIDTH_0),
+ .WIDTH_0 (WIDTH_1))
+ child
+ (/*AUTOINST*/);
+
+endmodule
+
+// Local Variables:
+// verilog-auto-arg-sort: t
+// End:
diff --git a/tests/batch_prof_cell.v b/tests/batch_prof_cell.v
new file mode 100755
index 0000000..b96441a
--- /dev/null
+++ b/tests/batch_prof_cell.v
@@ -0,0 +1,4 @@
+module batch_prof_cell(Z,A,B);
+ output Z;
+ input A, B;
+endmodule
diff --git a/tests/carlson.v b/tests/carlson.v
new file mode 100644
index 0000000..347e1a6
--- /dev/null
+++ b/tests/carlson.v
@@ -0,0 +1,19 @@
+module x ();
+ always @ (/*AUTOSENSE*/bus or in1 or in2 or reset) begin
+ out4 = | bus;
+
+ out7 = 1'b0; // pre-initialize output of case so default not needed
+ case (bus[1:0])
+ 2'b00: out7 = in1;
+ 2'b01: out7 = in2;
+ 2'b10: out7 = reset;
+`ifdef BEH
+ default: begin
+ out7 = 1'bX; // force VCS simulation to propagate X's from the bus signal
+ $display ("\n Error, in module temp, bus[1:0] illegal value of 11\n");
+ end
+`endif
+
+ endcase // case(bus[1:0])
+ end
+endmodule
diff --git a/tests/case_question.v b/tests/case_question.v
new file mode 100644
index 0000000..41bfbde
--- /dev/null
+++ b/tests/case_question.v
@@ -0,0 +1,16 @@
+module test ();
+
+ always @(/*AUTOSENSE*/xyz)
+ begin
+ casex (xyz)
+ 4'b???0: r = 1;
+ 4'b??01: r = 2;
+ 4'b?001: r = 3;
+ default: r = 4;
+ endcase
+ end
+
+ assign x = y;
+
+endmodule
+
diff --git a/tests/comment_strip.v b/tests/comment_strip.v
new file mode 100644
index 0000000..e9e7181
--- /dev/null
+++ b/tests/comment_strip.v
@@ -0,0 +1,25 @@
+module foo;
+ initial begin
+ /* The function verilog-strip-comments should not change this line:*/
+ $display("INFO :[PIPE LINK %d]: ///////////////////////////////////////////",PIPE_LINK);
+
+ // to this:
+ $display("INFO :[PIPE LINK %d]: ");
+
+ /* The function verilog-strip-comments should not change this line:*/
+ $display("INFO :[PIPE LINK %d]: /* ",PIPE_LINK); /* This comment should go away */
+ // to this:
+ $display("INFO :[PIPE LINK %d]: ");
+
+ /* also this comment should not get eaten
+ because of use of slashes // and such like
+ */
+ /*
+ ugly hidded end comment // */
+ $display("don't forget me agentina");
+ // another hidden comment /*
+ /**/
+
+ end
+
+endmodule // foo
diff --git a/tests/debug.v b/tests/debug.v
new file mode 100644
index 0000000..0b79ffd
--- /dev/null
+++ b/tests/debug.v
@@ -0,0 +1,15 @@
+`include "some_macros.v"
+
+module z();
+
+ $display("%t:", $time);
+ a = b;
+ casfasdf = d;
+ g = r;
+ fgasdfasdfasdfasfdasfd <= p;
+ gh := h;
+ gf <=g;
+ ssdf = 5;
+ f = zsfdsdf >= f;
+
+endmodule
diff --git a/tests/disable.v b/tests/disable.v
new file mode 100644
index 0000000..cc31d34
--- /dev/null
+++ b/tests/disable.v
@@ -0,0 +1,27 @@
+module foo;
+ task my_task;
+ begin :body_my_task
+ fork
+ join
+ case (a)
+ endcase // case endcase
+ if (a) begin
+ end
+ begin
+ end
+ fork : main_fork
+ begin : body_main_fork
+ fork : sub_fork
+ begin
+ // st1
+ end
+ begin
+ // st2
+ end
+ join_any // first wins
+ a = b;
+ disable fork; // kill others
+ end // block: body_main_fork
+ end // block: body_main_fork
+ endtask // my_task
+endmodule // foo
diff --git a/tests/escape_a.v b/tests/escape_a.v
new file mode 100644
index 0000000..9d4cd61
--- /dev/null
+++ b/tests/escape_a.v
@@ -0,0 +1,14 @@
+module escape_a (/*AUTOARG*/
+ // Outputs
+ \o[10] , \o[2] ,
+ // Inputs
+ \i&e;
+ );
+ output \o[10] ;
+ output \o[2] ;
+ input \i&e; ;
+
+ wire \o[10] = \i&e; ;
+ wire \o[2] = \i&e; ;
+
+endmodule
diff --git a/tests/escape_top.v b/tests/escape_top.v
new file mode 100644
index 0000000..1a16a33
--- /dev/null
+++ b/tests/escape_top.v
@@ -0,0 +1,29 @@
+module escape_top (/*AUTOARG*/
+ // Outputs
+ \oren10 , \o[2] ,
+ // Inputs
+ \i&e;
+ );
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input \i&e; ; // To a of escape_a.v
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output \o[2] ; // From a of escape_a.v
+ output \oren10 ; // From a of escape_a.v
+ // End of automatics
+
+ /* escape_a AUTO_TEMPLATE(
+ .\(.*o.*10.*\) (\\oren10 ),
+ ); */
+
+ escape_a a (/*AUTOINST*/
+ // Outputs
+ .\o[10] (\oren10 ), // Templated
+ .\o[2] (\o[2] ),
+ // Inputs
+ .\i&e; (\i&e; ));
+
+endmodule
diff --git a/tests/example.v b/tests/example.v
new file mode 100644
index 0000000..a96634e
--- /dev/null
+++ b/tests/example.v
@@ -0,0 +1,33 @@
+module example (/*AUTOARG*/
+ // Outputs
+ lower_out, o,
+ // Inputs
+ lower_inb, lower_ina, i
+ );
+ input i;
+ output o;
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input lower_ina; // To inst of inst.v
+ input lower_inb; // To inst of inst.v
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output lower_out; // From inst of inst.v
+ // End of automatics
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg o;
+ // End of automatics
+ inst inst (/*AUTOINST*/
+ // Outputs
+ .lower_out (lower_out),
+ // Inputs
+ .lower_inb (lower_inb),
+ .lower_ina (lower_ina));
+ always @ (/*AUTOSENSE*/i) begin
+ o = i;
+ end
+endmodule
+
+
diff --git a/tests/flag_f_reeves.v b/tests/flag_f_reeves.v
new file mode 100644
index 0000000..fa3c3e0
--- /dev/null
+++ b/tests/flag_f_reeves.v
@@ -0,0 +1,15 @@
+
+module flag_f_reeves
+ (/*AUTOARG*/) ;
+
+ /*AUTOOUTPUT*/
+
+ /*AUTOINPUT*/
+
+ flag_f_reeves_IBUF ibuf
+ (/*AUTOINST*/);
+
+endmodule
+// Local Variables:
+// verilog-library-flags: ("-f flag_f_reeves.vc")
+// End:
diff --git a/tests/flag_f_reeves.vc b/tests/flag_f_reeves.vc
new file mode 100644
index 0000000..b62fcce
--- /dev/null
+++ b/tests/flag_f_reeves.vc
@@ -0,0 +1 @@
+-y subdir
diff --git a/tests/for.v b/tests/for.v
new file mode 100644
index 0000000..83c73a3
--- /dev/null
+++ b/tests/for.v
@@ -0,0 +1,28 @@
+module lbm
+ (/*AUTOARG*/
+ // Outputs
+ outgo,
+ // Inputs
+ income
+ );
+
+ input [1:0] income;
+ output [1:0] outgo;
+ reg [1:0] outgo;
+
+ integer i;
+ always @ (/*AUTOSENSE*/income) begin
+ for (i=0; i<32; i=i+1) begin
+ outgo[i] = income[i];
+ end
+ end
+
+ always @ (/*AUTOSENSE*/income) begin
+ if (|income) begin
+ $display("[0%10t] %I-for.v: found %s \"quote\" ",
+ $time, ((|income)?"in":"out"));
+
+ end
+ end
+
+endmodule
diff --git a/tests/gorfajn.v b/tests/gorfajn.v
new file mode 100644
index 0000000..1540832
--- /dev/null
+++ b/tests/gorfajn.v
@@ -0,0 +1,12 @@
+module x;
+ always @(/*autosense*/d32S_CurCcbH or ramS_CcbBaseH or ramS_ccbsizeH)
+ begin
+ case (ramS_ccbsizeH)
+ 2'b00 : ramS_CcbAddH = {2'b00, d32S_CurCcbH };
+ 2'b01 : ramS_CcbAddH = {1'b0, d32S_CurCcbH, 1'b0};
+ 2'b10 : ramS_CcbAddH = {d32S_CurCcbH, 2'b00};
+ 2'b11 : ramS_CcbAddH = {d32S_CurCcbH, 2'b00}; // unused
+ endcase
+ ramS_CcbAddresH = {10'h000, ramS_CcbAddH} + ramS_CcbBaseH;
+ end
+endmodule
diff --git a/tests/grisamore_twoinone.v b/tests/grisamore_twoinone.v
new file mode 100644
index 0000000..ac73e3f
--- /dev/null
+++ b/tests/grisamore_twoinone.v
@@ -0,0 +1,56 @@
+module foo (/*AUTOARG*/
+ // Outputs
+ d,
+ // Inputs
+ b, a
+ );
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input a; // To foo2 of foo2.v
+ input b; // To foo2 of foo2.v
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output d; // From foo2 of foo2.v
+ // End of automatics
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ // End of automatics
+ /*AUTOREGINPUT*/
+ // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+ // End of automatics
+ foo2 foo2 (/*AUTOINST*/
+ // Outputs
+ .d (d),
+ // Inputs
+ .a (a),
+ .b (b));
+
+endmodule
+
+
+module foo2 (/*AUTOARG*/
+ // Outputs
+ d,
+ // Inputs
+ a, b
+ );
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ // End of automatics
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ // End of automatics
+ /*AUTOREGINPUT*/
+ // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+ // End of automatics
+ input a;
+ input b;
+ output d;
+
+ //{ Behavioral verilog code here}
+endmodule
+
diff --git a/tests/hangcase.v b/tests/hangcase.v
new file mode 100644
index 0000000..d66783a
--- /dev/null
+++ b/tests/hangcase.v
@@ -0,0 +1,59 @@
+// See Line 54
+
+module hangcase (/*AUTOARG*/);
+
+ //
+ assign w_rdat_ena = ({16{foo[ 0]}} & bar ) |
+ ({16{foo[ 1]}} & bar ) |
+ ({16{foo[ 2]}} & bar ) |
+ ({16{foo[ 3]}} & bar ) |
+ ({16{foo[ 4]}} & bar ) |
+ ({16{foo[ 5]}} & bar ) |
+ ({16{foo[ 6]}} & bar ) |
+ ({16{foo[ 7]}} & bar ) |
+ ({16{foo[ 8]}} & bar ) |
+ ({16{foo[ 9]}} & bar ) |
+ ({16{foo[10]}} & bar ) |
+ ({16{foo[11]}} & bar ) |
+ ({16{foo[12]}} & bar ) |
+ ({16{foo[13]}} & bar ) |
+ ({16{foo[14]}} & bar ) |
+ ({16{foo[15]}} & bar ) ;
+
+ //
+ assign w_rdat_mrk = ({16{foo[ 0]}} & bar & baz ) |
+ ({16{foo[ 1]}} & bar & baz ) |
+ ({16{foo[ 2]}} & bar & baz ) |
+ ({16{foo[ 3]}} & bar & baz ) |
+ ({16{foo[ 4]}} & bar & baz ) |
+ ({16{foo[ 5]}} & bar & baz ) |
+ ({16{foo[ 6]}} & bar & baz ) |
+ ({16{foo[ 7]}} & bar & baz ) |
+ ({16{foo[ 8]}} & bar & baz ) |
+ ({16{foo[ 9]}} & bar & baz ) |
+ ({16{foo[10]}} & bar & baz ) |
+ ({16{foo[11]}} & bar & baz ) |
+ ({16{foo[12]}} & bar & baz ) |
+ ({16{foo[13]}} & bar & baz ) |
+ ({16{foo[14]}} & bar & baz ) |
+ ({16{foo[15]}} & bar & baz ) ;
+
+ //
+ assign w_wdat_ena_set = ({16{ena_set}} & col_dec );
+ assign w_wdat_ena_clr = ({16{ena_clr}} & col_dec );
+ assign w_wdat_mrk_set = ({16{mrk_set}} & w_rdat_ena );
+ assign w_wdat_mrk_clr = ({16{mrk_clr}} & col_dec );
+ assign w_wdat_ena = (w_rdat_ena & ~w_wdat_ena_clr) | w_wdat_ena_set;
+ assign w_wdat_mrk = (w_rdat_mrk & ~w_wdat_mrk_clr) | w_wdat_mrk_set;
+
+ //
+ assign w_dat15_ena = foo[15] ? w_wdat_ena : bar;
+
+ //
+ assign w_dat15_mrk = foo[15] ? w_wdat_mrk : baz;
+
+ //^^^^ FIX NEWLINE ABOVE HERE
+ //
+ assign w_timeout_mrk = row_check ? w_wdat_mrk : r_timeout_mrk;
+
+endmodule
diff --git a/tests/indent_1.v b/tests/indent_1.v
new file mode 100644
index 0000000..0b9432e
--- /dev/null
+++ b/tests/indent_1.v
@@ -0,0 +1,6 @@
+module foo(reg_input_signal_name);
+ input a;
+ input reg_input_signal_name;
+
+endmodule // foo
+
diff --git a/tests/indent_2.v b/tests/indent_2.v
new file mode 100644
index 0000000..98793ba
--- /dev/null
+++ b/tests/indent_2.v
@@ -0,0 +1,18 @@
+module foo(reg_input_signal_name,a,b,c,d,e);
+ // foo bar
+ output c;//this is a comment
+
+
+ reg foo;
+ //a
+
+ /* jj
+ KK */
+reg foo;
+ output reg /* */ signed d;
+output reg signed e; /* so is this */
+
+ reg [31:0] blather;
+
+endmodule // foo
+
diff --git a/tests/indent_3.v b/tests/indent_3.v
new file mode 100644
index 0000000..7fbdcd5
--- /dev/null
+++ b/tests/indent_3.v
@@ -0,0 +1,7 @@
+module junk (/*AUTOARG*/) ;
+ input a_junk;
+ input wire signed [15:0] b_junk;
+ output c_junk;
+ output [15:0][31:0][1024:(`REALLY_BIG_NAME-1)] d_junk;
+endmodule // junk
+
diff --git a/tests/indent_4.v b/tests/indent_4.v
new file mode 100644
index 0000000..521750f
--- /dev/null
+++ b/tests/indent_4.v
@@ -0,0 +1,22 @@
+module foo;
+ initial
+ begin
+ s1;
+ end
+
+ always @(a)
+ begin
+ s1;
+ end // always @ (a)
+ always
+ begin
+ s1;
+ end // always begin
+ always_ff
+ begin
+ end // always_ff begin
+ task
+ t;
+ endtask // t
+
+endmodule // foo
diff --git a/tests/indent_always_decl.v b/tests/indent_always_decl.v
new file mode 100644
index 0000000..c63882d
--- /dev/null
+++ b/tests/indent_always_decl.v
@@ -0,0 +1,34 @@
+module foo ();
+ // Before the always block,
+ // indents to here: (which I like)
+ // V
+ wire [10:0] mux_output0 =
+ select0[0] ? mux_input0 :
+ select0[1] ? mux_input1 :
+ select0[2] ? mux_input2 :
+ select0[3] ? mux_input3 :
+ select0[4] ? mux_input4 :
+ select0[5] ? mux_input5 :
+ select0[6] ? mux_input6 :
+ mux_input7;
+
+ reg foobar;
+ always @(posedge clk)
+ if (reset_n) begin
+ foobar <= 1'b0;
+ end
+
+ // After the always block,
+ // indents to here:
+ // V
+ wire [10:0] mux_output1 =
+ select1[0] ? mux_input8 :
+ select1[1] ? mux_input9 :
+ select1[2] ? mux_input10 :
+ select1[3] ? mux_input11 :
+ select1[4] ? mux_input12 :
+ select1[5] ? mux_input13 :
+ select1[6] ? mux_input14 :
+ mux_input15;
+endmodule
+
diff --git a/tests/indent_assert.v b/tests/indent_assert.v
new file mode 100644
index 0000000..6be93da
--- /dev/null
+++ b/tests/indent_assert.v
@@ -0,0 +1,7 @@
+module assert_test;
+ reg [31:0] whatever2;
+ initial begin
+ a = b;
+ assert(std::randomize(whatever2) with { whatever2 inside {[10:100]};});
+ end
+endmodule // assert_test
diff --git a/tests/indent_assert_else.v b/tests/indent_assert_else.v
new file mode 100644
index 0000000..04552aa
--- /dev/null
+++ b/tests/indent_assert_else.v
@@ -0,0 +1,50 @@
+module myassert(input clk,
+ input reset,
+ input [15:0] data);
+
+ property myproperty;
+ @(posedge clk)
+ $rose(reset) |-> data == 16'h0;
+ endproperty
+
+ //Assert, cover, and assume property statements
+ //support begin/end keywords. The else begin/end
+ //clause below is getting indented improperly.
+ myassert0: assert property(myproperty) begin
+ $display("myassert0 was successful");
+ a;
+ b;
+ c;
+ d;
+ end // myassert0: assert property (myproperty)
+ else begin
+ $fatal("myassert0 was unsuccessful");
+ end // else: !assert property(myproperty)
+ if (a) begin
+ b;
+ c;
+ end // if (a)
+ else begin
+ o;
+ end // else: !if(a)
+ assert (a) begin
+ o;
+ end // assert (a)
+ else begin
+ o;
+ end // else: !assert (a)
+
+ assert (statement) begin
+ $display("assertion passed"); //this code is correctly indented
+ end // assert (statement)
+ else begin // this whole section should be moved to the left
+ $error("assertion failed");
+ end // else: !assert (statement)
+
+ //Also, any statements following the assert,
+ //cover, and assume property statements get
+ // indented too far to the right.
+ always @(posedge clk) begin
+ a;
+ end // always @ (posedge clk)
+endmodule
diff --git a/tests/indent_assert_property.v b/tests/indent_assert_property.v
new file mode 100644
index 0000000..fd435bc
--- /dev/null
+++ b/tests/indent_assert_property.v
@@ -0,0 +1,25 @@
+module myassert(input clk,
+ input reset,
+ input [15:0] data);
+
+ property myproperty;
+ @(posedge clk)
+ $rose(reset) |-> data == 16'h0;
+ endproperty
+
+ //Assert, cover, and assume property statements
+ //support begin/end keywords. The else begin/end
+ //clause below is getting indented improperly.
+ myassert0: assert property(myproperty) begin
+ $display("myassert0 was successful");
+ end
+else begin
+ $fatal("myassert0 was unsuccessful");
+end
+
+ //Also, any statements following the assert,
+ //cover, and assume property statements get
+ // indented too far to the right.
+ always @(posedge clk) begin
+ end
+endmodule
diff --git a/tests/indent_assignment.v b/tests/indent_assignment.v
new file mode 100644
index 0000000..06b4c08
--- /dev/null
+++ b/tests/indent_assignment.v
@@ -0,0 +1,28 @@
+// Issue 941 : The following operators should not be broken by auto-indents
+module m;
+initial begin
+a = b;
+a <= b;
+a <<= b;
+a <<<= b;
+a >= b;
+a >>= b;
+a >>>= b;
+a == b;
+a != b;
+a === b;
+a !== b;
+a ==? b;
+a !=? b;
+a <-> b;
+a -> b;
+a ->> b;
+a |-> b;
+a |=> b;
+a #-# b;
+a #=# b;
+a := b;
+a :/ b;
+end
+
+endmodule
diff --git a/tests/indent_attributes.v b/tests/indent_attributes.v
new file mode 100644
index 0000000..7129017
--- /dev/null
+++ b/tests/indent_attributes.v
@@ -0,0 +1,10 @@
+module example(out1, out2, out3);
+ (* LOC = "D14" *)
+ output out1;
+ /* foobar */ (* LOC = "C15" *) /* jar */ output out2;
+ (* LOC = "C16" *)
+ output out3;
+ out1 = 1'b1;
+ out2 = 1'b1;
+ out3 = 1'b1;
+endmodule
diff --git a/tests/indent_begin_clapp.v b/tests/indent_begin_clapp.v
new file mode 100644
index 0000000..eae4b7a
--- /dev/null
+++ b/tests/indent_begin_clapp.v
@@ -0,0 +1,44 @@
+// bug 825
+module x;
+
+always @*
+begin
+end
+
+initial
+begin
+end
+
+final
+begin
+end
+
+initial forever
+ begin
+end
+
+foreach(1)
+begin
+ end
+
+do
+ begin
+ end while (i);
+
+initial @a.b
+ begin
+end
+
+always @E
+ begin
+ end
+
+forever @E
+ begin
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-indent-begin-after-if: nil
+// End:
diff --git a/tests/indent_bracket.v b/tests/indent_bracket.v
new file mode 100644
index 0000000..ad44b16
--- /dev/null
+++ b/tests/indent_bracket.v
@@ -0,0 +1,12 @@
+// bug437: Indentation of continued assignment incorrect if first line ends with ']'
+module foo
+(input [63:0] data_in,
+ input ctl_in,
+
+output [63:0] data_out,
+output ctl_out);
+
+assign data_out = data_in[1] ? data_in[63:0]
+: 64'h0;
+
+endmodule
diff --git a/tests/indent_case.v b/tests/indent_case.v
new file mode 100644
index 0000000..8fdee11
--- /dev/null
+++ b/tests/indent_case.v
@@ -0,0 +1,48 @@
+module testcaseindent();
+ case (a)
+ 1: begin
+ asdf;
+ end // case: 1
+
+ 2: begin
+ asdfasdf;
+ end // case: 2
+
+ 3: begin
+ asdfasd;
+ end // case: 3
+
+ endcase // case (a)
+
+
+ unique case (a)
+ 1: begin
+ asdf;
+ end // case: 1
+
+ 2: begin
+ case (d)
+ 2: a;
+ 3: c;
+ 4: begin
+ priority casex (f)
+ 4: g;
+ 5: h;
+ endcase // priority casex
+ end
+ endcase // case (d)
+ asdfasdf;
+ end // case: 2
+
+ 3: begin
+ asdfasd;
+ end // case: 3
+
+ endcase // case (a)
+ unique case (a)
+ 1: asdf;
+ 2: asdfasdf;
+ 3: asdfasd;
+ endcase // case (a)
+
+endmodule // test_case_indent
diff --git a/tests/indent_class.v b/tests/indent_class.v
new file mode 100644
index 0000000..d74031e
--- /dev/null
+++ b/tests/indent_class.v
@@ -0,0 +1,53 @@
+class foo();
+ int my_field;
+endclass // foo
+
+class temp;
+ extern function test();
+ extern function test2();
+ function foo();
+ foo = 1;
+ endfunction // foo
+ extern function test3();
+ reg [31:0] b;
+endclass // temp
+
+class short extends temp;
+ logic a;
+endclass
+
+`define vmm_channel(A) A+A
+
+
+module foo;
+ reg a;
+ reg [1:0] b;
+
+ initial begin
+ b = `vmm_channel(a);
+ end // initial begin
+endmodule // foo
+
+
+class A;
+ extern function int e1();
+ extern function int e2(int src,int dst);
+ extern static function int f1();
+ extern static function int f2(int src,int dst);
+ extern static function int f3(int src,int dst);
+ extern static function chandle f10(int src);
+ extern static function automatic int f11(int mcid);
+ extern function automatic int f13(int mcid);
+ static function int s1();
+ int i = 0;
+ endfunction
+ static function int s2();
+ int i = 0;
+ endfunction
+ function int f1();
+ int i = 0;
+ endfunction
+ function int f2();
+ int i = 0;
+ endfunction
+endclass
diff --git a/tests/indent_clocking.v b/tests/indent_clocking.v
new file mode 100644
index 0000000..8b6b9ff
--- /dev/null
+++ b/tests/indent_clocking.v
@@ -0,0 +1,17 @@
+module t;
+ default clocking @(posedge clk);
+ begin
+ a = 8;
+ end
+ property foo (a)
+ a = b;
+ endproperty
+ cover property (prop) $display("**COVERAGE**");
+ assert property (foo) a;
+ assume property (bar) b;
+ b1: assume property (bar) b;
+ B2: assert property (foo) a;
+ B2: cover property (foo) a;
+ assume property (bar) b;
+ a;
+endmodule
diff --git a/tests/indent_clockingblock.v b/tests/indent_clockingblock.v
new file mode 100644
index 0000000..d8534a0
--- /dev/null
+++ b/tests/indent_clockingblock.v
@@ -0,0 +1,38 @@
+class mipsbfm_trans extends vmm_data;
+static vmm_log log = new ("mipsbfm_trans", "class") ;
+logic [31:0] addr, data, mask, op;
+function new();
+super.new(this.log);
+endfunction: new
+endclass // mipsbfm_trans
+
+interface mipsbfm_if(input clk);
+logic [31:0] data;
+logic [31:0] addr;
+logic [31:0] mask;
+logic [31:0] op;
+logic valid;
+
+clocking cb @(posedge clk);
+output data;
+output addr;
+output mask;
+output op;
+output valid;
+endclocking // cb
+
+endinterface // mipsbfm_if
+
+
+`vmm_channel(mipsbfm_trans);
+
+//--------------------------------------------------------------
+// MIPS BFM Master Xactor Class
+//--------------------------------------------------------------
+
+class mipsbfm_master extends vmm_xactor;
+// Transaction channels
+mipsbfm_trans_channel in_chan ;
+
+endclass // mipsbfm_master
+
diff --git a/tests/indent_comments.v b/tests/indent_comments.v
new file mode 100644
index 0000000..d6b707b
--- /dev/null
+++ b/tests/indent_comments.v
@@ -0,0 +1,7 @@
+module dummy (
+ input wire xx,
+ output wire yy, // comment with paren ) adsfasdf
+ ouput wire zz); // oops - matched paren in comment!!
+endmodule // dummy
+
+
diff --git a/tests/indent_constraint.v b/tests/indent_constraint.v
new file mode 100644
index 0000000..9890426
--- /dev/null
+++ b/tests/indent_constraint.v
@@ -0,0 +1,146 @@
+// my simple if else example, indented by verilog-mode
+if (x == 1)
+ begin
+ test1 <= 1;
+ test2 <= 2;
+ end
+else
+ begin
+ test1 <= 2;
+ test2 <= 1;
+ end
+
+// code from IEEE spec, pg. 164
+class MyBus extends Bus;
+ rand AddrType atype;
+ constraint addr_range
+ {
+ (atype == low ) -> addr inside { [0 : 15] };
+ (atype == mid ) -> addr inside { [16 : 127]};
+ (atype == high) -> addr inside {[128 : 255]};
+ }
+ //
+endclass // MyBus
+
+// same example, with verilog mode indenting, Cexp indent = 3
+class MyBus extends Bus;
+ rand AddrType atype;
+ constraint addr_range
+ {
+ (atype == low ) -> addr inside { [0 : 15] };
+ (atype == mid ) -> addr inside { [16 : 127]};
+ (atype == high) -> addr inside {[128 : 255]};
+ }
+ //
+endclass // MyBus
+
+// same example, with verilog mode indenting, Cexp indent = 0
+class MyBus extends Bus;
+ rand AddrType atype;
+ constraint addr_range
+ {
+ (atype == low ) -> addr inside { [0 : 15] };
+ (atype == mid ) -> addr inside { [16 : 127]};
+ (atype == high) -> addr inside {[128 : 255]};
+ }
+endclass // MyBus
+
+// covergroup example from IEEE pg. 317
+covergroup cg @(posedge clk );
+ a : coverpoint v_a {
+ bins a1 = { [0:63] };
+ bins a2 = { [64:127] };
+ bins a3 = { [128:191] };
+ bins a4 = { [192:255] };
+ }
+ b : coverpoint v_b {
+ bins b1 = {0};
+ bins b2 = { [1:84] };
+ bins b3 = { [85:169] };
+ bins b4 = { [170:255] };
+ }
+ //
+ c : cross a, b
+ {
+ bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
+ bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
+ bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
+ }
+endgroup
+
+// here is the same code with verilog-mode indenting
+// covergroup example from IEEE pg. 317
+covergroup cg @(posedge clk );
+ a : coverpoint v_a
+ {
+ bins a1 = { [0:63] };
+ bins a2 = { [64:127] };
+ bins a3 = { [128:191] };
+ bins a4 = { [192:255] };
+ }
+ // foo
+ b : coverpoint v_b
+ {
+ bins b1 = {0};
+ bins b2 = { [1:84] };
+ bins b3 = { [85:169] };
+ bins b4 = { [170:255] };
+ }
+ c : cross a, b
+ {
+ bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
+ bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
+ bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
+ }
+endgroup
+
+module fool;
+
+ always @(posedge clk) begin
+ if(!M_select)
+ xferCount < = 8'd0;
+ else
+ case (condition[1 :0])
+ 2'b00 : xferCount <= xferCount;
+ 2'b01 : xferCount <= xferCount - 8'd1;
+ 2'b10 : xferCount <= xferCount + 8'd1;
+ 2'b11 : xferCount <= xferCount;
+ endcase // case (condition[1:0])
+ end
+ // But not this :
+ always @(posedge clk) begin
+ if(!M_select)
+ xferCount < = 8'd0;
+ else
+ case ({M_seqAddr,OPB_xferAck})
+ 2'b00 : xferCount <= xferCount;
+ 2'b01 : xferCount <= xferCount - 8'd1;
+ 2'b10 : xferCount <= xferCount + 8'd1;
+ 2'b11 : xferCount <= xferCount;
+ endcase // case ({M_seqAddr,OPB_xferAck})
+ end // always @ (posedge clk)
+
+endmodule // fool
+
+module foo;
+ initial begin
+ k = 10;
+ std::randomize(delay) with { (delay>=1000 && delay<=3000); };
+ j = 9;
+ end
+endmodule // foo
+
+
+// Issue 324 - constraint indentation is not correct
+// This checks for indentation around { and } inside constraint contents
+class myclass;
+constraint c {
+foreach(items[i]) {
+if(write) {
+items[i].op_code == WRITE;
+} else if(read) {
+items[i].op_code == READ;
+}
+}
+}
+endclass // myclass
diff --git a/tests/indent_constraint2.v b/tests/indent_constraint2.v
new file mode 100644
index 0000000..77ecf48
--- /dev/null
+++ b/tests/indent_constraint2.v
@@ -0,0 +1,25 @@
+
+constraint Cepon_gate_random::grant_relations_c {
+ foreach (grant_relation_m[index]) {
+ if ((index == 0) && (last_start_time_m < time_stamp_m+`MINIMUM_TIME_TO_GATE)) grant_relation_m[index] == EPON_GATE_IN_ORDER;
+
+ else {
+
+ grant_relation_m[index] dist {
+ EPON_GATE_IN_ORDER :/55,
+ EPON_GATE_1ST_CONTAINS_2ND :/5,
+ EPON_GATE_2ND_CONTAINS_1ST :/5,
+ EPON_GATE_1ST_START_2ND_START :/5,
+ EPON_GATE_2ND_START_1ST_START :/5,
+ EPON_GATE_NO_GAP_1ST :/5,
+ EPON_GATE_NO_GAP_2ND :/5,
+ EPON_GATE_1CC_GAP :/5,
+ EPON_GATE_1CC_INTERLEAVE :/5,
+ EQUAL :/5
+ };
+
+}
+
+ }
+
+ }
diff --git a/tests/indent_constraint3.v b/tests/indent_constraint3.v
new file mode 100644
index 0000000..4f4538c
--- /dev/null
+++ b/tests/indent_constraint3.v
@@ -0,0 +1,30 @@
+//bug433
+
+class data;
+ rand integer data1;
+ rand integer data2,data3;
+ rand reg [31:0] foo;
+
+ constraint basic_c {
+ //empty constraint
+ }
+
+ constraint complex_c {
+ data1 <= 100;
+ foo inside {[40:999]};
+ if(foo < 87)
+ data2 == 10;
+ if(data2 == 76) {
+ data3 == 8;
+ }
+ }
+
+ constraint implication_c {
+ data1 == 10 -> data3 >= -1;
+ }
+
+ function new();
+ data1 = 0;
+ data2 = 78;
+ endfunction // new
+endclass // data
diff --git a/tests/indent_covergroup.v b/tests/indent_covergroup.v
new file mode 100644
index 0000000..148892b
--- /dev/null
+++ b/tests/indent_covergroup.v
@@ -0,0 +1,46 @@
+module coverage;
+ enum { red, green, blue } color;
+ covergroup foo @(posedge clk);
+ c : coverpoint color;
+ c : coverpoint color;
+ c : coverpoint color;
+ c : coverpoint color;
+ endgroup // foo
+
+ foo = bar;
+
+ sequence bar
+ b = c;
+ endsequence // bar
+ j = taskt;
+ function foo;
+ begin
+ foo = 1;
+ end
+ endfunction // foo
+
+ randsequence bar
+ b = c;
+ endsequence // bar
+
+ case (foo)
+ 1: a;
+ 2:b;
+ endcase // case (foo)
+
+ casex (foo)
+ 1: a;
+ 2:b;
+ endcase // case (foo)
+
+ casez (foo)
+ 1: a;
+ 2:b;
+ endcase // case (foo)
+
+ randcase (foo)
+ 1: a;
+ 2:b;
+ endcase // case (foo)
+
+endmodule // coverage
diff --git a/tests/indent_coverpoint.v b/tests/indent_coverpoint.v
new file mode 100644
index 0000000..52650f4
--- /dev/null
+++ b/tests/indent_coverpoint.v
@@ -0,0 +1,29 @@
+
+// here is the same code with verilog-mode indenting
+// covergroup example from IEEE pg. 317
+covergroup cg @(posedge clk);
+a: coverpoint v_a {
+bins a1 = { [0:63] };
+bins a2 = { [64:127] };
+bins a3 = { [128:191] };
+bins a4 = { [192:255] };
+}
+b: coverpoint v_b iff ( g )
+{
+bins b1 = {0};
+bins b2 = { [1:84] };
+bins b3 = { [85:169] };
+bins b4 = { [170:255] };
+}
+c: coverpoint v_c iff ( !g ) {
+bins c1 = {0};
+bins c2 = { [1:84] };
+bins c3 = { [85:169] };
+bins c4 = { [170:255] };
+}
+d: cross a , b, c {
+bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
+bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
+bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
+}
+endgroup
diff --git a/tests/indent_decl-1.v b/tests/indent_decl-1.v
new file mode 100644
index 0000000..8ec2dae
--- /dev/null
+++ b/tests/indent_decl-1.v
@@ -0,0 +1,27 @@
+module soft_rst
+ (
+ // System clock and reset
+ input clk,
+ input rst_n,
+
+ // Interface to software land
+ input req_soft_rst, // Soft reset request
+ output soft_rst_dne, // Soft reset done
+
+ // Interface to other modules
+ output dma_halt, // Reset pending, halt activity
+ input tx_quiet, // TX side is dormant
+ input rx_quiet, // RX side is dormant
+ input c,
+ output soft_rst, // Soft (sync) reset to VC3 side
+ output hs_async_rst_n // Async reset to host side
+ );
+
+ reg [1:0] state;
+
+ reg [1:0] IDLE = 2'h0,
+ HALT = 2'h1,
+ RST = 2'h2,
+ DONE = 2'h3;
+
+endmodule // soft_rst
diff --git a/tests/indent_decl.v b/tests/indent_decl.v
new file mode 100644
index 0000000..040c3b7
--- /dev/null
+++ b/tests/indent_decl.v
@@ -0,0 +1,9 @@
+module foo;
+ input a;
+ input b;
+ input [1:0] cfg_dev_i; // Config Device: 0b00 = Pangu, 0b01 = Switch
+ output switch_idsel_o; // Switch PCI IDSEL
+ output pangu_idsel_o; // Pangu PCI IDSEL
+ output wire g;
+ inout wire h;
+endmodule // foo
diff --git a/tests/indent_directives.v b/tests/indent_directives.v
new file mode 100644
index 0000000..cb8f97c
--- /dev/null
+++ b/tests/indent_directives.v
@@ -0,0 +1,69 @@
+module foo;
+`ifdef LABEL_A
+ CHIP CPU (
+ .clkin(clkin),
+ `ifdef LABEL_B
+ .bclko(bclko),
+ `endif
+ .cmode(cmode),
+ );
+ input sysclk;
+ `ifdef LABEL_B
+ input bclko;
+ `endif
+ input cmode;
+`endif
+
+ // instead of:
+
+`ifdef LABEL_A
+ CHIP CPU (
+ .clkin(clkin),
+ `ifdef LABEL_B
+ .bclko(bclko),
+ `endif
+ .cmode(cmode),
+ );
+ input sysclk;
+ `ifdef LABEL_B
+ input bclko;
+ `endif
+ input cmode;
+`endif // `ifdef LABEL_A
+ reg a,b;
+`ifdef A
+ always @(a) begin
+ b = a; // asfSDfsdfsasa
+ b = a; // asfSDfsdfsasa
+ b = a; // asfSDfsdfsasa //
+ b = a; // asfSDfsdfsasa //
+ b = a; // asfSDfsdfsasa //
+ b = a; // asfSDfsdfsasa //
+ b = a; // asfSDfsdfsasa //
+ b = a; // asfSDfsdfsasa //
+ b = a; // asfSDfsdfsasa //
+ end
+`elsif B
+ always @(b) begin
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa //
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa //
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa //
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa //
+ end
+`else // !`elsif B
+ always @(a or b) begin
+ a <= b;
+ b <= a;
+ end
+`endif // !`elsif B
+
+
+endmodule // foo
diff --git a/tests/indent_dpi.v b/tests/indent_dpi.v
new file mode 100644
index 0000000..10e1b42
--- /dev/null
+++ b/tests/indent_dpi.v
@@ -0,0 +1,29 @@
+ import "DPI-C" function string fna (input string str1);
+export "DPI" c_identifier = task task_identifier;
+ import "DPI" context function string fnb (input string str1);
+
+module testbench;
+
+ import "DPI" function string fn1 (input string str1);
+ import "DPI-C" function void dpiWriteArray (input bit[7:0] data[]);
+ import "DPI-C" pure function void dpiReadArray (output bit[7:0] data[]);
+ import "DPI-C" function void dpiAesSetKey ( int key_high_u int key_high_l,
+ int key_low_u, int key_low_l );
+ import "DPI-C" function void dpiAesSetIV (int iv_high_u, int iv_high_l,
+ int iv_low_u, int iv_low_l);
+ import "DPI-C" function void dpiAesSetSkip (int skip);
+ import "DPI-C" function void dpiAesCBCEncrypt ();
+
+ logic a;
+endmodule // testbench
+
+/*
+package ref_model;
+ import "DPI-C" xx_write_bmp_file =
+ function void write_bmp_file(input string filename);
+
+ import "DPI-C" xx_demosaic =
+ function void demosaic(regs regs,
+ inout pix_buf imgR, imgG, imgB);
+endpackage
+*/
diff --git a/tests/indent_foreach.v b/tests/indent_foreach.v
new file mode 100644
index 0000000..b07ba29
--- /dev/null
+++ b/tests/indent_foreach.v
@@ -0,0 +1,14 @@
+`ifndef FOO
+ `define FOO
+module foo;
+ reg [31:0] payload [255:0];
+ reg [7:0] index;
+
+ always @ (b) begin
+ foreach (1) begin
+ @(router.cb);
+ end // foreach (1)
+ end // always @ (b)
+endmodule // foo
+`else // !`ifndef FOO
+`endif // !`ifndef FOO
diff --git a/tests/indent_fork_join_any.v b/tests/indent_fork_join_any.v
new file mode 100644
index 0000000..93f099e
--- /dev/null
+++ b/tests/indent_fork_join_any.v
@@ -0,0 +1,27 @@
+module fork_join_any;
+ initial begin
+ fork
+ begin
+ fork
+ begin
+ end
+ join_any
+ a = b;
+ disable fork;
+ blah;
+ wait fork;
+ blah;
+ end
+ join_any
+ foo = bar;
+ end // initial fork
+endmodule // fork_join_any
+
+class x;
+ task y;
+ a = b;
+ wait fork;
+ $display("I'm indented too far");
+ endtask // y
+endclass // x
+
diff --git a/tests/indent_formfeed.v b/tests/indent_formfeed.v
new file mode 100644
index 0000000..1d06580
--- /dev/null
+++ b/tests/indent_formfeed.v
@@ -0,0 +1,9 @@
+
+module x;
+
+ foo;
+endmodule
+
+bar;
+module z;
+endmodule
diff --git a/tests/indent_function.v b/tests/indent_function.v
new file mode 100644
index 0000000..2614d06
--- /dev/null
+++ b/tests/indent_function.v
@@ -0,0 +1,50 @@
+module t;
+
+endmodule
+class C;
+ function int f();
+ f = 17;
+ endfunction
+ extern function int g();
+ virtual function int f();
+ a;
+ endfunction // int
+ // pure virtual functions have no endfunction.
+ C a;
+ initial begin
+ $display("hello world");
+ $display("a of f is %d, g is %d", a.f(),a.g());
+ end
+ function int C::g();
+ g = 18;
+ endfunction // g
+ // pure virtual functions have no endfunction.
+endclass // C
+
+class pure_virt_func_class;
+ pure virtual function string pure_virt_func();
+ pure virtual function string pure_virt_func();
+ pure virtual function string pure_virt_func();
+ extern pure virtual task t();
+ pure virtual task t();
+ virtual task t();
+ /* body */
+ endtask // t
+ virtual function f();
+ /* body */
+ endfunction // f
+endclass // pure_virt_func_class
+
+class base_test extends uvm_test;
+ `uvm_component_utils(base_test)
+ typedef virtual my_if my_vif_t;
+ // A function definition starting with the virtual keyword should not be
+ // detected as a declaration. This issue is seen when an attempt to indent
+ // each declaration is done (when the verilog-auto-lineup variable is set
+ // to 'declarations).
+ // In other words, the "function" in "virtual function" below must not be
+ // aligned with "my_if" in the "typedef virtual my_if.." line above.
+ virtual function void start_of_simulation_phase(uvm_phase phase);
+ super.start_of_simulation_phase(phase);
+ endfunction : start_of_simulation_phase
+endclass : base_test
diff --git a/tests/indent_generate.v b/tests/indent_generate.v
new file mode 100644
index 0000000..00480fb
--- /dev/null
+++ b/tests/indent_generate.v
@@ -0,0 +1,15 @@
+module test();
+
+ reg [3:0] x;
+
+ genvar i;
+ generate
+ for(i=0; i<4; i=i+1) begin:a
+ always @(*) begin
+ x[i] = 1;
+ end
+ wire y = 0;
+ end
+ endgenerate
+endmodule // test
+
diff --git a/tests/indent_if.v b/tests/indent_if.v
new file mode 100644
index 0000000..6732e22
--- /dev/null
+++ b/tests/indent_if.v
@@ -0,0 +1,7 @@
+module foo;
+ initial
+ if (cond1) begin
+ sig1 <= {4'h0, 4'hc};
+ sig2 <= 8'hff;
+ end // if (cond1)
+endmodule // foo
diff --git a/tests/indent_if2.v b/tests/indent_if2.v
new file mode 100644
index 0000000..1381d98
--- /dev/null
+++ b/tests/indent_if2.v
@@ -0,0 +1,23 @@
+module foo;
+ always@(*)
+ begin
+ if(state==LBT_STATE)
+ begin
+ if(something)
+ begin
+ end
+ else
+ begin
+ end
+ end
+ else if(state==HS_0_STATE)
+ begin
+ end
+ else if(state==STATE_4)
+ begin
+ end
+ else
+ begin
+ end
+ end // always@ (*)
+endmodule // foo
diff --git a/tests/indent_ifdef.v b/tests/indent_ifdef.v
new file mode 100644
index 0000000..00360b2
--- /dev/null
+++ b/tests/indent_ifdef.v
@@ -0,0 +1,46 @@
+module test(out);
+ output out;
+`define wow
+`define nest_one
+`define second_nest
+`define nest_two
+`ifdef wow
+ initial $display("wow is defined");
+ `ifdef nest_one
+ initial $display("nest_one is defined");
+ `ifdef nest_two
+ initial $display("nest_two is defined");
+ `else
+ initial $display("nest_two is not defined");
+ `endif
+ `else
+ initial $display("nest_one is not defined");
+ `endif
+`else
+ initial $display("wow is not defined");
+ `ifdef second_nest
+ initial $display("second_nest is defined");
+ `else
+ initial $display("second_nest is not defined");
+ `endif
+`endif
+endmodule
+
+
+// Local Variables:
+// verilog-auto-lineup: all
+// verilog-auto-endcomments: t
+// verilog-auto-indent-on-newline: t
+// verilog-auto-lineup: all
+// verilog-auto-newline: nil
+// verilog-case-indent: 2
+// verilog-highlight-p1800-keywords: nil
+// verilog-indent-begin-after-if: t
+// verilog-indent-level: 2
+// verilog-indent-level-behavioral: 2
+// verilog-indent-level-declaration: 2
+// verilog-indent-level-directive: 2
+// verilog-indent-level-module: 2
+// verilog-minimum-comment-distance: 40
+// verilog-tab-always-indent: t
+// End:
diff --git a/tests/indent_ifdef_generate.v b/tests/indent_ifdef_generate.v
new file mode 100644
index 0000000..858c0a1
--- /dev/null
+++ b/tests/indent_ifdef_generate.v
@@ -0,0 +1,32 @@
+// Issue 559 - nested ifdef with generate indentation bug
+module m;
+
+`ifndef DDR_PT_GATE_SIM
+generate
+/***************** Assertions for DP HM signals ***************************************************************/
+for (dp_id=0; dp_id <PDDR_NUM_DP; dp_id++) begin: DPConnectGen
+
+if (PDDR_DP_HV[dp_id]) begin: VGen
+`ifdef IO_DDR3
+// CR?V connectivity for DP HM
+DP_CRN0V15_Connection: assert property (ConnectProp(1'b1, `PHYTOP.CRN0V[dp_id+PGEN_NUM_ADR], `PHYTOP.DPBundleGen[dp_id].u_DpBundle.`DPV_INST.CRN0V15))
+else begin
+$display ($stime, " ERROR: CRN0V[%0d] to DP HM %0d CRN0V15 Connection Failed", dp_id+PGEN_NUM_ADR, dp_id);
+
+postError();
+
+end // else: !assert property
+DP_CRN1V15_Connection: assert property (ConnectProp(1'b1, `PHYTOP.CRN1V[dp_id+PGEN_NUM_ADR], `PHYTOP.DPBundleGen[dp_id].u_DpBundle.`DPV_INST.CRN1V15))
+else begin
+$display ($stime, " ERROR: CRN1V[%0d] to DP HM %0d CRN1V15 Connection Failed", dp_id+PGEN_NUM_ADR, dp_id);
+
+postError();
+
+end // else: !assert property
+end // block: VGen
+`endif // `ifdef IO_DDR3
+end // block: DPConnectGen
+endgenerate
+`endif
+
+endmodule // m
diff --git a/tests/indent_immediate_assertion.sv b/tests/indent_immediate_assertion.sv
new file mode 100644
index 0000000..c682efb
--- /dev/null
+++ b/tests/indent_immediate_assertion.sv
@@ -0,0 +1,27 @@
+// Issue 949 - Indenting SVA assert final block broken
+module tb;
+begin
+a0: assert final (data0 == 1) else
+$error;
+end
+endmodule
+
+
+// Now check for other types of immediate assertion
+module tb;
+always @(abcd) begin
+
+// simple immediate assert statement
+assert (xyz) a = b;
+
+// deferred immediate cover statement w/ #0
+if(x)
+cover #0 (efg)
+$display("covered");
+
+// deferred immedate assume statement w/ final
+assume final (abcd) else
+$display();
+end
+
+endmodule
diff --git a/tests/indent_importfunction.v b/tests/indent_importfunction.v
new file mode 100644
index 0000000..18f2a66
--- /dev/null
+++ b/tests/indent_importfunction.v
@@ -0,0 +1,8 @@
+module toto (input logic dummy);
+ import "DPI-C" pure function real fabs (input real a);
+ import "DPI-C" context function real fcons (input real a);
+ import "DPI-C" string_sv2c = task string();
+ import "DPI-C" int_sv2c = task intsv2c();
+ import "DPI-C" context int_sv2c = task intsv2cont();
+ logic a; // wrong indentation
+endmodule // wrong indentation
diff --git a/tests/indent_interface.v b/tests/indent_interface.v
new file mode 100644
index 0000000..0f669da
--- /dev/null
+++ b/tests/indent_interface.v
@@ -0,0 +1,27 @@
+interface simple_bus; // Define the interface
+ logic req, gnt;
+ logic [7:0] addr, data;
+ logic [1:0] mode;
+ logic start, rdy;
+endinterface: simple_bus
+module memMod(
+ simple_bus a, // Access the simple_bus interface
+ input bit clk);
+
+ logic avail;
+ // When memMod is instantiated in module top, a.req is the req
+ // signal in the sb_intf instance of the simple_bus interface
+ always @(posedge clk)
+ a.gnt <= a.req & avail;
+endmodule
+module cpuMod(simple_bus b, input bit clk);
+ always @(b) begin
+ end
+endmodule
+module top;
+ logic clk = 0;
+ simple_bus sb_intf(); // Instantiate the interface
+ memMod mem(sb_intf, clk); // Connect the interface to the module instance
+ cpuMod cpu(.b(sb_intf), .clk(clk)); // Either by position or by name
+endmodule
+
diff --git a/tests/indent_linefeed.v b/tests/indent_linefeed.v
new file mode 100644
index 0000000..d90d70c
--- /dev/null
+++ b/tests/indent_linefeed.v
@@ -0,0 +1,18 @@
+module foo;
+ input a,b;
+
+ always @(a) begin
+ b <= #10 ~ a;
+ end
+endmodule // foo
+
+module bar;
+ //
+ input a,b;
+
+ always @(a) begin //
+ b <= #10 ~ a;
+
+ a;
+ end
+endmodule // foo
diff --git a/tests/indent_lineup_inlists.v b/tests/indent_lineup_inlists.v
new file mode 100644
index 0000000..46ceba4
--- /dev/null
+++ b/tests/indent_lineup_inlists.v
@@ -0,0 +1,25 @@
+module soft_rst (
+ // System clock and reset
+ input clk,
+ input rst_n,
+
+ // Interface to software land
+ input req_soft_rst, // Soft reset request
+ output soft_rst_dne, // Soft reset done
+
+ // Interface to other modules
+ output dma_halt, // Reset pending, halt activity
+ input tx_quiet, // TX side is dormant
+ input rx_quiet, // RX side is dormant
+ output soft_rst, // Soft (sync) reset to VC3 side
+ output hs_async_rst_n // Async reset to host side
+ );
+
+ reg [1:0] state;
+
+ localparam [1:0] IDLE = 2'h0,
+ HALT = 2'h1,
+ RST = 2'h2,
+ DONE = 2'h3;
+
+endmodule // soft_rst
diff --git a/tests/indent_lineup_mode_all.v b/tests/indent_lineup_mode_all.v
new file mode 100644
index 0000000..d98a057
--- /dev/null
+++ b/tests/indent_lineup_mode_all.v
@@ -0,0 +1,19 @@
+module test (pci_ack, reg_wr, reg_sel, clk, rst);
+ input [3:0] pci_ack;
+ input reg_wr;
+ input reg_sel;
+ input clk;
+ input rst;
+ initial begin
+ foo;
+ bar;
+ x <= y;
+ longish <= alsolongish;
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-lineup: all
+// End:
+
diff --git a/tests/indent_lineup_mode_assignments.v b/tests/indent_lineup_mode_assignments.v
new file mode 100644
index 0000000..7fe9e55
--- /dev/null
+++ b/tests/indent_lineup_mode_assignments.v
@@ -0,0 +1,18 @@
+module test (pci_ack, reg_wr, reg_sel, clk, rst);
+ input [3:0] pci_ack;
+ input reg_wr;
+ input reg_sel;
+ input clk;
+ input rst;
+ initial begin
+ foo;
+ bar;
+ x <= y;
+ longish <= alsolongish;
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-lineup: assignments
+// End:
diff --git a/tests/indent_lineup_mode_declarations.v b/tests/indent_lineup_mode_declarations.v
new file mode 100644
index 0000000..b7f036c
--- /dev/null
+++ b/tests/indent_lineup_mode_declarations.v
@@ -0,0 +1,19 @@
+module test (pci_ack, reg_wr, reg_sel, clk, rst);
+ input [3:0] pci_ack;
+ input reg_wr;
+ input reg_sel;
+ input clk;
+ input rst;
+ initial begin
+ foo;
+ bar;
+ x <= y;
+ longish <= alsolongish;
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-lineup: declarations
+// End:
+
diff --git a/tests/indent_lineup_mode_none.v b/tests/indent_lineup_mode_none.v
new file mode 100644
index 0000000..85eb88c
--- /dev/null
+++ b/tests/indent_lineup_mode_none.v
@@ -0,0 +1,19 @@
+module test (pci_ack, reg_wr, reg_sel, clk, rst);
+ input [3:0] pci_ack;
+ input reg_wr;
+ input reg_sel;
+ input clk;
+ input rst;
+ initial begin
+ foo;
+ bar;
+ x <= y;
+ longish <= alsolongish;
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-lineup: nil
+// End:
+
diff --git a/tests/indent_macro_braces.v b/tests/indent_macro_braces.v
new file mode 100644
index 0000000..327c48b
--- /dev/null
+++ b/tests/indent_macro_braces.v
@@ -0,0 +1,9 @@
+// bug 433 - Check indentation around macro (uvm/ovm/vmm) with curly-brace
+// internals (these look like a constraint)
+
+module m;
+if(x)
+`ovm_do_with(my,
+{ y == 1;
+z == 2; });
+endmodule
diff --git a/tests/indent_macro_comment.v b/tests/indent_macro_comment.v
new file mode 100644
index 0000000..69a75a4
--- /dev/null
+++ b/tests/indent_macro_comment.v
@@ -0,0 +1,41 @@
+// issue 935 - Incorrect indentation after multi-line `define macro
+`ifndef _ABC
+ `define _ABC
+
+ `define TEMPA 1
+
+// CORRECT INDENTATION
+
+ `define DEF1 { "a" \
+ , "b" \
+ }
+
+ // Incorrect indentation (v1) after multi-line macro definition above
+
+ `define TEMPB (`TEMPA >= 0 ? 0 : 1)
+
+ // Incorrect indentation (v1) *strangely, not yet affected by the >= chars above*
+
+ `define DEF2 { "a" \
+ , "b" \
+ }
+
+ // Incorrect indentation (v2) *NOW aligns to the
+ // >= sign in `define TEMPB above (which it should not)
+ // Looks like the multi-line macro definition DEF2
+ // above caused this second version of incorrect
+ // indentation*
+
+ `define TEMPC ((`TEMPA + 1_000_000) >= 0 ? 0 : 1)
+
+ // BACK TO Incorrect indentation (v1)!
+
+ `define DEF3 { "a" \
+ , "b" \
+ }
+
+ // BACK TO Incorrect indentation (v2)! Surprisingly
+ // the >= sign in `define TEMPC macro did not affect
+ // the indentation this time; but the indentation
+ // returned to (v2) as set by that sign in `define TEMPB
+`endif
diff --git a/tests/indent_mailbox.v b/tests/indent_mailbox.v
new file mode 100644
index 0000000..b50a1b8
--- /dev/null
+++ b/tests/indent_mailbox.v
@@ -0,0 +1,13 @@
+class Driver;
+ mailbox mbox; // <= not highlighted.
+ semaphore smtx;
+ int id;
+ virtual Rx_if Rx;
+
+ function new(mailbox mbox, int id, virtual Rx_if.TB Rx);
+ this.mbox = mbox;
+ this.id = i;
+ this.Rx = Rx;
+ endfunction // new
+endclass // Driver
+
diff --git a/tests/indent_modansi.v b/tests/indent_modansi.v
new file mode 100644
index 0000000..2d80560
--- /dev/null
+++ b/tests/indent_modansi.v
@@ -0,0 +1,16 @@
+module testmodule(
+ input wire [1:0] pin1,
+ input wire pin2,
+ input wire [1:0] pin3,
+ input wire pin4,
+ output wire pin5,
+ output wire [10:0] pin6,
+ output reg pin7,
+ output reg [1:0] pin8
+ );
+ initial begin
+ $display("alls well that ends well");
+ end
+endmodule // testmodule
+
+
diff --git a/tests/indent_modport.v b/tests/indent_modport.v
new file mode 100644
index 0000000..20c71b0
--- /dev/null
+++ b/tests/indent_modport.v
@@ -0,0 +1,6 @@
+module foo;
+ modport foo_mp;
+ modport foo_mp1(a);
+ modport foo_mp2(clocking bar_cb);
+ a;
+endmodule // foo
diff --git a/tests/indent_named_assert.v b/tests/indent_named_assert.v
new file mode 100644
index 0000000..8b70d34
--- /dev/null
+++ b/tests/indent_named_assert.v
@@ -0,0 +1,9 @@
+module test;
+property p_test;
+a |-> b;
+endproperty : p_test
+assert property (p_test);
+a_test : assert property (p_test);
+a = b; // this and following lines are not properly indented
+foo;
+endmodule // test
diff --git a/tests/indent_ovm.v b/tests/indent_ovm.v
new file mode 100644
index 0000000..96080f0
--- /dev/null
+++ b/tests/indent_ovm.v
@@ -0,0 +1,70 @@
+module ovm;
+class simple_item extends ovm_sequence_item;
+ rand int unsigned addr;
+ rand int unsigned data;
+ rand int unsigned delay;
+ constraint c1 { addr < 16'h2000; }
+ constraint c2 { data < 16'h1000; }
+ // OVM automation macros for general objects
+ `ovm_object_utils_begin(simple_item)
+ a = b;
+ c = d;
+ `ovm_field_int(addr, OVM_ALL_ON)
+ `ovm_field_int(data, OVM_ALL_ON)
+ `ovm_field_int(delay, OVM_ALL_ON)
+ `ovm_object_utils_end
+ // Constructor
+ function new (string name = "simple_item");
+ super.new(name);
+ endfunction : new
+endclass : simple_item
+class mydata extends ovm_object;
+
+ string str;
+ mydata subdata;
+ int field;
+ myenum e1;
+ int queue[$];
+ `ovm_object_utils(mydata)
+ `ovm_object_utils_begin(mydata) //requires ctor with default args
+ `ovm_field_string(str, OVM_DEFAULT)
+ `ovm_field_object(subdata, OVM_DEFAULT)
+ `ovm_field_int(field, OVM_DEC) //use decimal radix
+ `ovm_field_enum(myenum, e1, OVM_DEFAULT)
+ `ovm_field_queue_int(queue, OVM_DEFAULT)
+ `ovm_object_utils_end
+ `ovm_object_param_utils_begin(mydata) //requires ctor with default args
+ `ovm_field_string(str, OVM_DEFAULT)
+ `ovm_field_object(subdata, OVM_DEFAULT)
+ `ovm_field_int(field, OVM_DEC) //use decimal radix
+ `ovm_field_enum(myenum, e1, OVM_DEFAULT)
+ `ovm_field_queue_int(queue, OVM_DEFAULT)
+ `ovm_object_utils_end
+endclass
+class my_trans extends ovm_sequence_item;
+
+ rand bit [127:0] data [];
+
+ //---> Configuration
+ `ovm_object_utils_begin(my_trans)
+ `ovm_field_array_int ( data, OVM_ALL_ON)
+ `ovm_object_utils_end
+
+ function new (string name = "my_trans", ovm_sequencer_base sequencer = null, ovm_sequence parent_seq = null);
+ super.new(name, sequencer, parent_seq);
+ endfunction : new
+endclass : my_trans
+endmodule // ovm
+
+module tt;
+
+ initial begin
+ while (1) begin
+ `ovm_do_with(aa, {bb == 0;})
+ `ovm_do(cc)
+ `ovm_do(cc)
+ end // while (1)
+ end // initial begin
+
+endmodule // tt
+
diff --git a/tests/indent_param.v b/tests/indent_param.v
new file mode 100644
index 0000000..fbabe68
--- /dev/null
+++ b/tests/indent_param.v
@@ -0,0 +1,15 @@
+module example_block
+#(
+parameter PARAM = 1,
+FOO = 2,
+BARFLUG = 4,
+G = 5,
+)
+(// I/O
+input reset_n,
+input clk
+input a, b,
+output reg c
+);
+endmodule
+
diff --git a/tests/indent_preproc.v b/tests/indent_preproc.v
new file mode 100644
index 0000000..bd1d738
--- /dev/null
+++ b/tests/indent_preproc.v
@@ -0,0 +1,27 @@
+
+
+aa;
+`__FILE__
+ `__LINE__
+ `celldefine
+ `end_keywords
+ `resetall
+ `unconnected_drive
+ `undefineall
+
+`ifdef AA
+`else
+`endif
+`ifndef AA
+`elsif FOO
+`endif
+
+ `begin_keywords "FOO"
+`undef FOO
+
+`line 2 "xx" 2
+`include "YY"
+`include <YY>
+`pragma endofline
+`timescale 10ns/10ps
+`define foo bar
diff --git a/tests/indent_preproc_label.v b/tests/indent_preproc_label.v
new file mode 100644
index 0000000..a6684c7
--- /dev/null
+++ b/tests/indent_preproc_label.v
@@ -0,0 +1,16 @@
+// bug861/862 - named coverpoint inside/near pre-processor macro confuses indentation
+module m;
+
+`ifdef ASSERT_ON
+asrt_001: assert property(p_001);
+asrt_002: assert property(p_002);
+asrt_003: assert property(p_003);
+`endif
+
+`ifdef COVER_ON
+chk_001: cover property(p_001);
+chk_002: cover property(p_002);
+chk_003: cover property(p_003);
+`endif
+
+endmodule
diff --git a/tests/indent_property.v b/tests/indent_property.v
new file mode 100644
index 0000000..d9d7d7b
--- /dev/null
+++ b/tests/indent_property.v
@@ -0,0 +1,65 @@
+module foo();
+ initial begin
+ a;
+ end
+
+ always @(a) begin
+ b;
+ end
+ task a (a);
+ begin
+ a = f;
+a = f;
+ d <= 89;
+ sdf = sdf;
+ adada => asda;
+ d ->> g;
+ aasd <<<= 3;
+ ccc %= 6;
+d *= b;
+g -= c;
+ end
+ endtask // a
+
+
+ property p_3;
+ a => ##3 !a;
+ a |=> ##1 !a;
+ a |-> ##2 !a;
+ endproperty
+ property p_2;
+ @(posedge clk) b |-> ##1 c;
+ endproperty
+ property p_1;
+ @(posedge clk) a |-> b;
+ endproperty
+
+ initial d;
+
+ // ap_1 assert property (p_1); FIXME
+ // ap_2 assert property (p_2);
+
+ property p_lane_output_change_on_input_change;
+ @(negedge test_clk)
+ disable iff (ana_byp == 0)
+ !$stable(lane_inputs) |-> !$stable(lane_outputs);
+ endproperty
+
+// Issue #940 - '=' in |=> , #=#, and [=n] operators should not mis-indent next line of continued expression
+property p_nonSequential;
+a |-> b[=n] ##0
+c;
+endproperty
+
+property p_nonOverlapFollowedBy;
+a #=#
+c;
+endproperty
+
+property p_nonBlockingImplication;
+a |=> b[*n] ##0
+c;
+endproperty
+
+
+endmodule
diff --git a/tests/indent_randcase.v b/tests/indent_randcase.v
new file mode 100644
index 0000000..6951d21
--- /dev/null
+++ b/tests/indent_randcase.v
@@ -0,0 +1,18 @@
+module aa;
+
+ int a,b,c;
+
+ initial begin
+ randcase
+ 10 : begin
+ a = 1;
+ end
+ 15 : begin
+ b = 0;
+ c = 5;
+ end
+ endcase // randcase
+
+ end // initial begin
+
+endmodule // a
diff --git a/tests/indent_random.v b/tests/indent_random.v
new file mode 100644
index 0000000..fa301ab
--- /dev/null
+++ b/tests/indent_random.v
@@ -0,0 +1,38 @@
+module top;
+ initial begin
+ // Test
+ $display("Hello world");
+ void'(std::randomize(foo) with {foo < 10;}; );
+ end
+endmodule // top
+/*
+ --------------------------
+
+It also appears to have indentation problems with the following variation:
+
+== The code: ==
+*/
+module top;
+
+ initial begin
+ // Test
+ $display("Hello world");
+ assert(std::randomize(foo) with {foo < 10;}; )
+ else $error("ERROR randomizing foo");
+ end
+endmodule // top
+/*
+
+------------------------------
+
+Also tried the following (removed semicolon after closing-curly-brace), and got same result:
+*/
+
+module top;
+
+ initial begin
+ // Test
+ $display("Hello world");
+ void'(std::randomize(foo) with {foo < 10;} );
+ end
+endmodule // top
diff --git a/tests/indent_struct.v b/tests/indent_struct.v
new file mode 100644
index 0000000..7074891
--- /dev/null
+++ b/tests/indent_struct.v
@@ -0,0 +1,45 @@
+module foo;
+
+ a = { g + c; };
+ a = c;
+
+ typedef struct {
+ reg r;
+ ahb_op_t op; // Read, write, etc.
+ ahb_cycle_type_t cti; // Cycle type for bursts
+ ahb_incr_type_t incr; // Increment type (for bursts)
+ bit b;
+ reg r;
+ ahb_thingy a;
+ bit [31:2] addr; // Starting address
+ bit [3:0] byte_sel; // Byte lane select
+ int len; // Length of transfer
+ bit [31:0] data[0:7]; // Write data
+ } ahb_req_t;
+
+ struct {
+ reg f;
+ xyzzy b;
+ };
+ struct packed {
+ int a; // ok
+ };
+ struct packed signed {
+ int a; // woops
+ };
+ struct packed unsigned {
+ int a; // woops
+ };
+
+endmodule // foo
+
+module foo (
+ input a;
+ input c;
+ output d;
+ );
+ always @(a) g;
+
+
+
+endmodule // foo
diff --git a/tests/indent_task.v b/tests/indent_task.v
new file mode 100644
index 0000000..c9bea0e
--- /dev/null
+++ b/tests/indent_task.v
@@ -0,0 +1,92 @@
+module foo;
+
+ // for each additional in-air txmacphy byte
+ task nextTxByte();
+ TxByteCnt++;
+ TxLastByteTime = $time;
+ endtask // nextTxByte
+ task automatic blah();
+ t;
+ endtask // blah
+ function static foo();
+ foo = 1;
+ endfunction // foo
+ // start counting when txmacphy sees first in-air byte
+ task firstTxByte();
+ TxByteCnt = 1;
+ TxFirstByteTime = $time;
+ TxLastByteTime = $time;
+ endtask // firstTxByte
+
+ // outputs the overall performance of the RX path in Mbps (MBits per second)
+ task printRxPerformance();
+ integer ibps;
+ real Mbps;
+ if( RxByteCnt && systemTop.intMonitor.frgRxedCnt >= 2 ) begin
+ ibps =
+ (RxByteCnt*8*1000000000)/(RxLastByteTime-RxFirstByteTime);
+ Mbps = ibps/1000000;
+ $display("%t: %s - RX average performance: %fMbps (Mbits/sec)",
+ $time, myName, Mbps );
+ end
+ else
+ $display("%t: %s - Requires >= 2 RX frames in order to measure performance", $time, myName);
+
+ endtask // printRxPerformance
+
+endmodule // foo
+
+class a;
+ virtual function void foo();
+ foo = 2;
+ endfunction // void
+ extern function void bar();
+ function fred();
+ aaa;
+ endfunction // fred
+
+ task foo;
+ endtask // endtask
+
+ virtual task foo;
+ endtask // endtask
+
+ generate g;
+ endgenerate
+
+ covergroup g;
+ endgroup // g
+
+ property p;
+ endproperty
+
+ sequence s;
+ endsequence // s
+
+ clocking c;
+ endclocking // c
+
+ function f;
+ endfunction //
+
+ virtual function f;
+ endfunction //
+
+ protected function f;
+ endfunction //
+
+endclass // a
+
+class base_test extends uvm_test;
+ `uvm_component_utils(base_test)
+ typedef virtual my_if my_vif_t;
+ // A task definition starting with the virtual keyword should not be
+ // detected as a declaration. This issue is seen when an attempt to indent
+ // each declaration is done (when the verilog-auto-lineup variable is set
+ // to 'declarations).
+ // In other words, the "task" in "virtual task" below must not be
+ // aligned with "my_if" in the "typedef virtual my_if.." line above.
+ virtual task run_phase(uvm_phase phase);
+ super.run_phase(phase);
+ endtask // run_phase
+endclass // base_test
diff --git a/tests/indent_task_func_decl.sv b/tests/indent_task_func_decl.sv
new file mode 100644
index 0000000..b5d5da8
--- /dev/null
+++ b/tests/indent_task_func_decl.sv
@@ -0,0 +1,90 @@
+typedef class burst_drv;
+
+class burst_drv extends vmm_xactor;
+
+ int EXECUTING;
+ int OBSERVED;
+ int SUB_OBSERVED;
+
+ protected burst_drv_cfg cfg;
+ local burst_drv_cfg reset_cfg;
+ protected burst_xn rx_factory;
+ local burst_xn reset_rx_factory;
+
+ burst_xn_channel in_chan;
+ burst_xn_channel obs_chan;
+
+ burst_xn tr_main; // Current transaction in main()
+ /* could have [extern] [virtual] [protected|local] task [static|automatic|] name (); */
+ /* If extern -> then it is complete; other wise it is not complete */
+ /* class could have:
+ class c
+ extern virtual static protected task t ();
+ endclass
+ task declaration could have
+ task static t();
+ endtask
+ */
+ class c;
+ endclass // c
+ function f();
+ g;
+ endfunction // f
+ generate g;
+ /* a lot of stuff */
+ endgenerate
+ task t();
+ /**/
+ /**/
+ endtask // t
+ protected virtual task pv_t();
+ /**/
+ endtask // pv_t
+
+ protected task p_t();
+ /* ACK*/
+ endtask // p_t
+ virtual task v_t();
+ /**/
+ endtask // v_t
+ virtual protected task vp_t();
+ /**/
+ endtask // vp_t
+ protected virtual task pv_t();
+ /**/
+ endtask // pv_t
+ extern task e_t();
+ extern virtual task ev_t();
+ extern protected task ep_t();
+ extern protected virtual task epv_t();
+ extern protected virtual task main();
+ generate g;
+ /**/
+ endgenerate
+
+ extern virtual function void reconfigure(burst_drv_cfg cfg);
+ extern virtual function void reset_xactor(reset_e rst_type = SOFT_RST);
+ extern virtual function new (
+ string inst,
+ int stream_id,
+ burst_drv_cfg cfg = null,
+ burst_xn_channel in_chan = null,
+ burst_xn_channel obs_chan = null,
+ burst_xn rx_factory = null);
+ virtual task start();
+ super.start();
+ this.tx_dma.start();
+ this.rx_dma.start();
+ endtask // start
+ task start();
+ super.start();
+ this.tx_dma.start();
+ this.rx_dma.start();
+ endtask // start
+ task static start();
+ super.start();
+ this.tx_dma.start();
+ this.rx_dma.start();
+ endtask // static
+endclass : burst_drv
+
diff --git a/tests/indent_typedef.sv b/tests/indent_typedef.sv
new file mode 100644
index 0000000..58fa310
--- /dev/null
+++ b/tests/indent_typedef.sv
@@ -0,0 +1,5 @@
+package p;
+typedef enum {a, b} type_t;
+typedef enum {TASK, TASK2} type2_t;
+typedef enum {Package, Class} type3_t;
+endpackage
diff --git a/tests/indent_unique_case-1.v b/tests/indent_unique_case-1.v
new file mode 100644
index 0000000..628d029
--- /dev/null
+++ b/tests/indent_unique_case-1.v
@@ -0,0 +1,366 @@
+module xxx_xxxxxx (input wire clk, input wire reset);
+
+ typedef enum reg [4:0] {IDLE, IIII, HHHHH,
+ AA_OP, AA_CMRD, AA_CMRD_WAIT, AA_RMW, AA_RMW_WAIT, AA_CMLLL, AA_CMLLL_WAIT, AA_NEXT,
+ BB_OP, BB_CMLLL, BB_CMLLL_WAIT, BB_NEXT,
+ CC_OP, CC_NEXT_OOOO,
+ DD_OP, DD_CMRD, DD_CMRD_WAIT, DD_ACCUM, DD_CMLLL, DD_CMLLL_WAIT,
+ EE_OP, EE_NEXT_OOOO,
+ FF_OP,
+ zxcvzxcv, cvbncvbn} xxxxxx_state_e;
+
+ xxxxxx_state_e current_state;
+
+ always_ff @ (posedge clk) begin
+ if (reset) begin
+ current_state <= IDLE;
+ end
+ else begin
+ unique case (current_state)
+
+ IDLE : begin
+ qwerty <= '0;
+
+ if (~qqq_empty)
+ current_state <= HHHHH;
+ end
+ AA_CMLLL : begin
+ lll_start <= 1'b1;
+
+ if (jjjj_left < 4)
+ lll_wcnt <= jjjj_left[2:0];
+ else
+ lll_wcnt <= FOUR[2:0];
+
+ current_state <= AA_CMLLL_WAIT;
+ end
+
+ HHHHH : begin
+ qqq_opiuy <= 1'b1;
+
+ if (qqq_opiuy) begin
+ qqq_opiuy <= '0;
+ current_state <= IIII;
+
+ end
+ end
+
+ AA_OP : begin
+ if (aa_pgm_err) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin
+ jjjj_left <= tgbyhn;
+
+ current_state <= AA_CMRD;
+ end
+ end
+
+ AA_CMRD : begin
+ uuuuu <= 1'b1;
+ current_state <= AA_CMRD_WAIT;
+ end
+ IIII : begin
+ qqq_opiuy <= '0;
+ if (err_iiii) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin
+ unique0 case (opm_cur)
+
+ `XXXCP : current_state <= AA_OP;
+ `XXXZR : current_state <= BB_OP;
+
+ default : current_state <= zxcvzxcv;
+ endcase // unique0 case
+
+ end // else: !if(err_iiii)
+ end // case: IIII
+
+ AA_CMRD_WAIT : begin
+ uuuuu <= '0;
+ if (kjkjkjkjk) begin
+ if (err_cmrd_par) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin
+ if (err_cmrd_csel) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin : assign_writecvbn
+ lllcvbn <= asdf ? ghjk : rdcvbn;
+ lll_par <= asdf ? cvbn : rd_par;
+
+ current_state <= AA_CMLLL;
+ end
+ end // else: !if(err_cmrd_par)
+ end // if (kjkjkjkjk)
+ end // case: AA_CMRD_WAIT
+
+ AA_CMLLL_WAIT : begin
+ lll_start <= '0;
+
+ if (lll_done) begin
+ if (alalala) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin
+ current_state <= AA_NEXT;
+ end
+ end
+ end // case: AA_CMLLL_WAIT
+
+
+
+ AA_NEXT : begin
+
+ if (qwerty) begin
+ qwerty <= '0;
+
+
+ unique case (opm_cur)
+
+ `XXXCP : current_state <= cvbncvbn;
+ `XXXSG : current_state <= CC_NEXT_OOOO;
+ default : current_state <= zxcvzxcv;
+ endcase // unique case
+
+ end // if (qwerty)
+ else begin
+ jjjj_left <= jjjj_left - 4;
+
+ current_state <= AA_CMRD;
+ end // else: !if(qwerty)
+ end // case: AA_NEXT
+
+ BB_OP : begin
+ if (bb_pgm_err) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin
+ lllcvbn <= '0;
+ lll_par <= '0;
+ jjjj_left <= tgbyhn;
+
+ current_state <= BB_CMLLL;
+ end
+ end // case: BB_OP
+
+
+
+ BB_CMLLL : begin
+ lll_start <= 1'b1;
+
+ if (jjjj_left <= 4) begin
+ lll_wcnt <= jjjj_left[2:0];
+ qwerty <= 1'b1;
+ end
+ else begin
+ lll_wcnt <= FOUR[2:0];
+ end
+
+ current_state <= BB_CMLLL_WAIT;
+ end // case: BB_CMLLL
+
+
+
+ BB_CMLLL_WAIT : begin
+ lll_start <= '0;
+
+ if (lll_done) begin
+ if (alalala) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin
+ current_state <= BB_NEXT;
+ end
+ end
+ end // case: BB_CMLLL_WAIT
+
+
+
+
+ BB_NEXT : begin
+ if (qwerty) begin
+ qwerty <= '0;
+ current_state <= cvbncvbn;
+ end
+ else begin
+ jjjj_left <= jjjj_left - 4;
+ current_state <= BB_CMLLL;
+ end
+ end
+
+
+
+
+
+
+ CC_OP : begin
+ jjjj_left_oooo <= tgbyhn;
+
+ if (tgbyhn <= oooo_cur) begin
+ last_oooo <= 1'b1;
+ jjjj_left <= tgbyhn;
+ end
+ else begin
+ jjjj_left <= oooo_cur;
+ end
+
+ current_state <= AA_CMRD;
+
+ end // case: CC_OP
+
+
+
+
+ CC_NEXT_OOOO : begin
+ if (last_oooo) begin
+ current_state <= cvbncvbn;
+ end
+ else begin
+
+ rd_rrrr <= rd_rrrr + ttttt_cur;
+ lll_rrrr <= lll_rrrr + oooo_cur;
+
+
+ if (jjjj_left_oooo <= oooo_cur) begin
+ last_oooo <= 1'b1;
+ jjjj_left <= jjjj_left_oooo;
+ end
+ else begin
+ jjjj_left <= oooo_cur;
+ end
+
+ current_state <= AA_CMRD;
+ end // else: !if(last_oooo)
+
+ end // case: CC_NEXT_OOOO
+
+
+
+
+
+ DD_OP : begin
+ accumulate_sum <= '0;
+ jjjj_left <= tgbyhn;
+
+ current_state <= DD_CMRD;
+ end
+
+
+ DD_CMRD : begin
+ uuuuu <= 1'b1;
+
+ if (jjjj_left <= 4) begin
+ qwerty <= 1'b1;
+ end
+
+ current_state <= DD_CMRD_WAIT;
+ end
+
+
+
+ DD_CMRD_WAIT : begin
+ uuuuu <= '0;
+
+ if (kjkjkjkjk) begin
+ if (zazaz) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin
+
+ current_state <= DD_ACCUM;
+ end
+ end
+ end // case: DD_CMRD_WAIT
+
+
+ DD_ACCUM : begin
+ if (qwerty) begin
+ current_state <= DD_CMLLL;
+ end
+ else begin
+ current_state <= DD_CMRD;
+ end
+ end
+
+
+
+ DD_CMLLL : begin
+ lll_start <= 1'b1;
+
+ current_state <= DD_CMLLL_WAIT;
+ end
+
+
+
+ DD_CMLLL_WAIT : begin
+ lll_start <= '0;
+
+ end
+
+
+
+
+ EE_OP : begin
+ jjjj_left_oooo <= tgbyhn;
+
+ current_state <= AA_CMRD;
+ end
+
+
+
+
+ EE_NEXT_OOOO : begin
+ if (last_oooo) begin
+ current_state <= cvbncvbn;
+ end
+ else begin
+
+ end
+ end
+
+
+
+ FF_OP : begin
+ asdf <= 1'b1;
+
+ current_state <= CC_OP;
+ end
+
+ zxcvzxcv : begin
+ current_state <= cvbncvbn;
+ end
+
+ cvbncvbn : begin
+ if (dci_cur) begin
+ current_state <= IDLE;
+ cmd_proc_done <= 1'b1;
+ end
+ else if (crq_ready) begin
+ crq_start <= 1'b1;
+ crqcvbn <= complcvbn;
+ crq_proc_id <= proc_id_cur;
+
+ current_state <= IDLE;
+ cmd_proc_done <= 1'b1;
+ end
+ end // case: cvbncvbn
+
+ default : begin
+ current_state <= IDLE;
+ cmd_proc_done <= 1'b1;
+ end
+ endcase // unique case
+ end // else: !if(reset)
+ end // always _ff
+
+
+
+endmodule // xxx_xxxxxx
+
+
+
+
+
diff --git a/tests/indent_unique_case-2.v b/tests/indent_unique_case-2.v
new file mode 100644
index 0000000..c42dcdb
--- /dev/null
+++ b/tests/indent_unique_case-2.v
@@ -0,0 +1,52 @@
+module testmod ();
+ always_comb begin
+ unique case (eeee)
+ ZERO[1:0] : begin
+ a = 1;
+ end // case: ZERO[1:0]
+
+ ONE[1:0] : begin
+ a = 1;
+ end // case: ONE[1:0]
+
+ TWO[1:0] : begin
+ a = 1;
+ end // case: TWO[1:0]
+ THREE[1:0] : begin
+ a = 1;
+ end // case: THREE[1:0]
+ endcase // unique case (eeee)
+ end // always_comb
+
+ always_ff @ (posedge clk) begin
+ if (reset) begin
+ current_state <= `TQ STATE0;
+ end // if (reset)
+ else begin
+ priority case (current_state)
+ STATE0 : begin
+ current_state <= `TQ STATE3;
+ end // case: STATE0
+
+ STATE1 : begin
+ current_state <= `TQ STATE3;
+ end // case: STATE1
+
+ STATE2 : begin
+ current_state <= `TQ STATE3;
+ end // case: STATE2
+
+ STATE3 : begin
+ current_state <= `TQ STATE0;
+ end // case: STATE3
+
+ default : current_state <= `TQ STATE0;
+ endcase // priority case (current_state)
+ end // else: !if(reset)
+ end // always_ff @
+
+endmodule // testmod
+
+
+
+
diff --git a/tests/indent_unique_case.v b/tests/indent_unique_case.v
new file mode 100644
index 0000000..b00dca6
--- /dev/null
+++ b/tests/indent_unique_case.v
@@ -0,0 +1,36 @@
+module foo;
+ // syntaxify the unique keyword correctly please...
+ always_comb (*) begin
+ case (f)
+ 1 : 2;
+ endcase // case (f)
+
+ unique case(vlcnum)
+ 0 : unique case(in.value1)
+ 0 : out = 1; 1 : out = 3; 2 : out = 3; 3 : out = 4;
+ 4 : out = 4; 5 : out = 5; 6 : out = 5; 7 : out = 6;
+ 8 : out = 6; 9 : out = 7; 10: out = 7; 11: out = 8;
+ 12 : out = 8; 13: out = 9; 14: out = 9; 15: out = 9;
+ endcase
+ 1 :
+ unique
+ case(in.value1)
+ 0 : out = 3;
+ 1 : out = 3;
+ 2 : out = 3;
+ 3 : out = 3;
+ 4 : out = 3;
+ 5 : out = 4;
+ 6 : out = 4;
+ 7 : out = 4;
+ 8 : out = 4;
+ 9 : out = 5;
+ 10 : out = 5;
+ 11 : out = 6;
+ 12 : out = 6;
+ 13 : out = 6;
+ 14 : out = 6;
+ endcase // case (in.value1)
+ endcase // case (in.value1)
+ end
+endmodule
diff --git a/tests/indent_uvm.v b/tests/indent_uvm.v
new file mode 100644
index 0000000..9dac869
--- /dev/null
+++ b/tests/indent_uvm.v
@@ -0,0 +1,70 @@
+module uvm;
+class simple_item extends uvm_sequence_item;
+ rand int unsigned addr;
+ rand int unsigned data;
+ rand int unsigned delay;
+ constraint c1 { addr < 16'h2000; }
+ constraint c2 { data < 16'h1000; }
+ // UVM automation macros for general objects
+ `uvm_object_utils_begin(simple_item)
+ a = b;
+ c = d;
+ `uvm_field_int(addr, UVM_ALL_ON)
+ `uvm_field_int(data, UVM_ALL_ON)
+ `uvm_field_int(delay, UVM_ALL_ON)
+ `uvm_object_utils_end
+ // Constructor
+ function new (string name = "simple_item");
+ super.new(name);
+ endfunction : new
+endclass : simple_item
+class mydata extends uvm_object;
+
+ string str;
+ mydata subdata;
+ int field;
+ myenum e1;
+ int queue[$];
+ `uvm_object_utils(mydata)
+ `uvm_object_utils_begin(mydata) //requires ctor with default args
+ `uvm_field_string(str, UVM_DEFAULT)
+ `uvm_field_object(subdata, UVM_DEFAULT)
+ `uvm_field_int(field, UVM_DEC) //use decimal radix
+ `uvm_field_enum(myenum, e1, UVM_DEFAULT)
+ `uvm_field_queue_int(queue, UVM_DEFAULT)
+ `uvm_object_utils_end
+ `uvm_object_param_utils_begin(mydata) //requires ctor with default args
+ `uvm_field_string(str, UVM_DEFAULT)
+ `uvm_field_object(subdata, UVM_DEFAULT)
+ `uvm_field_int(field, UVM_DEC) //use decimal radix
+ `uvm_field_enum(myenum, e1, UVM_DEFAULT)
+ `uvm_field_queue_int(queue, UVM_DEFAULT)
+ `uvm_object_utils_end
+endclass
+class my_trans extends uvm_sequence_item;
+
+ rand bit [127:0] data [];
+
+ //---> Configuration
+ `uvm_object_utils_begin(my_trans)
+ `uvm_field_array_int ( data, UVM_ALL_ON)
+ `uvm_object_utils_end
+
+ function new (string name = "my_trans", uvm_sequencer_base sequencer = null, uvm_sequence parent_seq = null);
+ super.new(name, sequencer, parent_seq);
+ endfunction : new
+endclass : my_trans
+endmodule // uvm
+
+module tt;
+
+ initial begin
+ while (1) begin
+ `uvm_do_with(aa, {bb == 0;})
+ `uvm_do(cc)
+ `uvm_do(cc)
+ end // while (1)
+ end // initial begin
+
+endmodule // tt
+
diff --git a/tests/indent_virtual_class.sv b/tests/indent_virtual_class.sv
new file mode 100644
index 0000000..6a162fb
--- /dev/null
+++ b/tests/indent_virtual_class.sv
@@ -0,0 +1,9 @@
+// issue 928 - 'pure virtual' items in classes break indentation
+package p:
+virtual class c extends parent;
+pure virtual protected task t(type_t a, type_t b);
+function f(string s="");
+blah;
+endfunction:f
+endclass
+endpackage
diff --git a/tests/indent_warren.v b/tests/indent_warren.v
new file mode 100644
index 0000000..450564a
--- /dev/null
+++ b/tests/indent_warren.v
@@ -0,0 +1,6 @@
+`include "x.h"
+//
+module x;
+ ////
+ reg y;
+endmodule // x
diff --git a/tests/inject_first.v b/tests/inject_first.v
new file mode 100644
index 0000000..bcf783a
--- /dev/null
+++ b/tests/inject_first.v
@@ -0,0 +1,19 @@
+module ex_inject (i, o);
+ input i;
+ input j;
+ output o;
+
+ // Ok:
+ always @ (j or i)
+ o = i | j;
+ // No change:
+ always @ (j) o = i | j;
+ always @ (j or i or p) o = i | j;
+ // Instant
+
+ autoinst_lopaz_srpad pad
+ (.pin(pin),
+ .foo(bar),
+ .clk(newclk));
+
+endmodule
diff --git a/tests/inject_inst_empty_ports.v b/tests/inject_inst_empty_ports.v
new file mode 100644
index 0000000..04f6e7a
--- /dev/null
+++ b/tests/inject_inst_empty_ports.v
@@ -0,0 +1,25 @@
+module inject_inst_empty_ports;
+ logic [7:0] q;
+ logic [7:0] d;
+ logic clk, rst_n;
+
+ register r1 (.q(q),
+ .qb(), // unconnect output
+ .d(d),
+ .clk(clk),
+ .rst_n(rst_n)
+ );
+endmodule
+
+module register (
+ output logic [7:0] q, qb,
+ input logic [7:0] d,
+ input logic clk, rst_n
+ );
+
+ always_ff @(posedge clk or negedge rst_n)
+ if (!rst_n) q <= '0;
+ else q <= d;
+
+ assign qb = ~q;
+endmodule
diff --git a/tests/inject_inst_endparen.v b/tests/inject_inst_endparen.v
new file mode 100644
index 0000000..8c8b378
--- /dev/null
+++ b/tests/inject_inst_endparen.v
@@ -0,0 +1,35 @@
+module inject_inst_endparen;
+ logic [7:0] q;
+ logic [7:0] d;
+ logic clk, nreset;
+
+ register r1 (.q(q),
+ .d(d),
+ .clk(clk),
+ // This is the
+ // asynchronous reset
+ .rst_n(nreset)
+ );
+
+`if NEVER
+ register r1 (.q(qKEEP),
+ .d(dKEEP),
+ .clk(clkKEEP),
+ // This is the
+ // asynchronous reset
+ .rst_n(nreset)
+ );
+`endif
+
+endmodule
+
+module register (
+ output logic [7:0] q,
+ input logic [7:0] d,
+ input logic clk, rst_n
+ );
+
+ always_ff @(posedge clk or negedge rst_n)
+ if (!rst_n) q <= '0;
+ else q <= d;
+endmodule
diff --git a/tests/inject_inst_net_case.v b/tests/inject_inst_net_case.v
new file mode 100644
index 0000000..3ae86e0
--- /dev/null
+++ b/tests/inject_inst_net_case.v
@@ -0,0 +1,33 @@
+module inject_inst_net_case (
+ output logic [7:0] q2,
+ input logic [7:0] d,
+ input logic clk, rst_n
+ );
+ logic [7:0] Q1;
+
+ register2 r2 (.q2(q2), .q1(Q1), .ck(clk), .rst_n(rst_n));
+
+ register1 r1 (.q1(Q1), .d(d), .ck(clk), .rst_n(rst_n));
+endmodule
+
+module register2 (
+ output logic [7:0] q2,
+ input logic [7:0] q1,
+ input logic ck, rst_n
+ );
+
+ always_ff @(posedge ck or negedge rst_n)
+ if (!rst_n) q2 <= '0;
+ else q2 <= q1;
+endmodule
+
+module register1 (
+ output logic [7:0] q1,
+ input logic [7:0] d,
+ input logic ck, rst_n
+ );
+
+ always_ff @(posedge ck or negedge rst_n)
+ if (!rst_n) q1 <= '0;
+ else q1 <= d;
+endmodule
diff --git a/tests/inject_inst_param.v b/tests/inject_inst_param.v
new file mode 100644
index 0000000..eed4d0d
--- /dev/null
+++ b/tests/inject_inst_param.v
@@ -0,0 +1,19 @@
+module inject_inst_param;
+ parameter WIDTH = 8;
+ logic [WIDTH-1:0] q;
+ logic [WIDTH-1:0] d;
+ logic clk, rst_n;
+
+ register #(.WIDTH(WIDTH)) r1 (.q(q), .d(d), .clk(clk), .rst_n(rst_n));
+endmodule
+
+module register #(parameter WIDTH=4) (
+ output logic [WIDTH-1:0] q,
+ input logic [WIDTH-1:0] d,
+ input logic clk, rst_n
+ );
+
+ always_ff @(posedge clk or negedge rst_n)
+ if (!rst_n) q <= '0;
+ else q <= d;
+endmodule
diff --git a/tests/inject_path.f b/tests/inject_path.f
new file mode 100644
index 0000000..61af226
--- /dev/null
+++ b/tests/inject_path.f
@@ -0,0 +1,3 @@
+inject_path.v
+inject_path_sub.v
+
diff --git a/tests/inject_path.v b/tests/inject_path.v
new file mode 100644
index 0000000..cf46f2f
--- /dev/null
+++ b/tests/inject_path.v
@@ -0,0 +1,12 @@
+module inject_path;
+ logic [7:0] q;
+ logic [7:0] d;
+ logic clk, rst_n;
+
+ register r1 (.q(q), .d(d), .clk(clk), .rst_n(rst_n));
+endmodule
+
+// Local Variables:
+// mode: Verilog
+// verilog-library-flags:("-f inject_path.f")
+// End:
diff --git a/tests/inject_path_cmt.v b/tests/inject_path_cmt.v
new file mode 100644
index 0000000..0d38233
--- /dev/null
+++ b/tests/inject_path_cmt.v
@@ -0,0 +1,18 @@
+module comments_test;
+ logic [7:0] q1;
+ logic [7:0] d;
+ logic clk, rst_n;
+
+ register r1 (.q(q1),
+ .d(d),
+ // 100MHz clk signal
+ .clk100(clk),
+ // Asynchronous reset
+ .rst_n(rst_n)
+ );
+endmodule
+
+// Local Variables:
+// mode: Verilog
+// verilog-library-flags:("-f inject_path.f")
+// End:
diff --git a/tests/inject_path_sub.v b/tests/inject_path_sub.v
new file mode 100644
index 0000000..9d719c3
--- /dev/null
+++ b/tests/inject_path_sub.v
@@ -0,0 +1,21 @@
+// Note module names don't match, this is intentional to check the .f file
+
+module reg_core (
+ output logic [7:0] q,
+ input logic [7:0] d,
+ input logic clk, rst_n
+ );
+
+ always_ff @(posedge clk or negedge rst_n)
+ if (!rst_n) q <= '0;
+ else q <= d;
+endmodule
+
+module register (
+ output logic [7:0] q,
+ input logic [7:0] d,
+ input logic clk, rst_n
+ );
+
+ reg_core c1 (.q(q), .d(d), .clk(clk), .rst_n(rst_n));
+endmodule
diff --git a/tests/inst.v b/tests/inst.v
new file mode 100644
index 0000000..47652cb
--- /dev/null
+++ b/tests/inst.v
@@ -0,0 +1,18 @@
+module inst (/*AUTOARG*/
+ // Outputs
+ lower_out,
+ // Inputs
+ lower_inb, lower_ina
+ );
+
+ parameter param1;
+ parameter param2;
+
+ input lower_inb;
+ input lower_ina;
+ output lower_out;
+
+ wire lower_out = lower_ina | lower_inb;
+
+endmodule
+
diff --git a/tests/label_always.v b/tests/label_always.v
new file mode 100644
index 0000000..828d2e3
--- /dev/null
+++ b/tests/label_always.v
@@ -0,0 +1,49 @@
+// bug 895 - labeling of always constructs
+module example;
+
+always
+begin
+end
+
+always @(posedge clk)
+begin
+end
+
+always @*
+begin
+end
+
+always @(*)
+begin
+end // always @ (*)
+
+always_comb
+begin
+end
+
+always_latch
+begin
+end
+
+always @( *)
+begin
+end
+
+always @(* )
+begin
+end
+
+always_ff @(posedge clk)
+begin
+end
+
+always @(*)
+begin
+end // garbage
+
+endmodule
+
+// Local Variables:
+// verilog-minimum-comment-distance: 1
+// verilog-auto-endcomments: t
+// End:
diff --git a/tests/label_class.sv b/tests/label_class.sv
new file mode 100644
index 0000000..b2cddbc
--- /dev/null
+++ b/tests/label_class.sv
@@ -0,0 +1,3 @@
+// Bug 888 -- verilog-label-be should remove existing comment labels before adding new ones
+class c;
+endclass // delete-me
diff --git a/tests/label_do.v b/tests/label_do.v
new file mode 100644
index 0000000..ec5d614
--- /dev/null
+++ b/tests/label_do.v
@@ -0,0 +1,12 @@
+// bug 842
+module x;
+
+do begin
+end while();
+
+endmodule
+
+// Local Variables:
+// verilog-minimum-comment-distance: 1
+// verilog-auto-endcomments: t
+// End:
diff --git a/tests/label_function.v b/tests/label_function.v
new file mode 100644
index 0000000..c7ffe4e
--- /dev/null
+++ b/tests/label_function.v
@@ -0,0 +1,66 @@
+module test();
+
+ // function with no lifetime, return-type, or port-list
+ function f0;
+ blah0;
+ endfunction
+
+ // empty port-list
+ function f1();
+ blah1;
+ endfunction
+
+ // non-empty portlist
+ function f2(stuff2);
+ blah2;
+ endfunction
+
+ // test that ": function_identifier" remains unscathed
+ function f3;
+ endfunction : f3
+
+ // return type
+ function void f4;
+ blah4;
+ endfunction
+
+ // return type with empty port-list.
+ function void f5();
+ int i;
+ begin
+ blah4;
+ end
+ endfunction
+
+ // return type, non-empty portlist
+ // also check that a stale auto-comment gets removed
+ function void f6(stuff,
+ that,
+ spans,
+ lines);
+ blah5;
+ endfunction // fX
+
+ // test lifetime keywords 'automatic' and 'static'
+ function automatic f7();
+ endfunction
+
+ // test a crazy-long function declaration
+ function static union packed signed {bit[1:0] a, bit[2:0] b} [5:0] f8(input ports, input ports, output ports);
+ endfunction
+
+ // port-list that doesn't start on the same line as the function declaration
+ function automatic void f9
+ (int a,
+ int b);
+ endfunction
+
+ // mismatched keyword
+ function f10;
+ endtask
+
+ // make sure previous screw-up doesn't affect future functions
+ function f11;
+ endfunction
+
+endmodule
diff --git a/tests/label_macro.v b/tests/label_macro.v
new file mode 100644
index 0000000..cdf5293
--- /dev/null
+++ b/tests/label_macro.v
@@ -0,0 +1,23 @@
+// Bug 859 -- 'end' should label after a user/library-defined macro
+// that isn't terminated with a semi-colon
+class c;
+
+`uvm_info(get_type_name(), "Digital power up.", UVM_MEDIUM)
+
+fork
+begin
+end
+join
+
+`made_up_macro (a, \
+ b, \
+ c)
+begin: named_block
+end
+
+endclass
+
+// Local Variables:
+// verilog-minimum-comment-distance: 1
+// verilog-auto-endcomments: t
+// End:
diff --git a/tests/label_no_indent.v b/tests/label_no_indent.v
new file mode 100644
index 0000000..6e3aa14
--- /dev/null
+++ b/tests/label_no_indent.v
@@ -0,0 +1,15 @@
+// bug 841
+module x;
+
+always @*
+begin
+end
+
+endmodule
+
+// Local Variables:
+// verilog-indent-level-module: 0
+// verilog-indent-begin-after-if: nil
+// verilog-minimum-comment-distance: 1
+// verilog-auto-endcomments: t
+// End:
diff --git a/tests/label_task.v b/tests/label_task.v
new file mode 100644
index 0000000..ed993a1
--- /dev/null
+++ b/tests/label_task.v
@@ -0,0 +1,51 @@
+module test();
+
+ // task with no lifetime, return-type, or port-list
+ task t0;
+ blah0;
+ endtask
+
+ // empty port-list
+ task t1();
+ blah1;
+ endtask
+
+ // non-empty portlist
+ task t2(stuff2);
+ blah2;
+ endtask
+
+ // test that ": task_identifier" remains unscathed
+ task t3;
+ endtask : t3
+
+ // check that stale auto-label is overwritten
+ task t4(input port1, output port2, inout port3);
+ begin
+ blah blah blah;
+ end
+ endtask // tX
+
+ // test lifetime keywords 'automatic' and 'static'
+ task static t7();
+ endtask
+
+ // test a more complete example
+ task automatic t8(input ports, input ports, output ports);
+ endtask
+
+ // port-list that doesn't start on the same line as the task declaration
+ task automatic t9
+ (int a,
+ int b);
+ endtask
+
+ // mismatched keyword
+ task t10;
+ endfunction
+
+ // make sure even the simplest test works after all the insanity
+ task t11;
+ endtask
+
+endmodule
diff --git a/tests/lavigne_instpath.v b/tests/lavigne_instpath.v
new file mode 100644
index 0000000..252da9d
--- /dev/null
+++ b/tests/lavigne_instpath.v
@@ -0,0 +1,28 @@
+module lavigne_instpath ();
+
+ /* lavigne_t1 AUTO_TEMPLATE (
+ .a(a1),
+ );
+ */
+ lavigne_t1 m1 (/*AUTOINST*/
+ // Inputs
+ .a (a1)); // Templated
+
+ /* lavigne_t2 AUTO_TEMPLATE (
+ .b(b2),
+ );
+ */
+
+ lavigne_t2 m2 (/*AUTOINST*/
+ // Inputs
+ .b (b2)); // Templated
+
+endmodule
+
+// verilkkkkkkkog-library-directories:("*/")
+
+//(load-file "/usr/local/common/site-lisp/local/verilog-mode.el")
+
+// Local Variables:
+// verilog-library-flags:("-y lavigne_instpath/")
+// End:
diff --git a/tests/lavigne_instpath/lavigne_t1.v b/tests/lavigne_instpath/lavigne_t1.v
new file mode 100644
index 0000000..6292b54
--- /dev/null
+++ b/tests/lavigne_instpath/lavigne_t1.v
@@ -0,0 +1,3 @@
+module lavigne_t1 (a);
+input a;
+endmodule
diff --git a/tests/lavigne_instpath/lavigne_t2.v b/tests/lavigne_instpath/lavigne_t2.v
new file mode 100644
index 0000000..8867ea7
--- /dev/null
+++ b/tests/lavigne_instpath/lavigne_t2.v
@@ -0,0 +1,3 @@
+module lavigne_t2 (b);
+input b;
+endmodule
diff --git a/tests/lineup.v b/tests/lineup.v
new file mode 100644
index 0000000..7342add
--- /dev/null
+++ b/tests/lineup.v
@@ -0,0 +1,3 @@
+module ocnSwitchClockGen(output reg ocnSwitchClock);
+ parameter ocnSwitchClockPeriod = 2000;
+ \ No newline at end of file
diff --git a/tests/local_vmode.x b/tests/local_vmode.x
new file mode 100644
index 0000000..036e344
--- /dev/null
+++ b/tests/local_vmode.x
@@ -0,0 +1,10 @@
+module local_vmode ();
+
+ local_vmode_sub sub (/*AUTOINST*/);
+
+endmodule
+
+// Local Variables:
+// mode: Verilog
+// verilog-library-flags:("+libext+.x")
+// End:
diff --git a/tests/local_vmode_sub.x b/tests/local_vmode_sub.x
new file mode 100644
index 0000000..ab2d4b4
--- /dev/null
+++ b/tests/local_vmode_sub.x
@@ -0,0 +1,6 @@
+module local_vmode_sub (input in);
+endmodule
+
+// Local Variables:
+// mode: Verilog
+// End:
diff --git a/tests/mac_autosense_dot.v b/tests/mac_autosense_dot.v
new file mode 100644
index 0000000..dcae5e6
--- /dev/null
+++ b/tests/mac_autosense_dot.v
@@ -0,0 +1,9 @@
+//From: Michael McNamara <mac@verilog.com>
+//Date: Tue, 27 Jun 2000 04:38:32 -0700 (PDT)
+module x;
+
+ always @ (/*AS*/top.agc_tool.adc_dta_i or top.agc_tool.adc_preagc_dta_i) begin
+ agctoolerr = top.agc_tool.adc_dta_i / top.agc_tool.adc_preagc_dta_i;
+ end
+
+endmodule
diff --git a/tests/mac_test2.sv b/tests/mac_test2.sv
new file mode 100644
index 0000000..9c00ca1
--- /dev/null
+++ b/tests/mac_test2.sv
@@ -0,0 +1,14 @@
+module foobar;
+
+ sequence s_1;
+ {txd, txdk} && (ppd == 3'b000) && !txe;
+ endsequence // s_1
+
+ sequence s_phy_transmitting;
+ {rxd, rxdk} &&
+ ((ppd == 3'b000) || (ppd == 3'b001))
+ && rxv;
+ endsequence // s_phy_transmitting
+
+
+endmodule
diff --git a/tests/mac_test2.v b/tests/mac_test2.v
new file mode 100644
index 0000000..9c00ca1
--- /dev/null
+++ b/tests/mac_test2.v
@@ -0,0 +1,14 @@
+module foobar;
+
+ sequence s_1;
+ {txd, txdk} && (ppd == 3'b000) && !txe;
+ endsequence // s_1
+
+ sequence s_phy_transmitting;
+ {rxd, rxdk} &&
+ ((ppd == 3'b000) || (ppd == 3'b001))
+ && rxv;
+ endsequence // s_phy_transmitting
+
+
+endmodule
diff --git a/tests/more_params.v b/tests/more_params.v
new file mode 100644
index 0000000..6eab7c5
--- /dev/null
+++ b/tests/more_params.v
@@ -0,0 +1,54 @@
+module InstName (/*AUTOARG*/
+ // Outputs
+ out,
+ // Inputs
+ in
+ );
+ input [7:0] in;
+ output [7:0] out;
+ wire [7:0] out = ~in;
+endmodule // bottm
+
+module top (/*AUTOARG*/
+ // Outputs
+ outgo,
+ // Inputs
+ incom
+ );
+ input [31:0] incom;
+ output [31:0] outgo;
+
+ /* AUTO_LISP(defun getparam2 (strg)
+ (string-match "[^0-9]*[0-9]+[^0-9]*\\([0-9]+\\)" strg)
+ (match-string 1 strg))*/
+ /* InstName AUTO_TEMPLATE (
+ .out (@),
+ .in (@"(getparam2 vl-cell-name)"),
+ );
+ */
+
+ InstName BT0_2 (/*AUTOINST*/
+ // Outputs
+ .out (0), // Templated
+ // Inputs
+ .in (2)); // Templated
+ InstName BT1_3 (/*AUTOINST*/
+ // Outputs
+ .out (1), // Templated
+ // Inputs
+ .in (3)); // Templated
+ InstName BT2_5 (/*AUTOINST*/
+ // Outputs
+ .out (2), // Templated
+ // Inputs
+ .in (5)); // Templated
+ InstName BT3_9 (/*AUTOINST*/
+ // Outputs
+ .out (3), // Templated
+ // Inputs
+ .in (9)); // Templated
+
+endmodule
+
+
+
diff --git a/tests/morrison.v b/tests/morrison.v
new file mode 100644
index 0000000..2971787
--- /dev/null
+++ b/tests/morrison.v
@@ -0,0 +1,16 @@
+`define XYZ 4'ha
+
+module test ();
+
+ always @(/*AUTOSENSE*/r or x)
+ begin
+ casex(x)
+ 5: d = {r, `XYZ };
+ endcase
+ end
+
+endmodule // test
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests/params_multiline_msg618.v b/tests/params_multiline_msg618.v
new file mode 100644
index 0000000..b02900e
--- /dev/null
+++ b/tests/params_multiline_msg618.v
@@ -0,0 +1,15 @@
+module testMultiLineParams (/*AUTOARG*/) ;
+`include "params_multiline_msg618_inc.vh"
+ reg comboIn, comboOut;
+
+ // expect AUTOSENSE to be comboIn only, no params
+ always @ ( /*AUTOSENSE*/comboIn) begin
+ comboOout = param1 & param2 & param3 & comboIn;
+ end
+
+endmodule // foo
+
+// Local Variables:
+// verilog-library-directories:(".")
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests/params_multiline_msg618_inc.vh b/tests/params_multiline_msg618_inc.vh
new file mode 100644
index 0000000..87ff6bf
--- /dev/null
+++ b/tests/params_multiline_msg618_inc.vh
@@ -0,0 +1,6 @@
+parameter
+// full line comment
+ param1 = 1'b1, // trailing comment
+ param2 = 1'b0, /* trailing comment */
+// full line comment
+ param3 = 1'b1;
diff --git a/tests/property_test.v b/tests/property_test.v
new file mode 100644
index 0000000..1f8a12e
--- /dev/null
+++ b/tests/property_test.v
@@ -0,0 +1,62 @@
+
+//////////////////////////////////////////////////////////////////////////////
+//
+// Main
+//
+//////////////////////////////////////////////////////////////////////////////
+
+
+module test();
+
+ integer count;
+ bit test_clk;
+
+
+ // Create a test clock
+ always #01.8 test_clk = ~test_clk;
+
+ //**********************************************************************
+ // Testing.
+ // Shift a moving set of ones up the input vector. At each shift
+ // the outputs should change, which is checked by the assertions
+ // below. This test doesnt care which output changes, as that was
+ // checked to be accurate by formal means.
+ //**********************************************************************
+
+ initial begin
+ count=0;
+ end
+
+ always @(posedge test_clk) begin
+ count++;
+ end
+
+ //**********************************************************************
+ // SV assertions
+ //**********************************************************************
+ property p_lane_output_change_on_input_change;
+ @(negedge test_clk)
+ disable iff (ana_byp == 0)
+ !$stable(lane_inputs) |-> !$stable(lane_outputs);
+ endproperty
+
+ a_lane_output_change_on_input_change: assert property (p_lane_output_change_on_input_change)
+ else begin
+ $error("ERROR! Analog Bypass: Input change not observed on the outputs: %h (lane)",
+ lane_inputs);
+ end // UNMATCHED !!
+ endproperty //FIXME
+
+ property p_sup_output_change_on_input_change;
+ @(negedge test_clk)
+ disable iff (ana_byp == 0)
+ !$stable(sup_inputs) |-> !$stable(sup_outputs);
+ endproperty
+
+ a_sup_output_change_on_input_change: assert property (p_sup_output_change_on_input_change)
+ else begin
+ $error("ERROR! Analog Bypass: Input change not observed on the outputs: %h (sup)",
+ sup_inputs);
+ end
+endproperty
+endmodule // test
diff --git a/tests/reversed_bits.v b/tests/reversed_bits.v
new file mode 100644
index 0000000..4786b3a
--- /dev/null
+++ b/tests/reversed_bits.v
@@ -0,0 +1,39 @@
+module lbnsub
+ (/*AUTOARG*/
+ // Outputs
+ outgo,
+ // Inputs
+ income
+ );
+
+ input [7:4] income;
+ output [7:4] outgo;
+
+ wire [7:4] outgo = income;
+
+endmodule
+
+module lbm
+ (/*AUTOARG*/
+ // Outputs
+ outgo,
+ // Inputs
+ income
+ );
+
+ input [7:4] income;
+ output [7:4] outgo;
+
+ /*
+ lbnsub AUTO_TEMPLATE (
+ // Inputs
+ .income (income[4:7]));
+ */
+
+ lbnsub lbnsub (/*AUTOINST*/
+ // Outputs
+ .outgo (outgo[7:4]),
+ // Inputs
+ .income (income[4:7])); // Templated
+endmodule
+
diff --git a/tests/set_membership.sv b/tests/set_membership.sv
new file mode 100644
index 0000000..f29f347
--- /dev/null
+++ b/tests/set_membership.sv
@@ -0,0 +1,40 @@
+import avm_pkg::*;
+import tinyalu_pkg::*;
+
+module top;
+
+ alu_operation req;
+ string msg;
+ integer i;
+
+ initial begin
+ $display ("---- A or B inside {0,8'hFF} ----");
+ for (i = 1; i<=5; i++) begin
+ req = new();
+ assert( a() with {A} );
+ req.randomize()
+ with
+ {
+ A inside {0,8'hFF};
+ B inside {0,8'hFF};
+ };
+$sformat (msg,"ALU Request: %s", req.convert2string());
+avm_report_message("TOP",msg);
+$display;
+$display ("---- op inside [add_op : mul_op] ----");
+
+for (i = 1; i<=10; i++) begin
+ req = new();
+ assert(
+ req.randomize() with
+ {
+ op inside {[add_op : mul_op]};
+ }
+ );
+$sformat (msg,"ALU Request: %s", req.convert2string());
+avm_report_message("TOP",msg);
+end // for (i = 1; i<=10; i++)
+end // initial begin
+ endmodule // req_reader
+
+
diff --git a/tests/singh.v b/tests/singh.v
new file mode 100644
index 0000000..50496fc
--- /dev/null
+++ b/tests/singh.v
@@ -0,0 +1,52 @@
+// HERE IS THE TEST CASE
+module bt (/*AUTOARG*/
+ // Outputs
+ out,
+ // Inputs
+ in
+ );
+ input [7:0] in;
+ output [7:0] out;
+
+ wire [7:0] out = ~in;
+endmodule // bottm
+
+module top (/*AUTOARG*/
+ // Outputs
+ outgo,
+ // Inputs
+ incom
+ );
+ input [31:0] incom;
+ output [31:0] outgo;
+
+ /* bt AUTO_TEMPLATE (
+ .in (incom[@"(+ (* 8 @) 7)":@"(* 8 @)"]),
+ .out (outgo[@"(concat (int-to-string (+ (* 8 @) 7)) \":\" (int-to-string ( * 8 @)))"]));
+ */
+
+ bt BT0 (/*AUTOINST*/
+ // Outputs
+ .out (outgo[7:0]), // Templated
+ // Inputs
+ .in (incom[7:0])); // Templated
+ bt BT1 (/*AUTOINST*/
+ // Outputs
+ .out (outgo[15:8]), // Templated
+ // Inputs
+ .in (incom[15:8])); // Templated
+ bt BT2 (/*AUTOINST*/
+ // Outputs
+ .out (outgo[23:16]), // Templated
+ // Inputs
+ .in (incom[23:16])); // Templated
+ bt BT3 (/*AUTOINST*/
+ // Outputs
+ .out (outgo[31:24]), // Templated
+ // Inputs
+ .in (incom[31:24])); // Templated
+
+endmodule // top
+
+
+
diff --git a/tests/sol_asense.v b/tests/sol_asense.v
new file mode 100644
index 0000000..69585b1
--- /dev/null
+++ b/tests/sol_asense.v
@@ -0,0 +1,98 @@
+module x (/*AUTOARG*/
+ // Inputs
+ MIERHW, MBOOTH_P, CEIopMADH_E_D2_R, CEIopMAZH_E_D2_R, DDATAH, DIV2HI, HI_R, MCLA, MCLASH,
+ MULTSHCYC, MULTUSCYC, HI_P
+ );
+
+ input [18:0] MIERHW;
+ integer i;
+ integer MTEMP1;
+ integer MTEMP2;
+ input MBOOTH_P;
+ input CEIopMADH_E_D2_R;
+ input CEIopMAZH_E_D2_R;
+ input DDATAH;
+ input DIV2HI;
+ input HI_R;
+ input MCLA;
+ input MCLASH;
+ input MULTSHCYC;
+ input MULTUSCYC;
+ input HI_P;
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ // End of automatics
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ // End of automatics
+
+ always @(/*AUTOSENSE*/MIERHW) begin
+
+ for (i=0; i<=5; i=i+1) begin
+
+ MTEMP1[3:0] = {MIERHW[i*3+3],
+ MIERHW[i*3+2],
+ MIERHW[i*3+1],
+ MIERHW[i*3+0]};
+
+ casex (MTEMP1)
+
+ 4'b0000: MTEMP2 = 4'b0101; // +0
+ 4'b0001: MTEMP2 = 4'b0001; // +1
+ 4'b0010: MTEMP2 = 4'b0001; // +1
+ 4'b0011: MTEMP2 = 4'b0010; // +2
+ 4'b0100: MTEMP2 = 4'b0010; // +2
+ 4'b0101: MTEMP2 = 4'b0100; // +3
+ 4'b0110: MTEMP2 = 4'b0100; // +3
+ 4'b0111: MTEMP2 = 4'b1000; // +4
+ 4'b1000: MTEMP2 = 4'b0111; // -4
+ 4'b1001: MTEMP2 = 4'b1011; // -3
+ 4'b1010: MTEMP2 = 4'b1011; // -3
+ 4'b1011: MTEMP2 = 4'b1101; // -2
+ 4'b1100: MTEMP2 = 4'b1101; // -2
+ 4'b1101: MTEMP2 = 4'b1110; // -1
+ 4'b1110: MTEMP2 = 4'b1110; // -1
+ 4'b1111: MTEMP2 = 4'b1010; // -0
+
+ endcase
+
+ end
+
+ {MBOOTH_P[i*4+3],
+ MBOOTH_P[i*4+2],
+ MBOOTH_P[i*4+1],
+ MBOOTH_P[i*4+0]} = MTEMP2[3:0];
+
+ end
+
+ // always @(/*AUTOnotSENSE*/
+ // __CEIopMADH_E_D2_R or __CEIopMAZH_E_D2_R or __DIV2HI or
+ // __MULTUSCYC or __MULTSHCYC or
+ // __DDATAH or __HI_R or __MCLA or __MCLASH) begin
+
+ // always @(/*AUTOSENSE*/DDATAH or HI_R or MCLA or MCLASH) begin
+`define DMCLASH MCLASH
+`define DCONST 1'b1
+ always @(/*AUTOSENSE*/CEIopMADH_E_D2_R or CEIopMAZH_E_D2_R or DDATAH or DIV2HI or MCLA or MCLASH
+ or MULTSHCYC or MULTUSCYC) begin
+
+ case (1'b1)
+ CEIopMADH_E_D2_R: HI_P = MCLA;
+ CEIopMAZH_E_D2_R: HI_P = MCLA;
+ DIV2HI: HI_P = DDATAH;
+ MULTUSCYC: HI_P = MCLA;
+ MULTSHCYC: HI_P = `DMCLASH;
+ default: HI_P = `DCONST;
+ endcase
+ end
+endmodule
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests/src_frag.vs b/tests/src_frag.vs
new file mode 100644
index 0000000..8a3df22
--- /dev/null
+++ b/tests/src_frag.vs
@@ -0,0 +1,77 @@
+module src_frag (
+ input logic inp_signal_0, // Input Signal 0
+ input logic inp_signal_1, // Input Signal 1
+ input logic inp_signal_2, // Input Signal 2
+ input logic [10:0] inp_signal_3; // Input Signal 3
+ input logic inp_signal_4, // Input Signal 4
+ output logic outp_signal_0, // Output Signal 0
+ inout logic test,
+ output logic outp_signal_1 // Output Signal 1
+ );
+
+ logic [7:0] local_0; // Local Signal 0
+ logic local_1; // Local Signal 1
+ logic local_3; // Local Signal 3
+ var logic local_4; // Local Signal 4
+ var logic local_5; // Local Signal 5
+ logic signed [1:0] local_6;
+
+ logic local_1; // Local Signal 1
+ input logic in_lg;
+ inout logic io_lg;
+ output logic o_lg;
+ ref logic r_lg;
+ const logic c_rg;
+ static logic s_rg;
+ protected logic p_lg;
+ local logic l_lg;
+ localparam logic lp_lg = 23;
+ parameter logic p_lg = 32;
+ typedef logic td_lg;
+ input wire foo;
+ logic local_3; // Local Signal 3
+ var logic local_5; // Local Signal 5
+ byte B;
+ shortint si;
+ int f;
+ longint li;
+ integer I;
+ int unsigned uI;
+ time t;
+ bit b;
+ logic l;
+ reg r;
+ shortreal sR;
+ real R;
+ realtime Rt;
+ supply0 s0;
+ supply1 s1;
+ tri tr;
+ triand tra;
+ trior tro;
+ trireg trr;
+ tri0 tr0;
+ tri1 tr1;
+ uwire uw;
+ wire w;
+ wand wa;
+ wor wo;
+ string s;
+ event e;
+ chandle ch;
+ virtual v;
+ enum en;
+ genvar g;
+ struct st;
+ union u;
+ mailbox mb;
+ semaphore sm;
+
+
+ defparam v_lg = 56;
+
+endmodule // src_frag
+
+// Local Variables:
+// mode: Verilog
+// End:
diff --git a/tests/subdir/flag_f_reeves_IBUF.v b/tests/subdir/flag_f_reeves_IBUF.v
new file mode 100644
index 0000000..364e4c8
--- /dev/null
+++ b/tests/subdir/flag_f_reeves_IBUF.v
@@ -0,0 +1,2 @@
+module flag_f_reeves_IBUF (input a, output q);
+endmodule
diff --git a/tests/sv_import.v b/tests/sv_import.v
new file mode 100644
index 0000000..447fced
--- /dev/null
+++ b/tests/sv_import.v
@@ -0,0 +1,7 @@
+module dpi_test ();
+ /* FIXME
+ import "DPI-C" context task c_task (input int i,
+ output int o);
+ logic [7:0] byte_array[1:20];
+ */
+endmodule // dpi_test
diff --git a/tests/t_autoinst_def_clk.v b/tests/t_autoinst_def_clk.v
new file mode 100644
index 0000000..87147a3
--- /dev/null
+++ b/tests/t_autoinst_def_clk.v
@@ -0,0 +1,41 @@
+module t_autoinst_def_clk
+ (/*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input a, // To sub of sub.v
+ input b, // To sub of sub.v
+ input clk, // To sub of sub.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output c // From sub of sub.v
+ // End of automatics
+ );
+
+ sub sub
+ (/*AUTOINST*/
+ // Outputs
+ .c (c),
+ // Inputs
+ .clk (clk),
+ .a (a),
+ .b (b));
+
+endmodule // sdc_wombat
+
+module sub
+ (input clk,
+
+ input a,
+ input b,
+
+ output c
+ );
+
+ clocking cb
+ @(posedge clk);
+ endclocking
+
+ default clocking cb;
+
+endmodule
diff --git a/tests/task.v b/tests/task.v
new file mode 100644
index 0000000..ed5b2c4
--- /dev/null
+++ b/tests/task.v
@@ -0,0 +1,14 @@
+module foo(input bit [3:0] def,
+ input bit ghi,
+ input bit [1:0] jkl);
+
+ task cba(input bit [3:0] a,
+ input b,
+ c);
+ endtask // cba
+ task abc(input bit [3:0] def,
+ input bit ghi,
+ input bit [1:0] jkl);
+
+ endtask // abc
+endmodule // foo
diff --git a/tests/testcase.sv b/tests/testcase.sv
new file mode 100644
index 0000000..1ccf7d8
--- /dev/null
+++ b/tests/testcase.sv
@@ -0,0 +1,17 @@
+`define moo 1
+class foo;
+ extern function void bar();
+endclass: foo
+
+function void foo::bar();
+ int variable;
+endfunction: bar
+
+`define moo 1
+class fu;
+ extern function void br();
+endclass: fu
+
+function void fu::br();
+ int variable;
+endfunction: br
diff --git a/tests/testcases.v b/tests/testcases.v
new file mode 100644
index 0000000..de76c0c
--- /dev/null
+++ b/tests/testcases.v
@@ -0,0 +1,217 @@
+//Verilint 182 off // WARNING: Illegal statement for synthesis: $realtobits (in1)
+//Verilint 311 off // WARNING: Converting real to unsigned: $realtobits (in1)
+//Verilint 20 off // WARNING: Assign statement may not be synthesizable: assign out7[i] = ...;
+//Verilint 599 off // WARNING: This construct is not supported by Synopsys
+//Verilint 433 off // WARNING: More than one top level module
+//Verilint 71 off // WARNING: Case statement without default clause
+
+module testmodule (/*AUTOARG*/
+ // Outputs
+ out1, out2, out3, out4, out5, out7, out8, outb2, outb3, outb4, outb6, outb7, outb8, outb9,
+ outb10, outw1, outw2, outw3,
+ // Inputs
+ in1, in2, in3, in4, in5
+ );
+
+
+ function [2:0] ffs;
+ input [2:0] in;
+ ffs = in & 3'b010;
+ endfunction
+
+ task show;
+ input [2:0] in;
+ begin
+ $display ("Hi %x", in);
+ end
+ endtask
+
+ input [2:0] in1,in2,in3,in4,in5;
+ output [2:0] out1, out2,out3,out4,out5,out7,out8;
+ output outb2,outb3,outb4,outb6,outb7,outb8,outb9,outb10;
+ output [7:0] outw1,outw2,outw3;
+ reg [2:0] memarry [0:2];
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg [2:0] out1;
+ reg [2:0] out2;
+ reg [2:0] out3;
+ reg [2:0] out4;
+ reg [2:0] out5;
+ reg [2:0] out8;
+ reg outb2;
+ reg outb3;
+ reg outb4;
+ reg outb6;
+ reg outb7;
+ reg [7:0] outw1;
+ reg [7:0] outw2;
+ reg [7:0] outw3;
+ // End of automatics
+
+ wire outb8=1'b1, outb9=|{in1[0],in2[0]}, outb10=1'b0;
+
+ always @(/*AUTOSENSE*/in1 or in2 or in3 or in4) begin
+ :ignore_label
+ out1 = $realtobits(in1);
+ out2 = ffs(in1 | (in2) );
+ out3 = ffs /*check*/ (in2);
+ $display ("chk ", in1);
+ show (in4);
+ if (|in3) out4=1; else out4=0;
+ end
+
+ always @ (/*AUTOSENSE*/in1 or in2 or in3 or in5) begin
+ casex ({in5[1:0], (3'b010==in2)})
+ 3'bx_1_0: out5=3'b000;
+ 3'bx_1_1: out5=3'b010;
+ 3'bx_0_x: out5=3'b100;
+ endcase
+ casex ({in3[in1]})
+ 1'bx: out5=3'b000;
+ endcase
+ end
+
+ /*AUTO_CONSTANT (`temp) */
+
+`define temp 3'b010
+ always @(/*AUTOSENSE*/in3) begin
+ outb6 = (in3 == `temp);
+ end
+
+ integer i;
+ reg [2:0] out7;
+ always @ (/*AUTOSENSE*/in1) begin
+ for (i=0; i<3; i=i+1) begin
+ assign out7[i] = ~in1[i];
+ end
+ end
+
+ always @ (/*AUTOSENSE*/in1 or in2 or in3) begin
+ {outw1 [ffs(in1)], outw2 [ffs(in2)]} = 2'b10;
+ {outw3[(|in1)?in2:in3], outb2} = 2'b10;
+ end
+
+ initial memarry[0] = in2;
+ always @ (/*AUTOSENSE*/ /*memory or*/ in1) begin
+ $display (memarry[in1]);
+ end
+
+ always @(/*AUTOSENSE*/in1 or in2)
+ casex(in1[1:0]) // synopsys full_case parallel_case
+ 2'b01 : out8 = 3'b001;
+ 2'b10 : out8 = 3'b010;
+ default
+ out8 = in2;
+ endcase
+
+ parameter READ = 3'b111,
+ //WRITE = 3'b111,
+ CFG = 3'b010;
+ //supply1 one;
+
+ always @(/*AUTOSENSE*/in1 or in2) begin
+ outb7 = (in1==READ) || (in2==CFG);
+ end
+
+ always @(/*AUTOSENSE*/in1) begin
+ if (|in1) $display("We're at %t\n",$time);
+ end // case: default
+
+`define shift_instr 5'b01011
+ always @(/*AUTOSENSE*/in1 or in2 or in3 or in4 or in5 or outw1)
+ /*AUTO_CONSTANT(`shift_instr)*/
+ begin: label_no_sense
+ casex (outw1) // synopsys full_case parallel_case
+ {`shift_instr,3'bxxx}:
+ outb3 = in3[0];
+ 8'b00001x10: outb3 = in4[0];
+ 8'b00110011:
+ if (in5[0])
+ outb3 = in1[0];
+ else
+ outb3 = in2[1];
+ default
+ outb3 = in4[0];
+ endcase
+ end
+
+ parameter WIDLE = 0; // No Manual Write Burst
+
+ always @ (/*AUTOSENSE*/in1 or in2 or in3 or in4) begin
+ case(1'b1)
+ in2[WIDLE]:
+ outb4 = in1[0];
+ in3[in4]:
+ outb4 = in1[0];
+ default:
+ outb4 = 1'bx;
+ endcase
+ end
+
+endmodule
+
+module darren_jones_2 (/*AUTOARG*/
+ // Outputs
+ next_WSTATE,
+ // Inputs
+ WSTATE
+ );
+ input [1:0] WSTATE;
+ output [1:0] next_WSTATE;
+ reg [1:0] next_WSTATE;
+ parameter
+ WIDLE = 0, // No Manual Write Burst
+ WCB0 = 1; // 1st of the 4 Manual Write Burst
+
+ always @ (/*AUTOSENSE*/WSTATE) begin
+ next_WSTATE = 2'b0;
+ case (1'b1)
+ WSTATE[WIDLE]:
+ next_WSTATE[1'b0] = 1'b1;
+ WSTATE[WCB0]:
+ next_WSTATE[WCB0] = 1'b1;
+ endcase
+ end
+endmodule
+
+module darren_jones_3 (/*AUTOARG*/
+ // Outputs
+ var1,
+ // Inputs
+ state
+ );
+ input [2:1] state;
+ output var1;
+ reg var1;
+
+ parameter
+ IDLE = 1,
+ CAS1 = 2;
+
+ always @(/*AUTOSENSE*/state) begin
+ case (1'b1)
+ state[IDLE] : begin
+ var1 = 1'b1;
+ end
+ state[CAS1] : begin
+ var1 = 1'b1;
+ end
+ default : begin
+ var1 = 1'b1;
+ end
+ endcase
+ end
+
+ always @(/*AUTOSENSE*/add or lo or mc_32pff or mc_losel or slo or var1) begin
+ case(mc_losel)
+ 6'b000001: lo_mux = mc_32pff ? {add[39:0],lo[31:8]} :
+ {add[7:0],lo[63:8]};
+
+ 6'b010000: lo_mux = lo;
+ 6'b100000: lo_mux = var1 ? IDLE : slo;
+ endcase
+ end // always @ (...
+
+endmodule
diff --git a/tests/tss_max32.v b/tests/tss_max32.v
new file mode 100644
index 0000000..5c62a31
--- /dev/null
+++ b/tests/tss_max32.v
@@ -0,0 +1,45 @@
+// $Id: tss_max32.v,v 1.6 1999/01/20 17:34:54 wsnyder Exp $
+//============================================================================
+
+`time_scale
+
+module tss_max32 (/*AUTOARG*/
+ // Outputs
+ max,
+ // Inputs
+ a, b
+ );
+
+ //======================================================================
+ // Inputs/Outputs
+ //======================================================================
+
+ input [31:0] a; // Time a
+ input [31:0] b; // Time b
+ output [31:0] max; // MAX (a,b)
+
+ //======================================================================
+ // Automatic Wire/Register Declarations
+ //======================================================================
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ // End of automatics
+
+ //======================================================================
+ // Comparison
+ //======================================================================
+
+ wire alessb; // a<b or carry
+ //Verilint 110 off // WARNING: Incompatible width
+ DW01_cmp2 #(31) cmp (.LT_LE(alessb), .GE_GT(unused_ok),
+ .A(a[30:0]),
+ .B(b[30:0]),
+ .LEQ(1'b0), .TC(1'b0));
+ //Verilint 110 on // WARNING: Incompatible width
+
+ // Note because a has more bits we MUST choose it if a[31:8]==b[31:8]!
+ wire sela = ((a[31] != b[31]) ^ alessb);
+ wire [31:0] max = (sela ? b : a);
+
+endmodule
diff --git a/tests/two_modules.v b/tests/two_modules.v
new file mode 100644
index 0000000..74500b1
--- /dev/null
+++ b/tests/two_modules.v
@@ -0,0 +1,69 @@
+// Example module that doesn't instantiate
+module appendix1 (/*AUTOARG*/
+ // Outputs
+ z,
+ // Inputs
+ i
+ );
+ input i;
+ output z;
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg z;
+ // End of automatics
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ // End of automatics
+
+ always @ (/*AUTOSENSE*/i) begin
+ z = i;
+ end
+endmodule
+
+// Example module that does instantiate
+module appendix2 (/*AUTOARG*/
+ // Outputs
+ z,
+ // Inputs
+ i
+ );
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input i; // To apx10 of appendix1.v, ...
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [11:10] z; // From apx10 of appendix1.v, ...
+ // End of automatics
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ // End of automatics
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ // End of automatics
+
+ /*
+ appendix1 AUTO_TEMPLATE (
+ .z (z[@]),
+ );
+ */
+
+ appendix1 apx10 (/*AUTOINST*/
+ // Outputs
+ .z (z[10]), // Templated
+ // Inputs
+ .i (i));
+
+ appendix1 apx11 (/*AUTOINST*/
+ // Outputs
+ .z (z[11]), // Templated
+ // Inputs
+ .i (i));
+
+endmodule
diff --git a/tests/v2k_inst_hicks.v b/tests/v2k_inst_hicks.v
new file mode 100644
index 0000000..6020861
--- /dev/null
+++ b/tests/v2k_inst_hicks.v
@@ -0,0 +1,28 @@
+
+// 2001 Parameter Style
+module v2k_inst_hicks (
+ output wire [7:0] relay,
+ output wire relay_f,
+ output wire swen_f0_n,
+ input [31:0] dcb,
+ input relay_ce,
+ input wire simReset,
+ input wire clock
+ );
+
+ input [31:0] dcb_n2k;
+
+ // AUTOINST results NOT OK
+ v2k_inst_hicks v2k_inst_hicks (/*AUTOINST*/
+ // Outputs
+ .relay (relay[7:0]),
+ .relay_f (relay_f),
+ .swen_f0_n (swen_f0_n),
+ // Inputs
+ .dcb (dcb[31:0]),
+ .relay_ce (relay_ce),
+ .simReset (simReset),
+ .clock (clock),
+ .dcb_n2k (dcb_n2k[31:0]));
+
+endmodule
diff --git a/tests/v2k_localparam.v b/tests/v2k_localparam.v
new file mode 100644
index 0000000..d28c845
--- /dev/null
+++ b/tests/v2k_localparam.v
@@ -0,0 +1,14 @@
+
+// 2001 Parameter Style
+module v2k_localparam;
+
+ localparam X = 10;
+ parameter Y = 10;
+
+ reg z;
+
+ always @ (/*AS*/) begin
+ z = X | Y;
+ end
+
+endmodule
diff --git a/tests/v2k_signed_kundsen.v b/tests/v2k_signed_kundsen.v
new file mode 100644
index 0000000..17df41a
--- /dev/null
+++ b/tests/v2k_signed_kundsen.v
@@ -0,0 +1,21 @@
+module foo_bar (/*AUTOARG*/
+ // Outputs
+ result,
+ // Inputs
+ clk, rst, data, addr
+ )
+
+ input clk;
+ input rst;
+ input signed [15:-15] data;
+ input [11:0] addr;
+ output signed [15:0] result;
+
+ wire signed [15:-15] data;
+ reg signed [15:0] result;
+
+ always @ (/*AS*/rst) begin
+ result = 32'sh22 | rst;
+ end
+
+endmodule // foo_bar
diff --git a/tests/v2k_typedef_yee.v b/tests/v2k_typedef_yee.v
new file mode 100644
index 0000000..a20c57f
--- /dev/null
+++ b/tests/v2k_typedef_yee.v
@@ -0,0 +1,82 @@
+
+`include "v2k_typedef_yee_inc.v"
+module v2k_typedef_yee
+ (/*AUTOARG*/
+ // Outputs
+ sub2_out_pixel, ready, sub1_to_sub2_and_top,
+ // Inputs
+ sub1_in_pixel, reset, pixel_ff, cp
+ );
+
+ //-----------------------
+ // Output definitions
+ //
+ output logic_t sub1_to_sub2_and_top; // Explicit output port
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output logic_t ready; // From itest_sub2 of v2k_typedef_yee_sub2.v
+ output pixel24_t sub2_out_pixel; // From itest_sub2 of v2k_typedef_yee_sub2.v
+ // End of automatics
+
+
+ //-----------------------
+ // Input definitions
+ //
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input logic_t cp; // To itest_sub1 of v2k_typedef_yee_sub1.v, ...
+ input pixel24_t pixel_ff; // To itest_sub2 of v2k_typedef_yee_sub2.v
+ input logic_t reset; // To itest_sub1 of v2k_typedef_yee_sub1.v, ...
+ input pixel24_t sub1_in_pixel; // To itest_sub1 of v2k_typedef_yee_sub1.v
+ // End of automatics
+
+
+ //-----------------------
+ // Wire definitions
+ //
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ pixel24_t sub1_out_pixel; // From itest_sub1 of v2k_typedef_yee_sub1.v
+ logic_t sub1_to_sub2; // From itest_sub1 of v2k_typedef_yee_sub1.v
+ // End of automatics
+
+
+
+ //-----------------------
+ // Module instantiations
+ //
+ v2k_typedef_yee_sub1 itest_sub1
+ (/*AUTOINST*/
+ // Outputs
+ .sub1_out_pixel (sub1_out_pixel),
+ .sub1_to_sub2 (sub1_to_sub2),
+ .sub1_to_sub2_and_top (sub1_to_sub2_and_top),
+ // Inputs
+ .sub1_in_pixel (sub1_in_pixel),
+ .cp (cp),
+ .reset (reset));
+
+ /*v2k_typedef_yee_sub2 AUTO_TEMPLATE (
+ .sub2_in_pixel (sub1_out_pixel),
+ )
+ */
+ v2k_typedef_yee_sub2 itest_sub2
+ (/*AUTOINST*/
+ // Outputs
+ .sub2_out_pixel (sub2_out_pixel),
+ .ready (ready),
+ // Inputs
+ .sub2_in_pixel (sub1_out_pixel), // Templated
+ .cp (cp),
+ .reset (reset),
+ .sub1_to_sub2 (sub1_to_sub2),
+ .sub1_to_sub2_and_top (sub1_to_sub2_and_top),
+ .pixel_ff (pixel_ff));
+
+
+endmodule
+
+// Local Variables:
+// verilog-typedef-regexp: "_t$"
+// End:
diff --git a/tests/v2k_typedef_yee_inc.v b/tests/v2k_typedef_yee_inc.v
new file mode 100644
index 0000000..aaf1d38
--- /dev/null
+++ b/tests/v2k_typedef_yee_inc.v
@@ -0,0 +1,28 @@
+`ifdef __TEST_I
+
+`else
+
+ `define __TEST_I
+
+ `ifdef TWO_STATE_LOGIC
+typedef bit logic_t; // Use two-state logic
+ `else
+typedef logic logic_t; // Use four-state logic
+ `endif
+
+typedef reg ff_t; // Default F/F type
+typedef reg lat_t; // Default latch type
+
+//----------------------------
+// 24 bit wide pixel types
+//
+typedef union packed {
+ logic_t [23:0] bits;
+ struct packed {
+ logic_t [7:0] red;
+ logic_t [7:0] grn;
+ logic_t [7:0] blu;
+ } color;
+ } pixel24_t;
+
+`endif
diff --git a/tests/v2k_typedef_yee_sub1.v b/tests/v2k_typedef_yee_sub1.v
new file mode 100644
index 0000000..d7fb658
--- /dev/null
+++ b/tests/v2k_typedef_yee_sub1.v
@@ -0,0 +1,29 @@
+
+`include "v2k_typedef_yee_inc.v"
+module v2k_typedef_yee_sub1
+ (
+ output pixel24_t sub1_out_pixel,
+ input pixel24_t sub1_in_pixel,
+ input logic_t cp,
+ input logic_t reset,
+ output logic_t sub1_to_sub2,
+ output logic_t sub1_to_sub2_and_top
+ );
+
+
+ pixel24_t pixel_ff;
+
+
+ always_ff @(posedge cp) begin
+ pixel_ff <= sub1_in_pixel;
+ end
+
+ assign sub1_out_pixel = pixel_ff;
+ assign sub1_to_sub2 = '1;
+ assign sub1_to_sub2_and_top = '1;
+
+endmodule
+
+// Local Variables:
+// verilog-typedef-regexp: "_t$"
+// End:
diff --git a/tests/v2k_typedef_yee_sub2.v b/tests/v2k_typedef_yee_sub2.v
new file mode 100644
index 0000000..83540f3
--- /dev/null
+++ b/tests/v2k_typedef_yee_sub2.v
@@ -0,0 +1,35 @@
+
+`include "v2k_typedef_yee_inc.v"
+module v2k_typedef_yee_sub2
+ (/*AUTOARG*/
+ // Outputs
+ sub2_out_pixel, ready,
+ // Inputs
+ sub2_in_pixel, cp, reset, sub1_to_sub2, sub1_to_sub2_and_top, pixel_ff
+ );
+
+ output pixel24_t sub2_out_pixel,
+ output logic_t ready,
+ input pixel24_t sub2_in_pixel,
+ input logic_t cp,
+ input logic_t reset,
+ input logic_t sub1_to_sub2,
+ input logic_t sub1_to_sub2_and_top
+
+ pixel24_t pixel_ff;
+ ff_t sub1_to_sub2_ff;
+
+
+ always_ff @(posedge cp) begin
+ pixel_ff <= sub2_in_pixel;
+ sub1_to_sub2_ff <= sub1_to_sub2;
+ end
+
+ assign sub2_out_pixel = pixel_ff;
+ assign ready = sub1_to_sub2_ff;
+
+endmodule
+
+// Local Variables:
+// verilog-typedef-regexp: "_t$"
+// End:
diff --git a/tests/verilint_113.v b/tests/verilint_113.v
new file mode 100644
index 0000000..d76096d
--- /dev/null
+++ b/tests/verilint_113.v
@@ -0,0 +1,26 @@
+module cdl_io (/*AUTOARG*/
+ // Outputs
+ topsig,
+ // Inputs
+ clk
+ );
+
+ input clk;
+ output topsig;
+
+ //Verilint 113 off // WARNING: in macro RSV_CDLBASE_RDWR, Multiple drivers to a flipflop
+
+ reg topsig;
+`define TOPSIG {topsig}
+
+ always @ (posedge clk) begin
+ `TOPSIG <= #0 1'b1;
+ end
+
+ task direct_write;
+ input val;
+ begin
+ `TOPSIG = val;
+ end
+ endtask
+endmodule
diff --git a/tests/vmm_regressions.sv b/tests/vmm_regressions.sv
new file mode 100644
index 0000000..ff5df4b
--- /dev/null
+++ b/tests/vmm_regressions.sv
@@ -0,0 +1,251 @@
+
+`include "vmm.sv"
+
+class my_xactor extends vmm_xactor;
+ typedef enum { AA, BB, CC } e_myenum;
+ typedef class t_mydata;
+ typedef class t_myclass;
+
+ int myint;
+ int myintarr[10];
+ int myintda[];
+ int myintaa_int[int];
+ int myintaa_str[string];
+
+ string mystr;
+ string mystrarr[10];
+ string mystrda[];
+ string mystraa_int[int];
+ string mystraa_str[string];
+
+ e_myenum myenum;
+ e_myenum myenumarr[10];
+ e_myenum myenumda[];
+ e_myenum myenumaa_int[int];
+ e_myenum myenumaa_str[string];
+
+ t_mydata mydata;
+ t_mydata mydataarr[10];
+ t_mydata mydatada[];
+ t_mydata mydataaa_int[int];
+ t_mydata mydataaa_str[string];
+
+ t_myclass myclass;
+ t_myclass myclassarr[10];
+ t_myclass myclassda[];
+ t_myclass myclassaa_int[int];
+ t_myclass myclassaa_str[string];
+
+ vmm_channel mych;
+ vmm_channel mycharr[10];
+ vmm_channel mychda[];
+ vmm_channel mychaa_int[int];
+ vmm_channel mychaa_str[string];
+
+ vmm_xactor myxact;
+ vmm_xactor myxactarr[10];
+ vmm_xactor myxactda[];
+ vmm_xactor myxactaa_int[int];
+ vmm_xactor myxactaa_str[string];
+
+ vmm_subenv mysub;
+ vmm_subenv mysubarr[10];
+ vmm_subenv mysubda[];
+ vmm_subenv mysubaa_int[int];
+ vmm_subenv mysubaa_str[string];
+
+ vmm_scenario mysc;
+
+ `vmm_data_member_begin(my_xactor)
+ `vmm_data_member_scalar(myint, DO_ALL)
+ `vmm_data_member_scalar_array(myintarr, DO_ALL )
+ `vmm_data_member_da(myintda, DO_ALL )
+ `vmm_data_member_scalar_aa_scalar(myintaa_int, DO_ALL )
+ `vmm_data_member_scalar_aa_string(myintaa_str, DO_ALL )
+
+ `vmm_data_member_string(mystr, DO_ALL)
+ `vmm_data_member_string_array(mystrarr, DO_ALL)
+ `vmm_data_member_string_da(mystrda, DO_ALL)
+ `vmm_data_member_string_aa_scalar(mystraa_int, DO_ALL)
+ `vmm_data_member_string_aa_string(mystraa_str, DO_ALL)
+
+ `vmm_data_member_enum(myenum, DO_ALL)
+ `vmm_data_member_enum_array(myenumarr, DO_ALL)
+ `vmm_data_member_enum_da(myenumda, DO_ALL)
+ `vmm_data_member_enum_aa_scalar(myenumaa_int, DO_ALL)
+ `vmm_data_member_enum_aa_string(myenumaa_str, DO_ALL)
+
+ `vmm_data_member_vmm_data(mydata, DO_ALL, DO_DEEP )
+ `vmm_data_member_vmm_data_array(mydataarr, DO_ALL, DO_DEEP )
+ `vmm_data_member_vmm_data_da(mydatada, DO_ALL, DO_DEEP )
+ `vmm_data_member_vmm_data_aa_scalar(mydataaa_int, DO_ALL, DO_DEEP )
+ `vmm_data_member_vmm_data_aa_string(mydataaa_str, DO_ALL, DO_DEEP )
+
+ `vmm_data_member_handle(myclass, DO_ALL )
+ `vmm_data_member_handle_array(myclassarr, DO_ALL )
+ `vmm_data_member_handle_da(myclassda, DO_ALL )
+ `vmm_data_member_handle_aa_scalar(myclassaa_int, DO_ALL )
+ `vmm_data_member_handle_aa_string(myclassaa_str, DO_ALL )
+ `vmm_data_member_end(my_xactor)
+
+ `vmm_env_member_begin(my_xactor)
+ `vmm_env_member_scalar(myint, DO_ALL)
+ `vmm_env_member_scalar_array(myintarr, DO_ALL )
+ `vmm_env_member_da(myintda, DO_ALL )
+ `vmm_env_member_scalar_aa_scalar(myintaa_int, DO_ALL )
+ `vmm_env_member_scalar_aa_string(myintaa_str, DO_ALL )
+
+ `vmm_env_member_string(mystr, DO_ALL)
+ `vmm_env_member_string_array(mystrarr, DO_ALL)
+ `vmm_env_member_string_da(mystrda, DO_ALL)
+ `vmm_env_member_string_aa_scalar(mystraa_int, DO_ALL)
+ `vmm_env_member_string_aa_string(mystraa_str, DO_ALL)
+
+ `vmm_env_member_enum(myenum, DO_ALL)
+ `vmm_env_member_enum_array(myenumarr, DO_ALL)
+ `vmm_env_member_enum_da(myenumda, DO_ALL)
+ `vmm_env_member_enum_aa_scalar(myenumaa_int, DO_ALL)
+ `vmm_env_member_enum_aa_string(myenumaa_str, DO_ALL)
+
+ `vmm_env_member_vmm_data(mydata, DO_ALL )
+ `vmm_env_member_vmm_data_array(mydataarr, DO_ALL )
+ `vmm_env_member_vmm_data_da(mydatada, DO_ALL )
+ `vmm_env_member_vmm_data_aa_scalar(mydataaa_int, DO_ALL )
+ `vmm_env_member_vmm_data_aa_string(mydataaa_str, DO_ALL )
+
+ `vmm_env_member_channel(mych, DO_ALL )
+ `vmm_env_member_channel_array(mycharr, DO_ALL )
+ `vmm_env_member_channel_da(mychda, DO_ALL )
+ `vmm_env_member_channel_aa_scalar(mychaa_int, DO_ALL )
+ `vmm_env_member_channel_aa_string(mychaa_str, DO_ALL )
+
+ `vmm_env_member_xactor(myxact, DO_ALL )
+ `vmm_env_member_xactor_array(myxactarr, DO_ALL )
+ `vmm_env_member_xactor_da(myxactda, DO_ALL )
+ `vmm_env_member_xactor_aa_scalar(myxactaa_int, DO_ALL )
+ `vmm_env_member_xactor_aa_string(myxactaa_str, DO_ALL )
+
+ `vmm_env_member_subenv(mysub, DO_ALL )
+ `vmm_env_member_subenv_array(mysubarr, DO_ALL )
+ `vmm_env_member_subenv_da(mysubda, DO_ALL )
+ `vmm_env_member_subenv_aa_scalar(mysubaa_int, DO_ALL )
+ `vmm_env_member_subenv_aa_string(mysubaa_str, DO_ALL )
+ `vmm_env_member_end(my_xactor)
+
+ `vmm_scenario_member_begin(my_xactor)
+ `vmm_scenario_member_scalar(myint, DO_ALL)
+ `vmm_scenario_member_scalar_array(myintarr, DO_ALL )
+ `vmm_scenario_member_da(myintda, DO_ALL )
+ `vmm_scenario_member_scalar_aa_scalar(myintaa_int, DO_ALL )
+ `vmm_scenario_member_scalar_aa_string(myintaa_str, DO_ALL )
+
+ `vmm_scenario_member_string(mystr, DO_ALL)
+ `vmm_scenario_member_string_array(mystrarr, DO_ALL)
+ `vmm_scenario_member_string_da(mystrda, DO_ALL)
+ `vmm_scenario_member_string_aa_scalar(mystraa_int, DO_ALL)
+ `vmm_scenario_member_string_aa_string(mystraa_str, DO_ALL)
+
+ `vmm_scenario_member_enum(myenum, DO_ALL)
+ `vmm_scenario_member_enum_array(myenumarr, DO_ALL)
+ `vmm_scenario_member_enum_da(myenumda, DO_ALL)
+ `vmm_scenario_member_enum_aa_scalar(myenumaa_int, DO_ALL)
+ `vmm_scenario_member_enum_aa_string(myenumaa_str, DO_ALL)
+
+ `vmm_scenario_member_vmm_data(mydata, DO_ALL, DO_DEEP )
+ `vmm_scenario_member_vmm_data_array(mydataarr, DO_ALL, DO_DEEP )
+ `vmm_scenario_member_vmm_data_da(mydatada, DO_ALL, DO_DEEP )
+ `vmm_scenario_member_vmm_data_aa_scalar(mydataaa_int, DO_ALL, DO_DEEP )
+ `vmm_scenario_member_vmm_data_aa_string(mydataaa_str, DO_ALL, DO_DEEP )
+
+ `vmm_scenario_member_handle(myclass, DO_ALL )
+ `vmm_scenario_member_handle_array(myclassarr, DO_ALL )
+ `vmm_scenario_member_handle_da(myclassda, DO_ALL )
+ `vmm_scenario_member_handle_aa_scalar(myclassaa_int, DO_ALL )
+ `vmm_scenario_member_handle_aa_string(myclassaa_str, DO_ALL )
+
+ `vmm_scenario_member_vmm_scenario(mysc, DO_ALL )
+ `vmm_scenario_member_end(my_xactor)
+
+ `vmm_subenv_member_begin(my_xactor)
+ `vmm_subenv_member_scalar(myint, DO_ALL)
+ `vmm_subenv_member_scalar_array(myintarr, DO_ALL )
+ `vmm_subenv_member_da(myintda, DO_ALL )
+ `vmm_subenv_member_scalar_aa_scalar(myintaa_int, DO_ALL )
+ `vmm_subenv_member_scalar_aa_string(myintaa_str, DO_ALL )
+
+ `vmm_subenv_member_string(mystr, DO_ALL)
+ `vmm_subenv_member_string_array(mystrarr, DO_ALL)
+ `vmm_subenv_member_string_da(mystrda, DO_ALL)
+ `vmm_subenv_member_string_aa_scalar(mystraa_int, DO_ALL)
+ `vmm_subenv_member_string_aa_string(mystraa_str, DO_ALL)
+
+ `vmm_subenv_member_enum(myenum, DO_ALL)
+ `vmm_subenv_member_enum_array(myenumarr, DO_ALL)
+ `vmm_subenv_member_enum_da(myenumda, DO_ALL)
+ `vmm_subenv_member_enum_aa_scalar(myenumaa_int, DO_ALL)
+ `vmm_subenv_member_enum_aa_string(myenumaa_str, DO_ALL)
+
+ `vmm_subenv_member_vmm_data(mydata, DO_ALL )
+ `vmm_subenv_member_vmm_data_array(mydataarr, DO_ALL )
+ `vmm_subenv_member_vmm_data_da(mydatada, DO_ALL )
+ `vmm_subenv_member_vmm_data_aa_scalar(mydataaa_int, DO_ALL )
+ `vmm_subenv_member_vmm_data_aa_string(mydataaa_str, DO_ALL )
+
+ `vmm_subenv_member_channel(mych, DO_ALL )
+ `vmm_subenv_member_channel_array(mycharr, DO_ALL )
+ `vmm_subenv_member_channel_da(mychda, DO_ALL )
+ `vmm_subenv_member_channel_aa_scalar(mychaa_int, DO_ALL )
+ `vmm_subenv_member_channel_aa_string(mychaa_str, DO_ALL )
+
+ `vmm_subenv_member_xactor(myxact, DO_ALL )
+ `vmm_subenv_member_xactor_array(myxactarr, DO_ALL )
+ `vmm_subenv_member_xactor_da(myxactda, DO_ALL )
+ `vmm_subenv_member_xactor_aa_scalar(myxactaa_int, DO_ALL )
+ `vmm_subenv_member_xactor_aa_string(myxactaa_str, DO_ALL )
+
+ `vmm_subenv_member_subenv(mysub, DO_ALL )
+ `vmm_subenv_member_subenv_array(mysubarr, DO_ALL )
+ `vmm_subenv_member_subenv_da(mysubda, DO_ALL )
+ `vmm_subenv_member_subenv_aa_scalar(mysubaa_int, DO_ALL )
+ `vmm_subenv_member_subenv_aa_string(mysubaa_str, DO_ALL )
+ `vmm_subenv_member_end(my_xactor)
+
+ `vmm_xactor_member_begin(my_xactor)
+ `vmm_xactor_member_scalar(myint, DO_ALL)
+ `vmm_xactor_member_scalar_array(myintarr, DO_ALL )
+ `vmm_xactor_member_da(myintda, DO_ALL )
+ `vmm_xactor_member_scalar_aa_scalar(myintaa_int, DO_ALL )
+ `vmm_xactor_member_scalar_aa_string(myintaa_str, DO_ALL )
+
+ `vmm_xactor_member_string(mystr, DO_ALL)
+ `vmm_xactor_member_string_array(mystrarr, DO_ALL)
+ `vmm_xactor_member_string_da(mystrda, DO_ALL)
+ `vmm_xactor_member_string_aa_scalar(mystraa_int, DO_ALL)
+ `vmm_xactor_member_string_aa_string(mystraa_str, DO_ALL)
+
+ `vmm_xactor_member_enum(myenum, DO_ALL)
+ `vmm_xactor_member_enum_array(myenumarr, DO_ALL)
+ `vmm_xactor_member_enum_da(myenumda, DO_ALL)
+ `vmm_xactor_member_enum_aa_scalar(myenumaa_int, DO_ALL)
+ `vmm_xactor_member_enum_aa_string(myenumaa_str, DO_ALL)
+
+ `vmm_xactor_member_vmm_data(mydata, DO_ALL )
+ `vmm_xactor_member_vmm_data_array(mydataarr, DO_ALL )
+ `vmm_xactor_member_vmm_data_da(mydatada, DO_ALL )
+ `vmm_xactor_member_vmm_data_aa_scalar(mydataaa_int, DO_ALL )
+ `vmm_xactor_member_vmm_data_aa_string(mydataaa_str, DO_ALL )
+
+ `vmm_xactor_member_channel(mych, DO_ALL )
+ `vmm_xactor_member_channel_array(mycharr, DO_ALL )
+ `vmm_xactor_member_channel_da(mychda, DO_ALL )
+ `vmm_xactor_member_channel_aa_scalar(mychaa_int, DO_ALL )
+ `vmm_xactor_member_channel_aa_string(mychaa_str, DO_ALL )
+
+ `vmm_xactor_member_xactor(myxact, DO_ALL )
+ `vmm_xactor_member_xactor_array(myxactarr, DO_ALL )
+ `vmm_xactor_member_xactor_da(myxactda, DO_ALL )
+ `vmm_xactor_member_xactor_aa_scalar(myxactaa_int, DO_ALL )
+ `vmm_xactor_member_xactor_aa_string(myxactaa_str, DO_ALL )
+ `vmm_xactor_member_end(my_xactor)
+
+endclass: my_xactor
diff --git a/tests/wasson.v b/tests/wasson.v
new file mode 100644
index 0000000..accc4de
--- /dev/null
+++ b/tests/wasson.v
@@ -0,0 +1,12 @@
+`define FOO 1'b1
+module foo(__a,b);
+
+ input __a;
+ output b;
+
+ always @(/*AUTOSENSE*/__a or `FOO) begin
+ b = __a ^ `FOO ;
+ end
+
+endmodule
+
diff --git a/tests/xx.v b/tests/xx.v
new file mode 100644
index 0000000..62cd672
--- /dev/null
+++ b/tests/xx.v
@@ -0,0 +1,13 @@
+always
+ @(w or c_int)
+ begin
+ if ((w == 1'b0) && ((status_register[7]) == 1'b1))
+ begin
+ write_protect <= `TRUE ;
+ end
+ if (w == 1'b1)
+ begin
+ write_protect <= `FALSE ;
+ end
+ end
+
diff --git a/tests_batch_ok/autoinout.v b/tests_batch_ok/autoinout.v
new file mode 100644
index 0000000..77b5576
--- /dev/null
+++ b/tests_batch_ok/autoinout.v
@@ -0,0 +1,67 @@
+module io1_sub(
+ /*AUTOARG*/
+ // Outputs
+ sec_out, lower_out,
+ // Inouts
+ sec_io, lower_io,
+ // Inputs
+ sec_ina, lower_ina
+ );
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input lower_ina; // To instio of instio.v
+ input sec_ina; // To instio of instio.v
+ // End of automatics
+
+ /*AUTOINOUT*/
+ // Beginning of automatic inouts (from unused autoinst inouts)
+ inout lower_io; // To/From instio of instio.v
+ inout sec_io; // To/From instio of instio.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output lower_out; // From instio of instio.v
+ output sec_out; // From instio of instio.v
+ // End of automatics
+
+ /* inst AUTO_TEMPLATE (
+ .lower_inb (1'b1),
+ )*/
+
+
+ instio instio (/*AUTOINST*/
+ // Outputs
+ .lower_out (lower_out),
+ .sec_out (sec_out),
+ // Inouts
+ .lower_io (lower_io),
+ .sec_io (sec_io),
+ // Inputs
+ .lower_ina (lower_ina),
+ .sec_ina (sec_ina));
+
+endmodule
+
+module instio (/*AUTOARG*/
+ // Outputs
+ lower_out, sec_out,
+ // Inouts
+ lower_io, sec_io,
+ // Inputs
+ lower_ina, sec_ina
+ );
+
+ input lower_ina;
+ inout lower_io;
+ output lower_out;
+ input sec_ina;
+ inout sec_io;
+ output sec_out;
+
+ wire lower_out = lower_ina | lower_io;
+ wire sec_out = sec_ina | sec_io;
+
+endmodule
+
diff --git a/tests_batch_ok/autoinst_lopaz.v b/tests_batch_ok/autoinst_lopaz.v
new file mode 100644
index 0000000..fb8337f
--- /dev/null
+++ b/tests_batch_ok/autoinst_lopaz.v
@@ -0,0 +1,76 @@
+module io1_sub(
+ /*AUTOARG*/);
+
+ wire [42:0] bscan_data; // boundary scan stitch
+ parameter bscan_count = 0;
+
+ assign bscan_data[0] = bscan_in;
+
+ /*
+ * Emacs template to auto instaniate MD[31:0] pads
+ */
+ /*
+ autoinst_lopaz_srpad AUTO_TEMPLATE (
+ .pin(MD[@]),
+ .pin_in({SDRAM_DQ_in[@],SDRAM_DQ_in[@]}),
+ .pin_out(SDRAM_DQ_out[@]),
+ .pin_outen(SDRAM_DQ_outen),
+ .sdrmode(SDRAM_single_rate),
+ .hw_enb(SDRAM_upper_word_enb),
+ .ff_rptr(SDRAM_ddr_inff_sel),
+ .ff_wptr(ddr_inff_enbH),
+ .clk(data_strobeH),
+ .bscan_so(bscan_data[@ + 1]),
+ .bscan_si(bscan_data[@]),
+ .bscan_shift(BScanShift),
+ .bscan_clock(BScanClock),
+ .bscan_mode(BScanMode),
+ .bscan_update(BScanUpdate),
+ .bscan_outen(SDRAM_DQ_bscan_outen),
+ );
+ */
+
+ autoinst_lopaz_srpad MD31_pad (/*AUTOINST*/
+ // Outputs
+ .pin_in ({SDRAM_DQ_in[31],SDRAM_DQ_in[31]}), // Templated
+ // Inouts
+ .pin (MD[31]), // Templated
+ // Inputs
+ .clk (data_strobeH), // Templated
+ .pin_out (SDRAM_DQ_out[31]), // Templated
+ .pin_outen (SDRAM_DQ_outen)); // Templated
+
+
+ /* autoinst_lopaz_srpad AUTO_TEMPLATE (
+ .pin(MD[@"num"]),
+ );
+ */
+
+ /*AUTO_LISP(setq num 1)*/
+ autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/
+ // Outputs
+ .pin_in (pin_in[2*w-1:0]),
+ // Inouts
+ .pin (MD[1]), // Templated
+ // Inputs
+ .clk (clk),
+ .pin_out (pin_out[w-1:0]),
+ .pin_outen (pin_outen));
+
+ /* autoinst_lopaz_srpad AUTO_TEMPLATE (
+ .pin(MD[@"num"]),
+ );
+ */
+
+ /*AUTO_LISP(setq num 2)*/
+ autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/
+ // Outputs
+ .pin_in (pin_in[2*w-1:0]),
+ // Inouts
+ .pin (MD[2]), // Templated
+ // Inputs
+ .clk (clk),
+ .pin_out (pin_out[w-1:0]),
+ .pin_outen (pin_outen));
+
+endmodule
diff --git a/tests_batch_ok/autoinst_star.v b/tests_batch_ok/autoinst_star.v
new file mode 100644
index 0000000..bd46af8
--- /dev/null
+++ b/tests_batch_ok/autoinst_star.v
@@ -0,0 +1,46 @@
+module io1_sub (/*AUTOARG*/);
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [w-1:0] pin; // To/From MD31_pad of autoinst_lopaz_srpad.v
+ wire [2*w-1:0] pin_in; // From MD31_pad of autoinst_lopaz_srpad.v, ...
+ wire templated; // To/From MD31_pad of autoinst_lopaz_srpad.v
+ // End of automatics
+
+ autoinst_lopaz_srpad MD31_pad
+ (.*,
+ .foo (touch_this_not_my_pretty));
+
+ /* autoinst_lopaz_srpad AUTO_TEMPLATE (
+ ); */
+
+ autoinst_lopaz_srpad MD31_pad
+ (.*);
+
+ /* autoinst_lopaz_srpad AUTO_TEMPLATE (
+ .pin (templated));
+ */
+
+ autoinst_lopaz_srpad MD31_pad
+ (.*,
+ // Outputs
+ // Inouts
+ .pin (templated) // Templated
+ );
+
+ // And .name with auto inst
+ autoinst_lopaz_srpad MD31_pad22
+ (.pin,
+ .clk,
+ /*AUTOINST*/
+ // Outputs
+ .pin_in (pin_in[2*w-1:0]),
+ // Inputs
+ .pin_out (pin_out[w-1:0]),
+ .pin_outen (pin_outen));
+
+ always @(posedge clk) begin
+ $display ("This .* shouldn't expand.\n");
+ end
+
+endmodule
diff --git a/tests_batch_ok/batch_li_parent.v b/tests_batch_ok/batch_li_parent.v
new file mode 100644
index 0000000..32c8081
--- /dev/null
+++ b/tests_batch_ok/batch_li_parent.v
@@ -0,0 +1,25 @@
+module batch_li_parent (/*AUTOARG*/
+ // Inputs
+ clk, rst
+ );
+
+ input rst;
+ input clk;
+
+ parameter WIDTH_0 = 8;
+ parameter WIDTH_1 = 16;
+
+ batch_li_child
+ #(.WIDTH_1 (WIDTH_0),
+ .WIDTH_0 (WIDTH_1))
+ child
+ (/*AUTOINST*/
+ // Inputs
+ .rst (rst),
+ .clk (clk));
+
+endmodule
+
+// Local Variables:
+// verilog-auto-arg-sort: t
+// End:
diff --git a/tests_ok/.gitignore b/tests_ok/.gitignore
new file mode 100644
index 0000000..e2ec6bf
--- /dev/null
+++ b/tests_ok/.gitignore
@@ -0,0 +1 @@
+0temp.v
diff --git a/tests_ok/abc.sv b/tests_ok/abc.sv
new file mode 100644
index 0000000..14bd9a2
--- /dev/null
+++ b/tests_ok/abc.sv
@@ -0,0 +1,20 @@
+
+covergroup CB;
+ a: coverpoint tr.a
+ {
+ bins a0 = {0};
+ bins a1 = {1};
+ option.weight=0;
+ }
+ b: coverpoint tr.b {
+ bins b0 = {0};
+ bins b1 = {1};
+ option.weight=0;
+ }
+ ab: cross a,b {
+ bins a0b0 = binsof(a.a0) && binsof(b.b0);
+ bins a1b0 = binsof(a.a1) && binsof(b.b0);
+ bins b0 = binsof(b.b0);
+ }
+endgroup // CB
+
diff --git a/tests_ok/auto_delete_whitespace.v b/tests_ok/auto_delete_whitespace.v
new file mode 100644
index 0000000..b6e5ec6
--- /dev/null
+++ b/tests_ok/auto_delete_whitespace.v
@@ -0,0 +1,12 @@
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Wilson Snyder.
+
+// Note intentional whitespace on following line
+// SPACES
+module x;
+ // TAB
+endmodule
+
+// Local Variables:
+// verilog-auto-delete-trailing-whitespace: t
+// End:
diff --git a/tests_ok/autoarg_comment.v b/tests_ok/autoarg_comment.v
new file mode 100644
index 0000000..8402ac6
--- /dev/null
+++ b/tests_ok/autoarg_comment.v
@@ -0,0 +1,17 @@
+module autoarg_comment
+
+ // Copyright 1997-1998, blah, blah, blah
+
+ (/*AUTOARG*/
+ // Outputs
+ outgo2,
+ // Inputs
+ income
+ );
+
+ //verilint 332 OFF //* Not all possible cases covered, but default case exists
+
+ input (* ATTRIB="val" *) income;
+ output outgo2;
+
+endmodule
diff --git a/tests_ok/autoarg_jwells_comment.v b/tests_ok/autoarg_jwells_comment.v
new file mode 100644
index 0000000..13a48a0
--- /dev/null
+++ b/tests_ok/autoarg_jwells_comment.v
@@ -0,0 +1,9 @@
+module tahoetop(/*AUTOARG*/);
+
+ /*AUTOWIRE*/
+
+
+ // the pad instance to look like "pads pads (/*AUTOINST*/". Then at
+ // diff the new against the old. Finally delete /*AUTOINST*/. This will
+
+endmodule
diff --git a/tests_ok/autoarg_quote_cmt.v b/tests_ok/autoarg_quote_cmt.v
new file mode 100644
index 0000000..26ae613
--- /dev/null
+++ b/tests_ok/autoarg_quote_cmt.v
@@ -0,0 +1,11 @@
+// bug360
+module f (/*AUTOARG*/
+ // Inputs
+ x
+ );
+
+ always @* r = "test/*";
+
+ input x;
+
+endmodule
diff --git a/tests_ok/autoarg_single.v b/tests_ok/autoarg_single.v
new file mode 100644
index 0000000..04a9e7d
--- /dev/null
+++ b/tests_ok/autoarg_single.v
@@ -0,0 +1,21 @@
+// msg1354
+module f (/*AUTOARG*/
+ // Outputs
+ o2,
+ o1,
+ // Inputs
+ z,
+ a,
+ q
+ );
+
+ output o2;
+ input z;
+ input a;
+ input q;
+ output o1;
+endmodule
+
+// Local Variables:
+// verilog-auto-arg-format:single
+// End:
diff --git a/tests_ok/autoarg_sort_fedeli.v b/tests_ok/autoarg_sort_fedeli.v
new file mode 100644
index 0000000..e8721d9
--- /dev/null
+++ b/tests_ok/autoarg_sort_fedeli.v
@@ -0,0 +1,16 @@
+module (/*AUTOARG*/
+ // Outputs
+ o1, o2,
+ // Inputs
+ a, q, z
+ );
+ output o2;
+ input z;
+ input a;
+ input q;
+ output o1;
+endmodule
+
+// Local Variables:
+// verilog-auto-arg-sort:t
+// End:
diff --git a/tests_ok/autoarg_string_bug259.v b/tests_ok/autoarg_string_bug259.v
new file mode 100644
index 0000000..c313508
--- /dev/null
+++ b/tests_ok/autoarg_string_bug259.v
@@ -0,0 +1,31 @@
+module bug_minimal
+ (input wire GND,
+ input wire VDD,
+
+ inout wire PIN1,
+ inout wire PIN2,
+ inout wire PIN3,
+ inout wire PIN4
+
+ /*AUTOARG*/);
+
+ // ----------------------------------------------------------------
+ /*AUTOWIRE*/
+
+ // ----------------------------------------------------------------
+ task force_value_to_1;
+ begin
+ $display("Enable test module checking ...");
+ force `value = 1'b1;
+ end
+ endtask
+
+ // ---------------------------------------------------------------
+ task force_value_to_0;
+ begin
+ $display("Disable test module checking ...");
+ force `value = 1'b0;
+ end
+ endtask
+
+endmodule
diff --git a/tests_ok/autoarg_supply_bug438.v b/tests_ok/autoarg_supply_bug438.v
new file mode 100644
index 0000000..bb795f2
--- /dev/null
+++ b/tests_ok/autoarg_supply_bug438.v
@@ -0,0 +1,28 @@
+module top
+ (
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input supply0 VDD, // To inst of inst_module.v
+ input supply1 VDD_from_child, // To inst of inst_module.v
+ input supply1 VSS, // To inst of inst_module.v
+ input non_supply // To inst of inst_module.v
+ // End of automatics
+ );
+
+ /*AUTOWIRE*/
+
+ inst_module inst (/*AUTOINST*/
+ // Inputs
+ .VDD (VDD),
+ .VSS (VSS),
+ .non_supply (non_supply),
+ .VDD_from_child (VDD_from_child));
+endmodule
+
+module inst_module (input supply0 VDD,
+ input supply1 VSS,
+ input non_supply,
+ input supply1 VDD_from_child
+ );
+
+endmodule
diff --git a/tests_ok/autoascii_myers.v b/tests_ok/autoascii_myers.v
new file mode 100644
index 0000000..aecafcf
--- /dev/null
+++ b/tests_ok/autoascii_myers.v
@@ -0,0 +1,76 @@
+module testit;
+ reg clk;
+ reg a_i;
+ reg b_i;
+
+ reg a_o;
+ reg b_o;
+ reg rst_n;
+
+ reg [7:0] shreg;
+
+
+ //== State enumeration
+ parameter [2:0] // synopsys enum state_info
+ SM_IDLE = 3'b000,
+ SM_SEND = 3'b001,
+ SM_WAIT1 = 3'b010;
+ //== State variables
+ reg [2:0] /* synopsys enum state_info */
+ state_r; /* synopsys state_vector state_r */
+ reg [2:0] /* synopsys enum state_info */
+ state_e1;
+
+ //== ASCII state decoding
+
+ /*AUTOASCIIENUM("state_r", "_stateascii_r", "sm_")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [39:0] _stateascii_r; // Decode of state_r
+ always @(state_r) begin
+ case ({state_r})
+ SM_IDLE: _stateascii_r = "idle ";
+ SM_SEND: _stateascii_r = "send ";
+ SM_WAIT1: _stateascii_r = "wait1";
+ default: _stateascii_r = "%Erro";
+ endcase
+ end
+ // End of automatics
+
+ initial begin
+ clk = 0;
+ a_i = 0;
+ b_i = 0;
+ rst_n = 0;
+ #20 rst_n = 1;
+ end
+ always #5 clk = ~clk;
+
+ always @(posedge clk or rst_n) begin
+ if (~rst_n) begin
+ a_o <= 0;
+ b_o <= 0;
+ shreg <= 8'b00110011;
+ end
+ else begin
+ a_o <= a_i;
+ b_o <= b_i;
+ shreg <= {shreg[6:0], shreg[7]};
+ end
+ end
+
+ task set_a_i;
+ begin
+ a_i = shreg[0];
+ end
+ endtask // set_a_i
+
+ always @(shreg & a_o) begin
+ set_a_i;
+ end
+
+ initial begin
+ $vcdpluson;
+ #500 $finish;
+ end
+
+endmodule // testit
diff --git a/tests_ok/autoascii_peltan.v b/tests_ok/autoascii_peltan.v
new file mode 100644
index 0000000..574c0fc
--- /dev/null
+++ b/tests_ok/autoascii_peltan.v
@@ -0,0 +1,37 @@
+module autoascii_peltan
+ (
+ input test,
+ output [1:0] test_out
+ );
+
+`include "autoascii_peltan_inc.v"
+
+ // Duplicate of what's in _inc
+ localparam [3:0] /* synopsys enum xstate */
+ state0 = 4'h0;
+
+ wire [3:0] /* synopsys enum xstate */
+ xstate;
+
+ /* synopsys translate off */
+
+ /*AUTOASCIIENUM("xstate", "v_xstate")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [47:0] v_xstate; // Decode of xstate
+ always @(xstate) begin
+ case ({xstate})
+ state0: v_xstate = "state0";
+ state1: v_xstate = "state1";
+ default: v_xstate = "%Error";
+ endcase
+ end
+ // End of automatics
+
+ /* synopsys translate on */
+
+endmodule // sample
+
+// Local Variables:
+// verilog-library-directories:(".")
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests_ok/autoascii_peltan_inc.v b/tests_ok/autoascii_peltan_inc.v
new file mode 100644
index 0000000..d0d0f70
--- /dev/null
+++ b/tests_ok/autoascii_peltan_inc.v
@@ -0,0 +1,3 @@
+localparam [3:0] /* synopsys enum xstate */
+ state0 = 4'h0,
+ state1 = 4'h1;
diff --git a/tests_ok/autoasciienum_auto.v b/tests_ok/autoasciienum_auto.v
new file mode 100644
index 0000000..417c397
--- /dev/null
+++ b/tests_ok/autoasciienum_auto.v
@@ -0,0 +1,43 @@
+// Code ok to distribute
+
+module autoasciienum_auto();
+
+ reg [2:0] /* auto enum sm_psm */ sm_psm;
+ reg [2:0] /* auto enum sm_ps2 */ sm_ps2;
+
+ localparam [2:0] // auto enum sm_psm
+ PSM_IDL = 0,
+ PSM_RST = 6,
+ PSM_ZOT = 7;
+
+ localparam [2:0] // auto enum sm_ps2
+ PS2_IDL = 0,
+ PS2_FOO = 1;
+
+ /*AUTOASCIIENUM("sm_psm", "_sm_psm__ascii", "_")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [47:0] _sm_psm__ascii; // Decode of sm_psm
+ always @(sm_psm) begin
+ case ({sm_psm})
+ PSM_IDL: _sm_psm__ascii = "psmidl";
+ PSM_RST: _sm_psm__ascii = "psmrst";
+ PSM_ZOT: _sm_psm__ascii = "psmzot";
+ default: _sm_psm__ascii = "%Error";
+ endcase
+ end
+ // End of automatics
+ /*AUTOASCIIENUM("sm_ps2", "_sm_ps2__ascii", "_")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [47:0] _sm_ps2__ascii; // Decode of sm_ps2
+ always @(sm_ps2) begin
+ case ({sm_ps2})
+ PS2_IDL: _sm_ps2__ascii = "ps2idl";
+ PS2_FOO: _sm_ps2__ascii = "ps2foo";
+ default: _sm_ps2__ascii = "%Error";
+ endcase
+ end
+ // End of automatics
+
+endmodule : autoasciienum_auto
+
+
diff --git a/tests_ok/autoasciienum_ex.v b/tests_ok/autoasciienum_ex.v
new file mode 100644
index 0000000..8faadc3
--- /dev/null
+++ b/tests_ok/autoasciienum_ex.v
@@ -0,0 +1,33 @@
+module sm (/*AUTOARG*/
+ // Outputs
+ state_e1, state_r
+ );
+
+ output [2:0] state_e1;
+ output [2:0] state_r;
+
+ //== State enumeration
+ parameter [2:0] // synopsys enum state_info
+ SM_IDLE = 3'b000,
+ SM_ACT = 3'b010;
+ //== State variables
+ reg [2:0] /* synopsys enum state_info */
+ state_r; /* synopsys state_vector state_r */
+ reg [2:0] /* synopsys enum state_info */
+ state_e1;
+
+ //== ASCII state decoding
+
+ /*AUTOASCIIENUM("state_r", "_stateascii_r", "sm_")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [31:0] _stateascii_r; // Decode of state_r
+ always @(state_r) begin
+ case ({state_r})
+ SM_IDLE: _stateascii_r = "idle";
+ SM_ACT: _stateascii_r = "act ";
+ default: _stateascii_r = "%Err";
+ endcase
+ end
+ // End of automatics
+
+endmodule
diff --git a/tests_ok/autoasciienum_frominc.v b/tests_ok/autoasciienum_frominc.v
new file mode 100644
index 0000000..fb66a28
--- /dev/null
+++ b/tests_ok/autoasciienum_frominc.v
@@ -0,0 +1,36 @@
+module sm (/*AUTOARG*/);
+
+ //==================== Constant declarations ==============
+
+`include "autoasciienum_param.v"
+
+ //==================== Intermediate Variables =============
+
+ reg [3:0] /* synopsys enum En_C14ChipNum */ chip_r;
+
+ //==================== DEBUG ASCII CODE =========================
+
+ /*AUTOASCIIENUM("chip_r", "chip_r__ascii","Ep_C14ChipNum_")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [31:0] chip_r__ascii; // Decode of chip_r
+ always @(chip_r) begin
+ case ({chip_r})
+ EP_C14ChipNum_RNP: chip_r__ascii = "rnp ";
+ EP_C14ChipNum_SPP: chip_r__ascii = "spp ";
+ EP_C14ChipNum_SRP: chip_r__ascii = "srp ";
+ EP_C14ChipNum_SMM2: chip_r__ascii = "smm2";
+ EP_C14ChipNum_SMM: chip_r__ascii = "smm ";
+ EP_C14ChipNum_TTE: chip_r__ascii = "tte ";
+ EP_C14ChipNum_DLE: chip_r__ascii = "dle ";
+ EP_C14ChipNum_OASP: chip_r__ascii = "oasp";
+ default: chip_r__ascii = "%Err";
+ endcase
+ end
+ // End of automatics
+
+endmodule
+
+//==== Emacs verilog-mode controls ====
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests_ok/autoasciienum_onehot.v b/tests_ok/autoasciienum_onehot.v
new file mode 100644
index 0000000..9e574bd
--- /dev/null
+++ b/tests_ok/autoasciienum_onehot.v
@@ -0,0 +1,56 @@
+// lint_checking MODLNM OFF
+
+module autoasciienum_onehot (
+ input clk,
+ input rst_n,
+ output ack
+ );
+
+ localparam // synopsys enum state_info
+ IDLE = 0,
+ S1 = 1,
+ S2 = 2,
+ S3 = 3,
+ DONE = 4;
+
+ reg [4:0] // synopsys enum state_info
+ cur_state, nxt_state;
+
+ always @ (*) begin
+ nxt_state = 5'h0;
+
+ case (1'b1)
+ cur_state[IDLE] : nxt_state[S1] = 1'b1;
+ cur_state[S1] : nxt_state[S2] = 1'b1;
+ cur_state[S2] : nxt_state[S3] = 1'b1;
+ cur_state[S3] : nxt_state[DONE] = 1'b1;
+ cur_state[DONE] : nxt_state[DONE] = 1'b1;
+ endcase
+ end
+
+ always @ (posedge clk or negedge rst_n)
+ if (rst_n == 1'b0) begin
+ cur_state <= 'h1;
+ end
+ else begin
+ cur_state <= nxt_state;
+ end
+
+ assign ack = cur_state[DONE];
+
+ /*AUTOASCIIENUM("cur_state", "cur_state_ascii")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [31:0] cur_state_ascii; // Decode of cur_state
+ always @(cur_state) begin
+ case ({cur_state})
+ (5'b1<<IDLE): cur_state_ascii = "idle";
+ (5'b1<<S1): cur_state_ascii = "s1 ";
+ (5'b1<<S2): cur_state_ascii = "s2 ";
+ (5'b1<<S3): cur_state_ascii = "s3 ";
+ (5'b1<<DONE): cur_state_ascii = "done";
+ default: cur_state_ascii = "%Err";
+ endcase
+ end
+ // End of automatics
+
+endmodule
diff --git a/tests_ok/autoasciienum_param.v b/tests_ok/autoasciienum_param.v
new file mode 100644
index 0000000..c0c3a2f
--- /dev/null
+++ b/tests_ok/autoasciienum_param.v
@@ -0,0 +1,16 @@
+
+`ifdef NOTDEFINED
+module just_for_proper_indentation ();
+`endif
+
+ //Verilint 175 off //WARNING: Unused parameter
+
+ parameter // synopsys enum En_C14ChipNum
+ EP_C14ChipNum_OASP = 4'h0,
+ EP_C14ChipNum_DLE = 4'h2,
+ EP_C14ChipNum_TTE = 4'h3,
+ EP_C14ChipNum_SMM = 4'h4,
+ EP_C14ChipNum_SMM2 = 4'h5,
+ EP_C14ChipNum_SRP = 4'h6,
+ EP_C14ChipNum_SPP = 4'h7,
+ EP_C14ChipNum_RNP = 4'h8;
diff --git a/tests_ok/autoasciienum_reed.v b/tests_ok/autoasciienum_reed.v
new file mode 100644
index 0000000..27c972b
--- /dev/null
+++ b/tests_ok/autoasciienum_reed.v
@@ -0,0 +1,52 @@
+
+module sm ();
+
+ localparam STATES = 7;
+
+ localparam /* synopsys enum states */
+ IDLE = 0, // '001
+ READ = 1, // '002
+ THINK = 2, // '004
+ SEND = 3, // '008
+ WAIT = 4, // '040
+ GET_ACK = 5, // '080
+ WAIT_REGBUS = 6; // '100
+
+ reg [STATES-1:0] /*synopsys enum states*/
+ state_i, state_r; /* synopsys state_vector state_r */
+
+ /*AUTOASCIIENUM("state_r","state_onehot,ascii_r","","onehot")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [87:0] state_onehot,ascii_r; // Decode of state_r
+ always @(state_r) begin
+ case ({state_r})
+ (7'b1<<IDLE): state_onehot,ascii_r = "idle ";
+ (7'b1<<READ): state_onehot,ascii_r = "read ";
+ (7'b1<<THINK): state_onehot,ascii_r = "think ";
+ (7'b1<<SEND): state_onehot,ascii_r = "send ";
+ (7'b1<<WAIT): state_onehot,ascii_r = "wait ";
+ (7'b1<<GET_ACK): state_onehot,ascii_r = "get_ack ";
+ (7'b1<<WAIT_REGBUS): state_onehot,ascii_r = "wait_regbus";
+ default: state_onehot,ascii_r = "%Error ";
+ endcase
+ end
+ // End of automatics
+
+ /*AUTOASCIIENUM("state_r","state_notonehot_ascii_r")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [87:0] state_notonehot_ascii_r;// Decode of state_r
+ always @(state_r) begin
+ case ({state_r})
+ IDLE: state_notonehot_ascii_r = "idle ";
+ READ: state_notonehot_ascii_r = "read ";
+ THINK: state_notonehot_ascii_r = "think ";
+ SEND: state_notonehot_ascii_r = "send ";
+ WAIT: state_notonehot_ascii_r = "wait ";
+ GET_ACK: state_notonehot_ascii_r = "get_ack ";
+ WAIT_REGBUS: state_notonehot_ascii_r = "wait_regbus";
+ default: state_notonehot_ascii_r = "%Error ";
+ endcase
+ end
+ // End of automatics
+
+endmodule
diff --git a/tests_ok/autoasciienum_sm.v b/tests_ok/autoasciienum_sm.v
new file mode 100644
index 0000000..bc7b914
--- /dev/null
+++ b/tests_ok/autoasciienum_sm.v
@@ -0,0 +1,95 @@
+module sm (/*AUTOARG*/
+ // Outputs
+ state_r,
+ // Inputs
+ clk, rst_
+ );
+
+ //==================== Constant declarations ==============
+
+ parameter [2:0] // synopsys enum state_info
+ IDLE = 3'b000,
+ SEND = 3'b001,
+ WAIT1 = 3'b010,
+ UPDATE1 = 3'b011,
+ WAIT2 = 3'b100;
+
+ parameter [2:0] /* synopsys enum state_info */ UPDATE2 = 3'b101;
+
+ parameter [2:0] NOT_A_STATE_ELEMENT = 3'b101;
+
+ parameter [2:0] /* synopsys enum other */
+ A_OTHER_STATE_ELEMENT = 3'b101;
+
+ //==================== Input Signals ======================
+
+ input clk; // System clock signal
+ input rst_;
+
+ //==================== Output Signals =====================
+
+ // s_ynopsys requires the enum comment between the keyword and the symbol While this seems silly,
+ // verilog requires this also to avoid misleading people that also use their tools.
+
+ output [2:0] state_r; // SM State information (to GPF)
+
+ //==================== Intermediate Variables =============
+
+ reg [2:0] /* synopsys enum state_info */ state_r; /* synopsys state_vector state_r */
+ reg [2:0] /* synopsys enum state_info */ state_e1; // next state of state-machine
+
+ //==================== Code Begin =========================
+
+ always @(/*AUTOSENSE*/state_r) begin
+ case(state_r) // synopsys full_case parallel_case
+ IDLE: begin
+ state_e1 = SEND;
+ end
+ SEND: begin
+ state_e1 = WAIT1;
+ end
+ WAIT1: begin
+ state_e1 = UPDATE1;
+ end
+ UPDATE1: begin
+ state_e1 = UPDATE2;
+ end
+ WAIT2: begin
+ state_e1 = UPDATE2;
+ end
+
+ UPDATE2: begin
+ state_e1 = IDLE;
+ end
+ default: state_e1 = state_r;
+ endcase
+ end
+
+ always @(posedge clk or negedge rst_) begin
+ if (~rst_) begin
+ state_r <= #0 IDLE;
+ end
+ else begin
+ state_r <= #0 state_e1;
+ end
+ end
+
+ //==================== DEBUG ASCII CODE =========================
+
+ /*AUTOASCIIENUM("state_r", "_stateascii_r")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [55:0] _stateascii_r; // Decode of state_r
+ always @(state_r) begin
+ case ({state_r})
+ IDLE: _stateascii_r = "idle ";
+ SEND: _stateascii_r = "send ";
+ WAIT1: _stateascii_r = "wait1 ";
+ UPDATE1: _stateascii_r = "update1";
+ WAIT2: _stateascii_r = "wait2 ";
+ UPDATE2: _stateascii_r = "update2";
+ default: _stateascii_r = "%Error ";
+ endcase
+ end
+ // End of automatics
+
+endmodule
diff --git a/tests_ok/autoconst_gesmith.v b/tests_ok/autoconst_gesmith.v
new file mode 100644
index 0000000..23a6973
--- /dev/null
+++ b/tests_ok/autoconst_gesmith.v
@@ -0,0 +1,20 @@
+module(/*AUTOARG*/)
+
+
+ always @(`ot.BOZ or
+ /*AUTOSENSE*/b)
+ begin
+ /*AUTO_CONSTANT(`ot.BOC) */
+ i = b;
+ c = `ot.BOC;
+ d = `ot.BOZ;
+ end
+
+ always @(/*AUTOSENSE*/b)
+ begin
+ /*AUTO_CONSTANT(ot.BOB) */
+ i = b;
+ c = ot.BOB;
+ end
+
+endmodule
diff --git a/tests_ok/autoconstant_gooch.v b/tests_ok/autoconstant_gooch.v
new file mode 100644
index 0000000..9bd8db9
--- /dev/null
+++ b/tests_ok/autoconstant_gooch.v
@@ -0,0 +1,102 @@
+module autoconstant_gooch
+ (/*AUTOARG*/
+ // Outputs
+ out1, out2, out3,
+ // Inputs
+ in1, in2, in3
+ );
+
+ input [3:0] in1;
+ input [3:0] in2;
+ input [3:0] in3;
+ output [3:0] out1;
+ reg [3:0] out1;
+ output [3:0] out2;
+ reg [3:0] out2;
+ output [3:0] out3;
+ reg [3:0] out3;
+
+
+
+ always @(/*AUTOSENSE*/in1 or in2 or in3)
+ begin
+ case (in1)
+ 4'b0001 : begin
+ out1 = in2;
+ end
+ 4'b0010 : begin
+ out1 = in2 + in3;
+ end
+ 4'b0100 : begin
+ out1 = in2 - in3;
+ end
+ 4'b1000 : begin
+ out1 = in2;
+ end
+ default : begin
+ out1 = {4{1'b0}};
+ end
+ endcase
+ end
+
+
+ always @(/*AUTOSENSE*/in1 or in2 or in3)
+ begin
+ case (in1)
+ 4'b0001 : begin
+ out2 = in2;
+ end
+ 4'b0010 : begin
+ out2 = in2 + in3;
+ end
+ 4'b0100 : begin
+ out2 = in2 - in3;
+ end
+ 4'b1000 : begin
+ out2 = in2;
+ end
+ default : begin
+ out2 = {4{1'b0}};
+ end
+ endcase
+ end
+
+
+ always @(/*AUTOSENSE*/in1 or in2 or in3)
+ begin
+ /* AUTO_CONSTANT( temp )*/
+ /* AxxxUTO_CONSTANT temp */
+ out3 = in1 + in2;
+ temp2 = temp;
+
+ // ERROR here - above constant definition is not
+ // correct - no braces - and so parser keeps looking
+ // for the first variable it finds between a pair of
+ // braces - in this case, in2. This in2 is now a
+ // "constant" and is removed from all sensitivity lists.
+ // ( in2 )
+
+ case (in1)
+ 4'b0001 : begin
+ out3 = in2;
+ end
+ 4'b0010 : begin
+ out3 = in2 + in3;
+ end
+ 4'b0100 : begin
+ out3 = in2 - in3;
+ end
+ 4'b1000 : begin
+ out3 = in2;
+ end
+ default : begin
+ out3 = {4{1'b0}};
+ end
+ endcase
+ end
+
+
+
+endmodule
+
+
diff --git a/tests_ok/autoinout.v b/tests_ok/autoinout.v
new file mode 100644
index 0000000..5850546
--- /dev/null
+++ b/tests_ok/autoinout.v
@@ -0,0 +1,67 @@
+module io1_sub(
+ /*AUTOARG*/
+ // Outputs
+ sec_out, lower_out,
+ // Inouts
+ sec_io, lower_io,
+ // Inputs
+ sec_ina, lower_ina
+ );
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input lower_ina; // To instio of instio.v
+ input sec_ina; // To instio of instio.v
+ // End of automatics
+
+ /*AUTOINOUT*/
+ // Beginning of automatic inouts (from unused autoinst inouts)
+ inout lower_io; // To/From instio of instio.v
+ inout sec_io; // To/From instio of instio.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output lower_out; // From instio of instio.v
+ output sec_out; // From instio of instio.v
+ // End of automatics
+
+ /* inst AUTO_TEMPLATE (
+ .lower_inb (1'b1),
+ )*/
+
+
+ instio instio (/*AUTOINST*/
+ // Outputs
+ .lower_out (lower_out),
+ .sec_out (sec_out),
+ // Inouts
+ .lower_io (lower_io),
+ .sec_io (sec_io),
+ // Inputs
+ .lower_ina (lower_ina),
+ .sec_ina (sec_ina));
+
+endmodule
+
+module instio (/*AUTOARG*/
+ // Outputs
+ lower_out, sec_out,
+ // Inouts
+ lower_io, sec_io,
+ // Inputs
+ lower_ina, sec_ina
+ );
+
+ input lower_ina;
+ inout lower_io;
+ output lower_out;
+ input sec_ina;
+ inout sec_io;
+ output sec_out;
+
+ wire lower_out = lower_ina | lower_io;
+ wire sec_out = sec_ina | sec_io;
+
+endmodule
+
diff --git a/tests_ok/autoinout_lovell.v b/tests_ok/autoinout_lovell.v
new file mode 100644
index 0000000..b52f140
--- /dev/null
+++ b/tests_ok/autoinout_lovell.v
@@ -0,0 +1,65 @@
+// Matthew Lovell <lovell@hp.com>
+
+module top_test(/*AUTOARG*/
+ // Outputs
+ ba, aa,
+ // Inputs
+ z, dc, db, da, \c-escaped-vec , \c-escaped-nvec , Z_int, Z0_int
+ );
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output aa; // From l1 of leaf.v
+ output ba; // From l1 of leaf.v
+ // End of automatics
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input [7:0] Z0_int; // To l1 of leaf.v
+ input [15:0] Z_int; // To l1 of leaf.v
+ input \c-escaped-nvec ; // To l1 of leaf.v
+ input [2:0] \c-escaped-vec ; // To l1 of leaf.v
+ input da; // To l1 of leaf.v
+ input [1:0] db; // To l1 of leaf.v
+ input [2:0] dc; // To l1 of leaf.v
+ input z; // To l1 of leaf.v
+ // End of automatics
+
+ /* leaf AUTO_TEMPLATE (
+ // Original reported bug
+ .a ({aa, test2.test3.no, test3.test4.no2}),
+ // Others
+ .b ( ~ ba),
+ .c ({\c-escaped-nvec , \c-escaped-vec [2:0] }),
+ .d ({da,~ db [1:0] , dc [2:0]}),
+ // Msg246
+ .e ({{4*1{1'b0}},Z_int[15:0],{1'b4{1'b0}},Z0_int[7:0]}),
+ .f (hi.ear.ial),
+ );
+ */
+ leaf l1 (/*AUTOINST*/
+ // Outputs
+ .a ({aa, test2.test3.no, test3.test4.no2}), // Templated
+ .b ( ~ ba), // Templated
+ // Inputs
+ .c ({\c-escaped-nvec , \c-escaped-vec [2:0] }), // Templated
+ .d ({da,~ db [1:0] , dc [2:0]}), // Templated
+ .e ({{4*1{1'b0}},Z_int[15:0],{1'b4{1'b0}},Z0_int[7:0]}), // Templated
+ .f (hi.ear.ial), // Templated
+ .z (z));
+endmodule // top_test
+
+module leaf(/*AUTOARG*/
+ // Outputs
+ a, b,
+ // Inputs
+ c, d, e, f, z
+ );
+ output a;
+ output b;
+ input c;
+ input d;
+ input e;
+ input f;
+ input z;
+endmodule
diff --git a/tests_ok/autoinout_ma.v b/tests_ok/autoinout_ma.v
new file mode 100644
index 0000000..b964d43
--- /dev/null
+++ b/tests_ok/autoinout_ma.v
@@ -0,0 +1,33 @@
+module foo
+ (
+ input soutb,
+ output sina,
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input sinb, // To i_bar of bar.v
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output souta // From i_bar of bar.v
+ // End of automatics
+ ) ;
+ bar i_bar(/*AUTOINST*/
+ // Outputs
+ .souta (souta),
+ .soutb (soutb),
+ // Inputs
+ .sina (sina),
+ .sinb (sinb));
+
+endmodule // foo
+
+module bar (/*AUTOARG*/
+ // Outputs
+ souta, soutb,
+ // Inputs
+ sina, sinb
+ ) ;
+ input sina, sinb;
+ output souta, soutb;
+endmodule // bar
diff --git a/tests_ok/autoinout_moller.v b/tests_ok/autoinout_moller.v
new file mode 100644
index 0000000..97314c3
--- /dev/null
+++ b/tests_ok/autoinout_moller.v
@@ -0,0 +1,49 @@
+module a ( /*AUTOARG*/
+ // Outputs
+ o1,
+ // Inouts
+ io1,
+ // Inputs
+ i1
+ ) ;
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input i1; // To b of b.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output o1; // From b of b.v
+ // End of automatics
+
+ /*AUTOINOUT*/
+ // Beginning of automatic inouts (from unused autoinst inouts)
+ inout io1; // To/From b of b.v
+ // End of automatics
+
+ b b
+ (/*AUTOINST*/
+ // Outputs
+ .o1 (o1),
+ // Inouts
+ .io1 (io1),
+ // Inputs
+ .i1 (i1));
+
+endmodule // a
+
+module b (/*AUTOARG*/
+ // Outputs
+ o1,
+ // Inouts
+ io1,
+ // Inputs
+ i1
+ ) ;
+
+ input i1 ;
+ output o1 ;
+ inout io1 ;
+
+endmodule // b
diff --git a/tests_ok/autoinout_regexp.v b/tests_ok/autoinout_regexp.v
new file mode 100644
index 0000000..c5e8286
--- /dev/null
+++ b/tests_ok/autoinout_regexp.v
@@ -0,0 +1,64 @@
+module io1_sub(
+ /*AUTOARG*/
+ // Outputs
+ sec_out,
+ // Inouts
+ sec_io,
+ // Inputs
+ sec_ina
+ );
+
+ /*AUTOINPUT("^s")*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input sec_ina; // To instio of instio.v
+ // End of automatics
+
+ /*AUTOINOUT("^s")*/
+ // Beginning of automatic inouts (from unused autoinst inouts)
+ inout sec_io; // To/From instio of instio.v
+ // End of automatics
+
+ /*AUTOOUTPUT("^s")*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output sec_out; // From instio of instio.v
+ // End of automatics
+
+ /* inst AUTO_TEMPLATE (
+ .lower_inb (1'b1),
+ )*/
+
+
+ instio instio (/*AUTOINST*/
+ // Outputs
+ .lower_out (lower_out),
+ .sec_out (sec_out),
+ // Inouts
+ .lower_io (lower_io),
+ .sec_io (sec_io),
+ // Inputs
+ .lower_ina (lower_ina),
+ .sec_ina (sec_ina));
+
+endmodule
+
+module instio (/*AUTOARG*/
+ // Outputs
+ lower_out, sec_out,
+ // Inouts
+ lower_io, sec_io,
+ // Inputs
+ lower_ina, sec_ina
+ );
+
+ input lower_ina;
+ inout lower_io;
+ output lower_out;
+ input sec_ina;
+ inout sec_io;
+ output sec_out;
+
+ wire lower_out = lower_ina | lower_io;
+ wire sec_out = sec_ina | sec_io;
+
+endmodule
+
diff --git a/tests_ok/autoinout_v2k.v b/tests_ok/autoinout_v2k.v
new file mode 100644
index 0000000..60398c4
--- /dev/null
+++ b/tests_ok/autoinout_v2k.v
@@ -0,0 +1,105 @@
+module parent
+ (
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input [3:0] a2, // To sub_module of child_a.v
+ input [3:0] a3, // To sub_module of child_a.v
+ input clk, // To sub_module of child_a.v, ...
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output d, // From sub_module of child_a.v
+ // End of automatics
+
+ /*AUTOINOUT*/
+ // Beginning of automatic inouts (from unused autoinst inouts)
+ inout [5:0] c, // To/From sub_module of child_a.v, ...
+ inout [5:0] c2, // To/From sub_module of child_a.v, ...
+ inout c3 // To/From sub_module of child_a.v, ...
+ // End of automatics
+ );
+
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [3:0] a; // From sub_module of child_b.v
+ wire [3:0] a4; // From sub_module of child_b.v
+ wire [2:0] b; // From sub_module of child_a.v
+ wire [2:0] b2; // From sub_module of child_a.v
+ wire [2:0] b3; // From sub_module of child_a.v
+ wire [2:0] b4; // From sub_module of child_a.v
+ // End of automatics
+
+
+ child_a sub_module
+ (/*AUTOINST*/
+ // Outputs
+ .b (b[2:0]),
+ .b2 (b2[2:0]),
+ .b3 (b3[2:0]),
+ .b4 (b4[2:0]),
+ .d (d),
+ // Inouts
+ .c (c[5:0]),
+ .c2 (c2[5:0]),
+ .c3 (c3),
+ // Inputs
+ .a (a[3:0]),
+ .a2 (a2[3:0]),
+ .a3 (a3[3:0]),
+ .a4 (a4[3:0]),
+ .clk (clk));
+
+ child_b sub_module
+ (/*AUTOINST*/
+ // Outputs
+ .a (a[3:0]),
+ .a4 (a4[3:0]),
+ // Inouts
+ .c (c[5:0]),
+ .c2 (c2[5:0]),
+ .c3 (c3),
+ // Inputs
+ .b (b[2:0]),
+ .b2 (b2[2:0]),
+ .b3 (b3[2:0]),
+ .b4 (b4[2:0]),
+ .clk (clk));
+
+endmodule // parent
+
+module child_a
+ (
+ input [3:0] a,
+ input [3:0] a2,
+ input [3:0] a3,
+ input [3:0] a4,
+ inout [5:0] c,
+ inout [5:0] c2,
+ inout c3,
+ output [2:0] b,
+ output [2:0] b2,
+ output [2:0] b3,
+ output [2:0] b4,
+ input clk,
+ output d
+ );
+endmodule
+
+
+module child_b
+ (
+ output [3:0] a,
+ output [3:0] a4,
+ inout [5:0] c,
+ inout [5:0] c2,
+ inout c3,
+ input [2:0] b,
+ input [2:0] b2,
+ input [2:0] b3,
+ input [2:0] b4,
+ input clk
+ );
+endmodule
diff --git a/tests_ok/autoinoutcomp.v b/tests_ok/autoinoutcomp.v
new file mode 100644
index 0000000..d3f17f1
--- /dev/null
+++ b/tests_ok/autoinoutcomp.v
@@ -0,0 +1,20 @@
+module autoinoutmodule (/*AUTOARG*/
+ // Outputs
+ lower_ina, lower_inb,
+ // Inputs
+ lower_out
+ );
+
+ output lower_inb;
+
+ /*AUTOINOUTCOMP("inst")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output lower_ina;
+ input lower_out;
+ // End of automatics
+ // Beginning of automatic in/out/inouts (from specific module)
+
+ wire lower_out = lower_ina | lower_inb;
+
+endmodule
+
diff --git a/tests_ok/autoinoutin.v b/tests_ok/autoinoutin.v
new file mode 100644
index 0000000..508bb16
--- /dev/null
+++ b/tests_ok/autoinoutin.v
@@ -0,0 +1,14 @@
+module autoinoutin (/*AUTOARG*/
+ // Inputs
+ lower_inb, lower_ina, lower_out
+ );
+
+ /*AUTOINOUTIN("inst")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ input lower_inb;
+ input lower_ina;
+ input lower_out;
+ // End of automatics
+
+endmodule
+
diff --git a/tests_ok/autoinoutmodport_bourduas_type.v b/tests_ok/autoinoutmodport_bourduas_type.v
new file mode 100644
index 0000000..f7d204a
--- /dev/null
+++ b/tests_ok/autoinoutmodport_bourduas_type.v
@@ -0,0 +1,41 @@
+//-*- mode: Verilog; verilog-indent-level: 3; indent-tabs-mode: nil; tab-width: 1 -*-
+
+module apl2c_connect(autoinoutmodport_type_intf ctl_i,
+ /*AUTOINOUTMODPORT("autoinoutmodport_type_intf", "ctl_cb")*/
+ // Beginning of automatic in/out/inouts (from modport)
+ input [4:0] inst,
+ input isel_t isel,
+ input replay
+ // End of automatics
+ );
+
+ /*AUTOASSIGNMODPORT("autoinoutmodport_type_intf", "ctl_cb", "ctl_i")*/
+ // Beginning of automatic assignments from modport
+ assign ctl_i.inst = inst;
+ assign ctl_i.isel = isel;
+ assign ctl_i.replay = replay;
+ // End of automatics
+
+endmodule
+
+interface autoinoutmodport_type_intf(input logic clk, input logic rst_n);
+ import uvm_pkg::*;
+ import ap_defines::*;
+
+ logic [4:0] inst;
+ isel_t isel;
+ logic replay;
+
+ clocking ctl_cb @(posedge clk);
+ input inst;
+ input isel;
+ input replay;
+ endclocking: ctl_cb
+
+ modport ctl_mp(clocking ctl_cb);
+
+endinterface
+
+// Local Variables:
+// verilog-typedef-regexp:"_t"
+// End:
diff --git a/tests_ok/autoinoutmodule.v b/tests_ok/autoinoutmodule.v
new file mode 100644
index 0000000..2aa3e4a
--- /dev/null
+++ b/tests_ok/autoinoutmodule.v
@@ -0,0 +1,19 @@
+module autoinoutmodule (/*AUTOARG*/
+ // Outputs
+ lower_out,
+ // Inputs
+ lower_inb, lower_ina
+ );
+
+ /*AUTOINOUTMODULE("inst")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output lower_out;
+ input lower_inb;
+ input lower_ina;
+ // End of automatics
+ // Beginning of automatic in/out/inouts (from specific module)
+
+ wire lower_out = lower_ina | lower_inb;
+
+endmodule
+
diff --git a/tests_ok/autoinoutmodule_iface.v b/tests_ok/autoinoutmodule_iface.v
new file mode 100644
index 0000000..aabd32a
--- /dev/null
+++ b/tests_ok/autoinoutmodule_iface.v
@@ -0,0 +1,14 @@
+// bug721
+module my_core
+ (
+ /*AUTOINOUTMODULE("autoinoutmodule_iface_sub")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ my_svi.master my_svi_port
+ // End of automatics
+ /*AUTOINOUT*/
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ );
+ /*AUTOWIRE*/
+
+endmodule
diff --git a/tests_ok/autoinoutmodule_iface_sub.v b/tests_ok/autoinoutmodule_iface_sub.v
new file mode 100644
index 0000000..96b404c
--- /dev/null
+++ b/tests_ok/autoinoutmodule_iface_sub.v
@@ -0,0 +1,4 @@
+module autoinoutmodule_iface_sub
+ (my_svi.master my_svi_port,
+ );
+endmodule
diff --git a/tests_ok/autoinoutmodule_ign.v b/tests_ok/autoinoutmodule_ign.v
new file mode 100644
index 0000000..f4e0af4
--- /dev/null
+++ b/tests_ok/autoinoutmodule_ign.v
@@ -0,0 +1,14 @@
+module autoinoutmodule (/*AUTOARG*/
+ // Outputs
+ lower_out
+ );
+
+ /*AUTOINOUTMODULE("inst","\(ina\|out\)","","ina")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output lower_out;
+ // End of automatics
+
+ wire lower_out = lower_ina;
+
+endmodule
+
diff --git a/tests_ok/autoinoutmodule_re2.v b/tests_ok/autoinoutmodule_re2.v
new file mode 100644
index 0000000..4aa27c7
--- /dev/null
+++ b/tests_ok/autoinoutmodule_re2.v
@@ -0,0 +1,22 @@
+module autoinoutmodule_re2 (/*AUTOARG*/
+ // Outputs
+ lower_out,
+ // Inputs
+ lower_inb, lower_ina
+ );
+
+ /*AUTOINOUTMODULE("inst","","input.*")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ input lower_inb;
+ input lower_ina;
+ // End of automatics
+
+ /*AUTOINOUTMODULE("inst","","output.*")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output lower_out;
+ // End of automatics
+
+ wire lower_out = lower_ina;
+
+endmodule
+
diff --git a/tests_ok/autoinoutmodule_regexp.v b/tests_ok/autoinoutmodule_regexp.v
new file mode 100644
index 0000000..198ae8c
--- /dev/null
+++ b/tests_ok/autoinoutmodule_regexp.v
@@ -0,0 +1,17 @@
+module autoinoutmodule (/*AUTOARG*/
+ // Outputs
+ lower_out,
+ // Inputs
+ lower_ina
+ );
+
+ /*AUTOINOUTMODULE("inst","\(ina\|out\)")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output lower_out;
+ input lower_ina;
+ // End of automatics
+
+ wire lower_out = lower_ina;
+
+endmodule
+
diff --git a/tests_ok/autoinoutmodule_v2k.v b/tests_ok/autoinoutmodule_v2k.v
new file mode 100644
index 0000000..95d0e81
--- /dev/null
+++ b/tests_ok/autoinoutmodule_v2k.v
@@ -0,0 +1,13 @@
+module autoinoutmodule (
+ /*AUTOINOUTMODULE("inst")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output lower_out,
+ input lower_inb,
+ input lower_ina
+ // End of automatics
+ );
+
+ wire lower_out = lower_ina | lower_inb;
+
+endmodule
+
diff --git a/tests_ok/autoinoutparam.v b/tests_ok/autoinoutparam.v
new file mode 100644
index 0000000..c221ba5
--- /dev/null
+++ b/tests_ok/autoinoutparam.v
@@ -0,0 +1,14 @@
+module autoinoutparam (/*AUTOARG*/);
+
+ /*AUTOINOUTPARAM("inst","param1")*/
+ // Beginning of automatic parameters (from specific module)
+ parameter param1;
+ // End of automatics
+
+ /*AUTOINOUTPARAM("inst")*/
+ // Beginning of automatic parameters (from specific module)
+ parameter param2;
+ // End of automatics
+
+endmodule
+
diff --git a/tests_ok/autoinput_array_bug294.v b/tests_ok/autoinput_array_bug294.v
new file mode 100644
index 0000000..0f3c729
--- /dev/null
+++ b/tests_ok/autoinput_array_bug294.v
@@ -0,0 +1,35 @@
+module mod1(input logic [1:0] reg1[4],
+ input logic reg2[5][6],
+ input logic [1:0] [3:0] [2:0] reg4);
+endmodule
+
+module mod2(output logic [1:0] reg1[4],
+ output logic [1:0] [3:0] [2:0] reg4);
+endmodule
+
+module dut (
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input logic reg2 [5][6] // To foo_i of mod1.v
+ // End of automatics
+ /*AUTOOUTPUT*/
+ );
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic [1:0] reg1 [4]; // From drv_i of mod2.v
+ logic [1:0][3:0] [2:0] reg4; // From drv_i of mod2.v
+ // End of automatics
+
+ mod1 foo_i(/*AUTOINST*/
+ // Inputs
+ .reg1 (reg1/*[1:0].[4]*/),
+ .reg2 (reg2/*.[5][6]*/),
+ .reg4 (reg4/*[1:0][3:0][2:0]*/));
+
+ /* drv_i AUTO_TEMPLATE (.reg1(reg1[]), );*/
+ mod2 drv_i(/*AUTOINST*/
+ // Outputs
+ .reg1 (reg1/*[1:0].[4]*/),
+ .reg4 (reg4/*[1:0][3:0][2:0]*/));
+endmodule
diff --git a/tests_ok/autoinput_asharma.v b/tests_ok/autoinput_asharma.v
new file mode 100644
index 0000000..e519a79
--- /dev/null
+++ b/tests_ok/autoinput_asharma.v
@@ -0,0 +1,30 @@
+module io1_sub(
+ /*AUTOARG*/
+ // Outputs
+ lower_out,
+ // Inputs
+ lower_ina
+ );
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input lower_ina; // To inst of inst.v
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output lower_out; // From inst of inst.v
+ // End of automatics
+
+ /* inst AUTO_TEMPLATE (
+ .lower_inb (1'b1),
+ )*/
+
+
+ inst inst (/*AUTOINST*/
+ // Outputs
+ .lower_out (lower_out),
+ // Inputs
+ .lower_inb (1'b1), // Templated
+ .lower_ina (lower_ina));
+
+endmodule
diff --git a/tests_ok/autoinput_asharma_v2k.v b/tests_ok/autoinput_asharma_v2k.v
new file mode 100644
index 0000000..545c085
--- /dev/null
+++ b/tests_ok/autoinput_asharma_v2k.v
@@ -0,0 +1,24 @@
+module io1_sub(
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input lower_ina, // To inst of inst.v
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output lower_out // From inst of inst.v
+ // End of automatics
+ );
+
+ /* inst AUTO_TEMPLATE (
+ .lower_inb (1'b1),
+ )*/
+
+
+ inst inst (/*AUTOINST*/
+ // Outputs
+ .lower_out (lower_out),
+ // Inputs
+ .lower_inb (1'b1), // Templated
+ .lower_ina (lower_ina));
+
+endmodule
diff --git a/tests_ok/autoinput_concat_ignore.v b/tests_ok/autoinput_concat_ignore.v
new file mode 100644
index 0000000..80e5e58
--- /dev/null
+++ b/tests_ok/autoinput_concat_ignore.v
@@ -0,0 +1,84 @@
+module xyz (/*AUTOARG*/
+ // Outputs
+ signal_f, signal_c,
+ // Inputs
+ signal_b
+ );
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input [2:0] signal_b; // To u_abc of abc.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output signal_c; // From u_abc of abc.v
+ output signal_f; // From u_def of def.v
+ // End of automatics
+
+ /*AUTOWIRE*/
+
+ /* abc AUTO_TEMPLATE
+ (
+ // Outputs
+ .signal_c (signal_c),
+ // Inputs
+ .signal_a ({1'b0, signal_f}),
+ .signal_b (signal_b[2:0]));
+ */
+
+ abc u_abc
+ (/*AUTOINST*/
+ // Outputs
+ .signal_c (signal_c), // Templated
+ // Inputs
+ .signal_a ({1'b0, signal_f}), // Templated
+ .signal_b (signal_b[2:0])); // Templated
+
+ /* def AUTO_TEMPLATE
+ (// Outputs
+ .signal_f (signal_f),
+ // Inputs
+ .signal_d ({1'b1, signal_c}),
+ .signal_e ({2'b11, signal_e}));
+ */
+
+ def u_def
+ (/*AUTOINST*/
+ // Outputs
+ .signal_f (signal_f), // Templated
+ // Inputs
+ .signal_d ({1'b1, signal_c}), // Templated
+ .signal_e ({2'b11, signal_e})); // Templated
+
+endmodule // xyz
+
+module abc (/*AUTOARG*/
+ // Outputs
+ signal_c,
+ // Inputs
+ signal_a, signal_b
+ );
+
+ input [1:0] signal_a;
+ input [2:0] signal_b;
+ output signal_c;
+
+endmodule // abc
+
+module def (/*AUTOARG*/
+ // Outputs
+ signal_f,
+ // Inputs
+ signal_d, signal_e
+ );
+
+ input [1:0] signal_d;
+ input [2:0] signal_e;
+ output signal_f;
+
+endmodule // def
+
+// Local Variables:
+// verilog-auto-ignore-concat: t
+// End:
diff --git a/tests_ok/autoinput_concat_lau.v b/tests_ok/autoinput_concat_lau.v
new file mode 100644
index 0000000..dbfc2fc
--- /dev/null
+++ b/tests_ok/autoinput_concat_lau.v
@@ -0,0 +1,41 @@
+module sub1 (/*AUTOARG*/
+ // Inouts
+ busout,
+ // Inputs
+ bus1
+ );
+
+ input [3:0] bus1;
+ inout [3:0] busout;
+
+ wire busout = bus1;
+
+endmodule
+
+
+module autoinput_concat_lau
+ (
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input [1:0] foo, // To sub1 of sub1.v
+ // End of automatics
+ /*AUTOINOUT*/
+ // Beginning of automatic inouts (from unused autoinst inouts)
+ inout [1:0] fooout // To/From sub1 of sub1.v
+ // End of automatics
+ );
+
+ /* sub1 AUTO_TEMPLATE (
+ .busout ({2'b0,fooout[1:0]}),
+ .bus1 ({2'b0,~foo[1:0]}),
+ );
+ */
+
+ sub1 sub1 (/*AUTOINST*/
+ // Inouts
+ .busout ({2'b0,fooout[1:0]}), // Templated
+ // Inputs
+ .bus1 ({2'b0,~foo[1:0]})); // Templated
+
+endmodule
+
diff --git a/tests_ok/autoinput_concat_lau2.v b/tests_ok/autoinput_concat_lau2.v
new file mode 100644
index 0000000..06c3f23
--- /dev/null
+++ b/tests_ok/autoinput_concat_lau2.v
@@ -0,0 +1,79 @@
+module xyz (/*AUTOARG*/
+ // Inputs
+ signal_e, signal_b
+ );
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input [2:0] signal_b; // To u_abc of abc.v
+ input signal_e; // To u_def of def.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire signal_c; // From u_abc of abc.v
+ wire signal_f; // From u_def of def.v
+ // End of automatics
+
+ /* abc AUTO_TEMPLATE
+ (
+ // Outputs
+ .signal_c (signal_c),
+ // Inputs
+ .signal_a ({1'b0, signal_f}),
+ .signal_b (signal_b[2:0]));
+ */
+
+ abc u_abc
+ (/*AUTOINST*/
+ // Outputs
+ .signal_c (signal_c), // Templated
+ // Inputs
+ .signal_a ({1'b0, signal_f}), // Templated
+ .signal_b (signal_b[2:0])); // Templated
+
+ /* def AUTO_TEMPLATE
+ (// Outputs
+ .signal_f (signal_f),
+ // Inputs
+ .signal_d ({1'b1, signal_c}),
+ .signal_e ({2'b11, signal_e}));
+ */
+
+ def u_def
+ (/*AUTOINST*/
+ // Outputs
+ .signal_f (signal_f), // Templated
+ // Inputs
+ .signal_d ({1'b1, signal_c}), // Templated
+ .signal_e ({2'b11, signal_e})); // Templated
+
+endmodule // xyz
+
+module abc (/*AUTOARG*/
+ // Outputs
+ signal_c,
+ // Inputs
+ signal_a, signal_b
+ );
+
+ input [1:0] signal_a;
+ input [2:0] signal_b;
+ output signal_c;
+
+endmodule // abc
+
+module def (/*AUTOARG*/
+ // Outputs
+ signal_f,
+ // Inputs
+ signal_d, signal_e
+ );
+
+ input [1:0] signal_d;
+ input [2:0] signal_e;
+ output signal_f;
+
+endmodule // def
diff --git a/tests_ok/autoinput_none.v b/tests_ok/autoinput_none.v
new file mode 100644
index 0000000..6dc023d
--- /dev/null
+++ b/tests_ok/autoinput_none.v
@@ -0,0 +1,30 @@
+// Julian Gorfajn
+
+`default_nettype none
+
+module top
+ (
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output wire o, // From sub of Sub.v
+ // End of automatics
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input wire i // To sub of Sub.v
+ // End of automatics
+ );
+
+ Sub sub (/*AUTOINST*/
+ // Outputs
+ .o (o),
+ // Inputs
+ .i (i));
+endmodule
+
+module Sub (input i, output o);
+endmodule
+
+// Local Variables:
+// verilog-auto-declare-nettype: "wire"
+// End:
diff --git a/tests_ok/autoinput_paren.v b/tests_ok/autoinput_paren.v
new file mode 100644
index 0000000..9a12eb1
--- /dev/null
+++ b/tests_ok/autoinput_paren.v
@@ -0,0 +1,28 @@
+module foo (/*AUTOARG*/
+ // Inputs
+ abd, abc
+ ) ;
+ /*AUTOINPUT("ab\(c\|d\)")*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input abc; // To i_bar of bar.v
+ input abd; // To i_bar of bar.v
+ // End of automatics
+ bar i_bar(/*AUTOINST*/
+ // Outputs
+ .aaa (aaa),
+ // Inputs
+ .abc (abc),
+ .abd (abd),
+ .bca (bca));
+
+endmodule // foo
+
+module bar (/*AUTOARG*/
+ // Outputs
+ aaa,
+ // Inputs
+ abc, abd, bca
+ ) ;
+ input abc,abd,bca;
+ output aaa;
+endmodule // bar
diff --git a/tests_ok/autoinsertlast_1.v b/tests_ok/autoinsertlast_1.v
new file mode 100644
index 0000000..d159d11
--- /dev/null
+++ b/tests_ok/autoinsertlast_1.v
@@ -0,0 +1,15 @@
+module ExampInsertLisp;
+
+ /*AUTOINSERTLAST(my-verilog-insert-hello "world")*/
+ // Beginning of automatic insert lisp
+ initial $write("hello world");
+ // End of automatics
+
+endmodule
+/*
+ Local Variables:
+ eval:
+ (defun my-verilog-insert-hello (who)
+ (insert (concat "initial $write(\"hello " who "\");\n")))
+ End:
+ */
diff --git a/tests_ok/autoinst_2k_fredriksen.v b/tests_ok/autoinst_2k_fredriksen.v
new file mode 100644
index 0000000..65538fe
--- /dev/null
+++ b/tests_ok/autoinst_2k_fredriksen.v
@@ -0,0 +1,21 @@
+module top ();
+
+
+ sub sub(/*AUTOINST*/
+ // Outputs
+ .b (b[PARAM2:0]),
+ // Inputs
+ .a (a[PARAM1:0]));
+
+endmodule // top
+
+module sub
+ #(parameter PARAM1=2,
+ PARAM2=3,
+ PARAM3=6)
+ ( input wire [PARAM1:0] a,
+ output reg [PARAM2:0] b
+ );
+
+
+endmodule
diff --git a/tests_ok/autoinst_ams_vorwerk.v b/tests_ok/autoinst_ams_vorwerk.v
new file mode 100644
index 0000000..696bd28
--- /dev/null
+++ b/tests_ok/autoinst_ams_vorwerk.v
@@ -0,0 +1,37 @@
+module autoinst_ams_vorwerk;
+
+ latch latch (/*AUTOINST*/
+ // Outputs
+ .q (q),
+ // Inputs
+ .en (en),
+ .d (d));
+
+endmodule
+
+module latch (/*AUTOARG*/
+ // Outputs
+ q,
+ // Inputs
+ en, d
+ );
+
+`ifdef __VAMS_ENABLE__
+ output (* integer groundSensitivity="gnd "; integer supplySensitivity="vdd "; *) q;
+`else
+ output q;
+`endif
+
+`ifdef __VAMS_ENABLE__
+ input (* integer groundSensitivity="gnd "; integer supplySensitivity="vdd "; *) en;
+`else
+ input en;
+`endif
+
+`ifdef __VAMS_ENABLE__
+ input (* integer groundSensitivity="gnd "; integer supplySensitivity="vdd "; *) d;
+`else
+ input d;
+`endif
+
+endmodule
diff --git a/tests_ok/autoinst_array.v b/tests_ok/autoinst_array.v
new file mode 100644
index 0000000..e72f481
--- /dev/null
+++ b/tests_ok/autoinst_array.v
@@ -0,0 +1,53 @@
+// bug637
+
+module submod_a
+ (
+ //Inputs
+ input wire signed [15:0] serial_in,
+ //Outputs
+ output wire signed [15:0] parallel_out [0:7]
+ );
+endmodule
+
+module submod_b
+ (
+ //Inputs
+ input wire signed [15:0] parallel_out [0:7],
+ //Outputs
+ output wire signed [15:0] final_out [0:7]
+ );
+endmodule
+
+module top
+ (
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input logic signed [15:0] serial_in, // To a_inst of submod_a.v
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output logic signed [15:0] final_out [0:7] // From b_inst of submod_b.v
+ // End of automatics
+ );
+
+ /*AUTOLOGIC*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic signed [15:0] parallel_out [0:7]; // From a_inst of submod_a.v
+ // End of automatics
+
+ submod_a a_inst
+ (/*AUTOINST*/
+ // Outputs
+ .parallel_out (parallel_out/*[15:0].[0:7]*/),
+ // Inputs
+ .serial_in (serial_in[15:0]));
+
+ submod_b b_inst
+ (/*AUTOINST*/
+ // Outputs
+ .final_out (final_out/*[15:0].[0:7]*/),
+ // Inputs
+ .parallel_out (parallel_out/*[15:0].[0:7]*/));
+
+
+endmodule
diff --git a/tests_ok/autoinst_array_braket.v b/tests_ok/autoinst_array_braket.v
new file mode 100644
index 0000000..1157c5a
--- /dev/null
+++ b/tests_ok/autoinst_array_braket.v
@@ -0,0 +1,71 @@
+module sub(output logic [1:-1] oned,
+ output logic [1:-1] [2:-1] twod,
+ output logic [1:-1] [2:-1] [3:-3] threed);
+endmodule
+
+module dut (
+ );
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic [1:-1] b_oned; // From subb of sub.v
+ logic [3:-3] b_threed; // From subb of sub.v
+ logic [2:-1] b_twod; // From subb of sub.v
+ logic [1:-1] c_oned; // From subc of sub.v
+ logic [x][y] [3:-3] c_threed; // From subc of sub.v
+ logic [x] [2:-1] c_twod; // From subc of sub.v
+ logic [1:-1] d_oned; // From subd of sub.v
+ logic [1:-1][2:-1] [3:-3] d_threed; // From subd of sub.v
+ logic [1:-1] [2:-1] d_twod; // From subd of sub.v
+ logic [1:-1] oned; // From sub1 of sub.v
+ logic [1:-1][2:-1] [3:-3] threed; // From sub1 of sub.v
+ logic [1:-1] [2:-1] twod; // From sub1 of sub.v
+ // End of automatics
+
+ /* sub AUTO_TEMPLATE ();
+ */
+
+ sub sub1 (/*AUTOINST*/
+ // Outputs
+ .oned (oned[1:-1]),
+ .twod (twod/*[1:-1][2:-1]*/),
+ .threed (threed/*[1:-1][2:-1][3:-3]*/));
+
+ /* sub AUTO_TEMPLATE (
+ .oned (b_oned[]),
+ .twod (b_twod[]),
+ .threed (b_threed[]));
+ */
+
+ // NOTE this results in the wrong declaration for b_twod/b_threed
+ sub subb (/*AUTOINST*/
+ // Outputs
+ .oned (b_oned[1:-1]), // Templated
+ .twod (b_twod[2:-1]), // Templated
+ .threed (b_threed[3:-3])); // Templated
+
+ /* sub AUTO_TEMPLATE (
+ .oned (c_oned[]),
+ .twod (c_twod[x][]),
+ .threed (c_threed[x][y][]));
+ */
+
+ sub subc (/*AUTOINST*/
+ // Outputs
+ .oned (c_oned[1:-1]), // Templated
+ .twod (c_twod[x][2:-1]), // Templated
+ .threed (c_threed[x][y][3:-3])); // Templated
+
+ /* sub AUTO_TEMPLATE (
+ .oned (d_oned[][]),
+ .twod (d_twod[][]),
+ .threed (d_threed[][]));
+ */
+
+ sub subd (/*AUTOINST*/
+ // Outputs
+ .oned (d_oned[1:-1]), // Templated
+ .twod (d_twod/*[1:-1][2:-1]*/), // Templated
+ .threed (d_threed/*[1:-1][2:-1][3:-3]*/)); // Templated
+
+endmodule
diff --git a/tests_ok/autoinst_atregexp.v b/tests_ok/autoinst_atregexp.v
new file mode 100644
index 0000000..1901551
--- /dev/null
+++ b/tests_ok/autoinst_atregexp.v
@@ -0,0 +1,35 @@
+module ex;
+
+ /* autoinst_paramover_sub AUTO_TEMPLATE "u_\(.*\)" (
+ .a(inA_@[]),
+ .b(outA_@[]),
+ );*/
+
+ autoinst_paramover_sub u_foo(/*AUTOINST*/
+ // Inouts
+ .a (inA_foo[bitsa:0]), // Templated
+ .b (outA_foo[bitsb:0])); // Templated
+ autoinst_paramover_sub u_bar(/*AUTOINST*/
+ // Inouts
+ .a (inA_bar[bitsa:0]), // Templated
+ .b (outA_bar[bitsb:0])); // Templated
+ autoinst_paramover_sub u_baz(/*AUTOINST*/
+ // Inouts
+ .a (inA_baz[bitsa:0]), // Templated
+ .b (outA_baz[bitsb:0])); // Templated
+
+ /* autoinst_paramover_sub AUTO_TEMPLATE (
+ .a(inN_@[]),
+ .b(outN_@[]),
+ );*/
+
+ autoinst_paramover_sub u_0_2(/*AUTOINST*/
+ // Inouts
+ .a (inN_0[bitsa:0]), // Templated
+ .b (outN_0[bitsb:0])); // Templated
+ autoinst_paramover_sub u_1_3(/*AUTOINST*/
+ // Inouts
+ .a (inN_1[bitsa:0]), // Templated
+ .b (outN_1[bitsb:0])); // Templated
+
+endmodule
diff --git a/tests_ok/autoinst_belkind_concat.v b/tests_ok/autoinst_belkind_concat.v
new file mode 100644
index 0000000..5f92e58
--- /dev/null
+++ b/tests_ok/autoinst_belkind_concat.v
@@ -0,0 +1,52 @@
+module aaa (/*AUTOARG*/
+ // Outputs
+ y1, y0,
+ // Inputs
+ y3, y2
+ );
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output y0; // From bbb of bbb.v
+ output y1; // From bbb of bbb.v
+ // End of automatics
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input y2; // To bbb of bbb.v
+ input y3; // To bbb of bbb.v
+ // End of automatics
+ /*AUTOWIRE*/
+
+ wire u0, u1, z0, z1;
+ /*
+ bbb AUTO_TEMPLATE (
+ .xo0 ({(u0), y0}),
+ .xo1 ({y1, (u1)}),
+ .xi0 ({(z0), y2}),
+ .xi1 ({y3, (z1)}),
+ );
+ */
+ bbb bbb (/*AUTOINST*/
+ // Outputs
+ .xo0 ({(u0), y0}), // Templated
+ .xo1 ({y1, (u1)}), // Templated
+ // Inputs
+ .xi0 ({(z0), y2}), // Templated
+ .xi1 ({y3, (z1)})); // Templated
+
+endmodule // aaa
+
+module bbb (/*AUTOARG*/
+ // Outputs
+ xo0, xo1,
+ // Inputs
+ xi0, xi1
+ );
+ output [1:0] xo0, xo1;
+ input [1:0] xi0, xi1;
+ /*AUTOTIEOFF*/
+ // Beginning of automatic tieoffs (for this module's unterminated outputs)
+ wire [1:0] xo0 = 2'h0;
+ wire [1:0] xo1 = 2'h0;
+ // End of automatics
+endmodule // bbb
diff --git a/tests_ok/autoinst_bits_lba.v b/tests_ok/autoinst_bits_lba.v
new file mode 100644
index 0000000..5c7033f
--- /dev/null
+++ b/tests_ok/autoinst_bits_lba.v
@@ -0,0 +1,27 @@
+module lba
+
+ (/*AUTOnotARG*/
+ // Outputs
+ );
+
+
+ /* autoinst_bits_lba_gi AUTO_TEMPLATE (
+ .WWCmdI (WWCmdI[]));
+ */
+
+ autoinst_bits_lba_gi gi (/*AUTOINST*/
+ // Outputs
+ .WWCmdI (WWCmdI[8:0]), // Templated
+ .WWADI (WWADI[31:0]),
+ // Inouts
+ .WWADB (WWADB[31:0]),
+ .WWCmdB (WWCmdB[8:0]),
+ // Inputs
+ .CLK (CLK),
+ .WWADoe (WWADoe),
+ .WWCoe (WWCoe),
+ .WWCmdIfOE (WWCmdIfOE[8:0]),
+ .WWADHold (WWADHold),
+ .iWWADO (iWWADO[31:0]));
+
+endmodule
diff --git a/tests_ok/autoinst_bits_lba_gi.v b/tests_ok/autoinst_bits_lba_gi.v
new file mode 100644
index 0000000..234076f
--- /dev/null
+++ b/tests_ok/autoinst_bits_lba_gi.v
@@ -0,0 +1,109 @@
+module autoinst_bits_lba_gi
+
+ // ==xxxxxxx==
+
+ // xxxxxxxxx 1997-1998, xxxxx xxx.
+ // xxx xxxxxx xxxxxxxx
+
+ // ****************************************************************** /
+ // ****************************************************************** /
+ // xxxxx, xxxxxxxxxxxx
+ // xxxxxxx: xxx-4080
+ // xxxxxx: xxx xxxxxxx
+ // xxxxx: xxxxxxx 16, 1998
+ // ******************************************************************* /
+ // ******************************************************************* /
+ // xxxx xxxx: xxx_xx.x
+ // xxxxxxxx xxxxxxx:
+ // $xxx: xxx_xx.x,x $
+ // xxxxxxxx 1.3 1998/03/06 00:27:00 xxx
+ // -- xxxxx xxxxxxx xx xx.xxxx xxx xxxxxxxx xxxxxxx.
+ // -- xxxx xxxxxxxxxxxxx xx xx xxxxxxxxxxx xx xx.x xxx xx.x xx xxxxxxx xxx xxxxxxxxxxx.
+ // -- xxxx xxxxx xxx xxxxxxxxxxxxx xxx1'x (xxxxxxx xx xxxxx) xx xx.x xxx xxxx xxxxxx
+ // xxxxxxxxxx.
+ // -- xxxxx xxxxxxxxxx xxxxxxxx xx xxx xx xxxxxxxxxxx xxx xxxx xxxxxx xxxxxxxxxxxx xxxx.
+ // -- xx xxx xxxxxxxxx xxx xxxxxx xx xx xx xxx xxxxx xxxxx xx xxxx xxxxxxxx xx xxxx.
+ // -- xx xx xxxx xxxxxxx xxx xxx xxxx xxxxxx xxxxxx (xxx xxx xxxx) xxx xxx xxxx/xxxx
+ // xxxxxxxxxx xxxx xxxxxxx.
+ //
+ // xxxxxxxx 1.2 1998/03/04 18:58:55 xxx
+ // xxxxx xxxxxxxxx xxx-xx xxxxxxx xxxxxxx xx xxxx xxxxx.
+ //
+ // xxxxxxxx 1.1 1998/02/23 19:31:52 xxx
+ // xxxxx xxxxx xxxxxx xxx xxxx xxxxx xxxxx xxxxxxxxxx.
+ //
+ // ---------------------------------------------------------------
+ //
+ // xxxxxxx xxx xxxxxxxxx xxx xxxxx xxx xxxxxxx xxx
+ //
+ // xxxx xxxxxx xxxxx xxx xxxxx xxxxxx xxxxxxx/xxxx xxx xxxx
+ // xx.x xxx xx xx xxxxxxxxx xxxx xxxx.x xxxxxx xx
+ // xxxx xxx xxxxxxx xx xxx. xx xxxx xxxxates the
+ // bidir Foo Bus into a chip input for use by li.v
+ //
+ // This module also isolates for input to lbsm.v, and drives
+ // (if so indicated by lbsm.v) the bidir Fooileo Cmd bus.
+ //
+ //
+
+ (
+ CLK,
+ WWADoe,
+ WWCoe,
+ WWCmdIfOE,
+ WWADHold,
+ iWWADO,
+ WWCmdI,
+ WWADI,
+ WWADB,
+ WWCmdB
+ );
+
+ /////////////////////////////////////////////////////////////////////
+ // inputs
+
+ input CLK; // LBA clk
+
+ // inputs from lbsm.v
+ input WWADoe; // FooBus Addr/Data OE
+ input WWCoe; // FooBus Cmd OE
+ input [8:0] WWCmdIfOE; // FooBus Cmd if enabled
+ input WWADHold; // FooBus Addr hold
+
+ // inputs from li.v
+ input [31:0] iWWADO; // FooBus Address/Data out next cycle
+
+
+ /////////////////////////////////////////////////////////////////////
+ // outputs
+
+ // outputs to lbsm.v
+ output [8:0] WWCmdI; // FooBus Command in
+
+ // outputs to li.v
+ output [31:0] WWADI; // FooBus Address/Data in
+
+
+ /////////////////////////////////////////////////////////////////////
+ // bidirs
+
+ // bidirs to/from off-chip
+ inout [31:0] WWADB; // bidir FooBus addr/data
+ inout [8:0] WWCmdB; // bidir FooBus command
+
+ /////////////////////////////////////////////////////////////////////
+ // reg's for outputs (some flops, some not)
+
+ /////////////////////////////////////////////////////////////////////
+ // other flops
+
+ reg [31:0] WWADIfOE; // FooBus Addr/Data Out if enabled
+
+
+
+endmodule
+
+
+// Local Variables:
+// eval:(if (fboundp `verilog-enable-indentation) (verilog-enable-indentation))
+// End:
diff --git a/tests_ok/autoinst_brucet.v b/tests_ok/autoinst_brucet.v
new file mode 100644
index 0000000..2ba058c
--- /dev/null
+++ b/tests_ok/autoinst_brucet.v
@@ -0,0 +1,39 @@
+module io1_sub(/*AUTOARG*/
+ // Outputs
+ x, y, z,
+ // Inputs
+ a, b
+ );
+
+ input a;
+ input b;
+ output x;
+ output y;
+ output z;
+
+ andcell c0 (
+ .c (x),
+ /*AUTOINST*/
+ // Inputs
+ .a (a),
+ .b (b));
+
+ orcell c0 (
+ .c (y),
+ /*AUTOINST*/
+ // Inputs
+ .a (a),
+ .b (b));
+
+ nandcell c0 (
+ .c (z),
+ /*AUTOINST*/
+ // Inputs
+ .a (a),
+ .b (b));
+
+endmodule
+
+// Local Variables:
+// verilog-library-files:("autoinst_brucet_library.v")
+// End:
diff --git a/tests_ok/autoinst_brucet_library.v b/tests_ok/autoinst_brucet_library.v
new file mode 100644
index 0000000..431357a
--- /dev/null
+++ b/tests_ok/autoinst_brucet_library.v
@@ -0,0 +1,38 @@
+module andcell (/*AUTOARG*/
+ // Outputs
+ c,
+ // Inputs
+ a, b
+ );
+
+ input a;
+ input b;
+ output c;
+ wire c = a&b;
+endmodule
+
+module nandcell (/*AUTOARG*/
+ // Outputs
+ c,
+ // Inputs
+ a, b
+ );
+
+ input a;
+ input b;
+ output c;
+ wire c = !(a&b);
+endmodule
+
+module orcell (/*AUTOARG*/
+ // Outputs
+ c,
+ // Inputs
+ a, b
+ );
+
+ input a;
+ input b;
+ output c;
+ wire c = a|b;
+endmodule
diff --git a/tests_ok/autoinst_bug373.v b/tests_ok/autoinst_bug373.v
new file mode 100644
index 0000000..1df0146
--- /dev/null
+++ b/tests_ok/autoinst_bug373.v
@@ -0,0 +1,47 @@
+typedef struct packed {
+ logic [7:0] data;
+ logic wr_ena;
+} mystruct_s;
+
+module submod
+ (input logic a_port,
+ input logic [4:0] b_bus,
+ input mystruct_s single_struct_is_fine,
+ input mystruct_s [2:0] array_of_struct_is_not,
+ output logic status);
+
+ /*AUTOTIEOFF*/
+ // Beginning of automatic tieoffs (for this module's unterminated outputs)
+ wire status = 1'h0;
+ // End of automatics
+
+endmodule // submod
+
+module top;
+ /*AUTOLOGIC*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic status; // From submod0 of submod.v
+ // End of automatics
+
+ /*AUTOREGINPUT*/
+ // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+ logic a_port; // To submod0 of submod.v
+ mystruct_s [2:0] array_of_struct_is_not; // To submod0 of submod.v
+ logic [4:0] b_bus; // To submod0 of submod.v
+ mystruct_s single_struct_is_fine; // To submod0 of submod.v
+ // End of automatics
+
+ submod submod0
+ (/*AUTOINST*/
+ // Outputs
+ .status (status),
+ // Inputs
+ .a_port (a_port),
+ .b_bus (b_bus[4:0]),
+ .single_struct_is_fine (single_struct_is_fine),
+ .array_of_struct_is_not (array_of_struct_is_not[2:0]));
+endmodule // top
+
+// Local Variables:
+// verilog-typedef-regexp: "_s$"
+// End:
diff --git a/tests_ok/autoinst_case_chakradhara.v b/tests_ok/autoinst_case_chakradhara.v
new file mode 100644
index 0000000..7ed5fc0
--- /dev/null
+++ b/tests_ok/autoinst_case_chakradhara.v
@@ -0,0 +1,27 @@
+module foo();
+ /*bar AUTO_TEMPLATE (
+ .pme\(.*\)_o (pme\1[]),
+ .PME\(.*\)_o (pMe\1[]),
+ .pme\(.*\)_o (pme\1[]),
+ );
+ */
+ bar bar
+ (/*AUTOINST*/
+ // Inputs
+ .PME_o (pMe), // Templated
+ .pme_o (pme), // Templated
+ .pmE_o (pmE_o));
+
+endmodule
+
+module bar
+ (/*AUTOARG*/
+ // Inputs
+ PME_o, pme_o, pmE_o
+ );
+
+ input PME_o;
+ input pme_o;
+ input pmE_o;
+
+endmodule
diff --git a/tests_ok/autoinst_casefold_hou.v b/tests_ok/autoinst_casefold_hou.v
new file mode 100644
index 0000000..6f0a358
--- /dev/null
+++ b/tests_ok/autoinst_casefold_hou.v
@@ -0,0 +1,45 @@
+typedef struct packed {
+ logic a,b,c;
+} tTest;
+
+module test
+ (
+ input clk,rst
+ );
+
+ wire [7:0] data_tm;
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ tTest q; // From foo of foo.v
+ // End of automatics
+
+ /* foo AUTO_TEMPLATE (
+ .tm (data_tm),
+ );
+ */
+
+ foo foo (/*AUTOINST*/
+ // Outputs
+ .q (q),
+ // Inputs
+ .clk (clk),
+ .rst (rst),
+ .tm (data_tm)); // Templated
+ /*AUTO_LISP(setq verilog-typedef-regexp "^t[A-Z]")*/
+endmodule
+
+module foo
+ (
+ input clk,
+ input rst,
+ input [7:0] tm,
+ output tTest q
+ );
+endmodule
+
+// Local Variables:
+// verilog-case-fold:nil
+// verilog-library-directories:(".")
+// verilog-typedef-regexp:"^t[A-Z]"
+// End:
diff --git a/tests_ok/autoinst_cavanaugh_pull.v b/tests_ok/autoinst_cavanaugh_pull.v
new file mode 100644
index 0000000..3234027
--- /dev/null
+++ b/tests_ok/autoinst_cavanaugh_pull.v
@@ -0,0 +1,130 @@
+
+module fifo(/*AUTOARG*/
+ // Outputs
+ fifo_full_w, data_valid_r, rdata_r,
+ // Inputs
+ clk, rst_n, enqueue_w, data_in_w, dequeue_w, full_threshold
+ );
+
+ input clk;
+ input rst_n;
+ output fifo_full_w;
+
+ input enqueue_w;
+ input [(DATA_WIDTH-1):0] data_in_w;
+
+ output data_valid_r;
+ input dequeue_w;
+ input [1:0] full_threshold;
+
+ output [(DATA_WIDTH-1):0] rdata_r;
+
+
+endmodule
+
+module req (p_clk, carb_rst_rnp, req_rp, len_rxp, deq_req, deq_len, deq_val);
+
+ input p_clk;
+ input carb_rst_rnp;
+ input [4:0] len_rxp;
+ input req_rp;
+ input deq_req;
+ output [4:0] deq_len;
+ output deq_val;
+ reg [5:0] fifo_entry1_rp;
+ reg [5:0] fifo_entry2_rp;
+ reg [4:0] deq_len;
+ reg deq_val;
+
+endmodule
+
+module pull( /*AUTOARG*/
+ // Outputs
+ d_len, d_val,
+ // Inputs
+ clk, rst_rnpha, lenar_rxp, rem_rpd, d_rews
+ );
+
+ input clk;
+ input rst_rnpha;
+ input [4:0] lenar_rxp;
+ input rem_rpd;
+ input d_rews;
+ output [4:0] d_len;
+ output d_val;
+
+
+ /* req AUTO_TEMPLATE "\(g[a-z0-9]+\|g.*[0-9]\)" (
+ .p_clk (my_clk_@),
+ .len_rxp (carb_rst_rnp_@),
+ .carb_rst_rnp (pull_req1));
+
+ */
+
+ req test432_gbe5(/*AUTOINST*/
+ // Outputs
+ .deq_len (deq_len[4:0]),
+ .deq_val (deq_val),
+ // Inputs
+ .p_clk (my_clk_gbe5), // Templated
+ .carb_rst_rnp (pull_req1), // Templated
+ .len_rxp (carb_rst_rnp_gbe5), // Templated
+ .req_rp (req_rp),
+ .deq_req (deq_req));
+
+ req gbe9_vreos(/*AUTOINST*/
+ // Outputs
+ .deq_len (deq_len[4:0]),
+ .deq_val (deq_val),
+ // Inputs
+ .p_clk (my_clk_gbe9), // Templated
+ .carb_rst_rnp (pull_req1), // Templated
+ .len_rxp (carb_rst_rnp_gbe9), // Templated
+ .req_rp (req_rp),
+ .deq_req (deq_req));
+
+
+ /* fifo AUTO_TEMPLATE "gbe[0-9]+_\([^\_]+\)" (
+ .clk (@_clk),
+ .\(.*data.*\) (@_\1),
+ .\(.*\)\(full\)\(.*\) (\1@\3),
+ .\(en\|de\)\(.\).+ (@_\1\2));
+ */
+
+
+
+ fifo #(5) gbe2_pull_req (/*AUTOINST*/
+ // Outputs
+ .fifo_full_w (fifo_pull_w), // Templated
+ .data_valid_r (pull_data_valid_r), // Templated
+ .rdata_r (pull_rdata_r), // Templated
+ // Inputs
+ .clk (pull_clk), // Templated
+ .rst_n (rst_n),
+ .enqueue_w (pull_enq), // Templated
+ .data_in_w (pull_data_in_w), // Templated
+ .dequeue_w (pull_deq), // Templated
+ .full_threshold (pull_threshold)); // Templated
+
+
+ fifo #(5)
+ gbe1_pull_req_fifo( /*AUTOINST*/
+ // Outputs
+ .fifo_full_w (fifo_pull_w), // Templated
+ .data_valid_r (pull_data_valid_r), // Templated
+ .rdata_r (pull_rdata_r), // Templated
+ // Inputs
+ .clk (pull_clk), // Templated
+ .rst_n (rst_n),
+ .enqueue_w (pull_enq), // Templated
+ .data_in_w (pull_data_in_w), // Templated
+ .dequeue_w (pull_deq), // Templated
+ .full_threshold (pull_threshold)); // Templated
+
+
+
+
+
+
+
+endmodule // pull_arb
diff --git a/tests_ok/autoinst_ciu.v b/tests_ok/autoinst_ciu.v
new file mode 100644
index 0000000..6994a72
--- /dev/null
+++ b/tests_ok/autoinst_ciu.v
@@ -0,0 +1,24 @@
+module testmux
+ (
+ input wire [2:0] a
+ );
+endmodule
+
+module top_test();
+
+ /* testmux AUTO_TEMPLATE "\(.*\)$" (
+ .a (@_a_value[]),
+ );
+ */
+
+ testmux foo1_1
+ (/*AUTOINST*/
+ // Inputs
+ .a (foo1_1_a_value[2:0])); // Templated
+
+ testmux foo1_2
+ (/*AUTOINST*/
+ // Inputs
+ .a (foo1_2_a_value[2:0])); // Templated
+
+endmodule
diff --git a/tests_ok/autoinst_clog2_bug522.v b/tests_ok/autoinst_clog2_bug522.v
new file mode 100644
index 0000000..538c63a
--- /dev/null
+++ b/tests_ok/autoinst_clog2_bug522.v
@@ -0,0 +1,30 @@
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by brad Dobbie.
+
+module mod;
+ submod #
+ (.VEC_W(8),
+ .IDX_W($clog2(VEC_W)))
+ submod
+ (/*AUTOINST*/
+ // Outputs
+ .idx (idx[2:0]),
+ // Inputs
+ .vec (vec[7:0]));
+endmodule
+
+module submod (/*AUTOARG*/
+ // Outputs
+ idx,
+ // Inputs
+ vec
+ );
+ parameter VEC_W = 32;
+ parameter IDX_W = $clog2(VEC_W);
+ input [VEC_W-1:0] vec;
+ output [IDX_W-1:0] idx;
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-param-value:t
+// End:
diff --git a/tests_ok/autoinst_cmtcell_msg270.v b/tests_ok/autoinst_cmtcell_msg270.v
new file mode 100644
index 0000000..7c3e65d
--- /dev/null
+++ b/tests_ok/autoinst_cmtcell_msg270.v
@@ -0,0 +1,15 @@
+module ex;
+
+ subwidth u_a2 // commented
+ (/*AUTOINST*/
+ // Outputs
+ .bus4a (bus4a[0:3]));
+
+endmodule
+
+module subwidth (/*AUTOARG*/
+ // Outputs
+ bus4a
+ );
+ output [0:3] bus4a;
+endmodule
diff --git a/tests_ok/autoinst_cmtinst_bug383.v b/tests_ok/autoinst_cmtinst_bug383.v
new file mode 100644
index 0000000..2d21b43
--- /dev/null
+++ b/tests_ok/autoinst_cmtinst_bug383.v
@@ -0,0 +1,45 @@
+module t;
+
+ /*fifo_s AUTO_TEMPLATE (
+ .ignored_signal (1'b1),
+ .out_signal (NC),
+ .out_bus (out_bus[]),
+ );
+ */
+ fifo_s data_fifo (
+ //fifo_s data_fifo (
+ // Inputs
+ .clk (fifo_clk),
+ /*AUTOINST*/
+ // Outputs
+ .out_bus (out_bus[31:0]), // Templated
+ .out_signal (NC), // Templated
+ // Inputs
+ .ignored_signal (1'b1), // Templated
+ .reset (reset));
+
+ /*fifo_s AUTO_TEMPLATE (
+ .ignored_signal (1'b1),
+ .out_signal (NC),
+ .out_bus (out_bus[]),
+ );
+ */
+ //fifo_s data_fifo (
+ fifo_s data_fifo (
+ // Inputs
+ .clk (fifo_clk),
+ /*AUTOINST*/
+ // Outputs
+ .out_bus (out_bus[31:0]), // Templated
+ .out_signal (NC), // Templated
+ // Inputs
+ .ignored_signal (1'b1), // Templated
+ .reset (reset));
+endmodule
+
+module fifo_s;
+ input ignored_signal;
+ input reset;
+ output [31:0] out_bus;
+ output out_signal;
+endmodule
diff --git a/tests_ok/autoinst_cmtparen_tennant.sv b/tests_ok/autoinst_cmtparen_tennant.sv
new file mode 100644
index 0000000..831a22f
--- /dev/null
+++ b/tests_ok/autoinst_cmtparen_tennant.sv
@@ -0,0 +1,117 @@
+typedef node logic;
+
+module top
+ #(parameter COLS = 4
+ )
+ ( input logic clk,
+ input logic rstb,
+ input logic [COLS-1:0] ival,
+ input logic [COLS-1:0][1:0] idata_some_extra_sig_length,
+
+ input logic [COLS-1:0][7:0] isig1,
+ input logic [COLS-1:0][6:0] isig2,
+ input logic [COLS-1:0][5:0] isig3,
+ /*AUTOINPUT*/
+
+ output logic [COLS-1:0] oval,
+ output logic [COLS-1:0][1:0] odata,
+ output logic [COLS-1:0] s3_oval,
+ output logic [COLS-1:0][1:0] s3_odata
+
+ /*AUTOOUTPUT*/
+ );
+
+
+ logic [COLS-1:0][1:0] s1_odata; // From isub1 of sub1.v
+ logic [COLS-1:0] s1_oval; // From isub1 of sub1.v
+ /*AUTOWIRE*/
+
+ /* sub2 AUTO_TEMPLATE(
+ .idata_some_extra_sig_length ( s1_odata),
+ .ival ( s1_oval),
+ );*/
+ sub2 isub2 (/*AUTOINST*/
+ // Outputs
+ .oval (oval[COLS-1:0]),
+ .odata (odata/*[COLS-1:0][1:0]*/),
+ // Inputs
+ .clk (clk),
+ .rstb (rstb),
+ .ival ( s1_oval), // Templated
+ .idata_some_extra_sig_length( s1_odata)); // Templated
+
+ genvar column;
+ /* sub1 AUTO_TEMPLATE(
+ .i.* ( @"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
+ .o.* ( s1_@"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
+ );*/
+ /* sub3 AUTO_TEMPLATE(
+ .i.* ( @"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
+ .o.* ( s3_@"vl-name"[column] @"(if (or(>(length vl-mbits)0) (>(length vl-bits)0)) (concat \\"/\\* \\" vl-mbits vl-bits \\" *\\/\\") )"),
+ );*/
+ generate for(column=0;column<4;column++) begin : COLUMN
+ sub1 isub1(/*AUTOINST*/
+ // Outputs
+ .oval ( s1_oval[column] ), // Templated
+ .odata ( s1_odata[column] /* [1:0] */), // Templated
+ // Inputs
+ .clk (clk),
+ .rstb (rstb),
+ .ival ( ival[column] ), // Templated
+ .idata_some_extra_sig_length( idata_some_extra_sig_length[column] /* [1:0] */), // Templated
+ .isig1 ( isig1[column] /* [7:0] */), // Templated
+ .isig2 ( isig2[column] /* [6:0] */), // Templated
+ .isig3 ( isig3[column] /* [5:0] */)); // Templated
+ sub3 isub3(/*AUTOINST*/
+ // Outputs
+ .oval ( s3_oval[column] ), // Templated
+ .odata ( s3_odata[column] /* [1:0] */), // Templated
+ // Inputs
+ .clk (clk),
+ .rstb (rstb),
+ .ival ( ival[column] ), // Templated
+ .idata_some_extra_sig_length( idata_some_extra_sig_length[column] /* [1:0] */)); // Templated
+
+ end endgenerate
+
+
+endmodule // top
+
+module sub1
+ ( input logic clk,
+ input logic rstb,
+ input logic ival,
+ input logic [1:0] idata_some_extra_sig_length,
+ input logic [7:0] isig1,
+ input logic [6:0] isig2,
+ input logic [5:0] isig3,
+ output logic oval,
+ output logic [1:0] odata
+ );
+endmodule // sub
+module sub3
+ ( input logic clk,
+ input logic rstb,
+ input logic ival,
+ input logic [1:0] idata_some_extra_sig_length,
+ output logic oval,
+ output logic [1:0] odata
+ );
+endmodule // sub
+
+module sub2
+ #(parameter COLS = 4
+ )
+ ( input logic clk,
+ input logic rstb,
+ input logic [COLS-1:0] ival,
+ input logic [COLS-1:0][1:0] idata_some_extra_sig_length,
+ output logic [COLS-1:0] oval,
+ output logic [COLS-1:0] [1:0] odata
+ );
+endmodule // sub
+// Local Variables:
+// verilog-typedef-regexp:"\\(^t_\\)\\|\\(^node$\\)\\|\\(_s$\\)\\|\\(_t$\\)"
+// verilog-library-directories:("." )
+// verilog-library-extensions:(".v" ".sv" ".h" ".vr" ".vm")
+// End:
diff --git a/tests_ok/autoinst_crawford_array.v b/tests_ok/autoinst_crawford_array.v
new file mode 100644
index 0000000..60860f1
--- /dev/null
+++ b/tests_ok/autoinst_crawford_array.v
@@ -0,0 +1,77 @@
+`define AUTO_NBR_A_INST 2
+
+module autoinst_crawford_array(/*AUTOARG*/
+ // Outputs
+ a_valid, a_data,
+ // Inputs
+ a_ready, clk, rst_n
+ );
+
+ // a interface
+ output [`AUTO_NBR_A_INST*1-1:0] a_valid;
+ output [`AUTO_NBR_A_INST*8-1:0] a_data;
+ input [`AUTO_NBR_A_INST*1-1:0] a_ready;
+
+ // clock interface
+ input clk;
+ input rst_n;
+
+ /*AUTOWIRE*/
+
+ // non-arrayed example
+ autoinst_crawford_array_a auto_a_0
+ (/*AUTOINST*/
+ // Outputs
+ .a_valid (a_valid),
+ .a_data (a_data[7:0]),
+ // Inputs
+ .a_ready (a_ready),
+ .clk (clk),
+ .rst_n (rst_n));
+
+ autoinst_crawford_array_a auto_a_1
+ (/*AUTOINST*/
+ // Outputs
+ .a_valid (a_valid),
+ .a_data (a_data[7:0]),
+ // Inputs
+ .a_ready (a_ready),
+ .clk (clk),
+ .rst_n (rst_n));
+
+ // Arrayed instances
+ // AUTOINST does not work for this one :-(
+ // Note it is tricky because I want clk and rst_n to fanout to both instances,
+ // but I want the valid signals to be discreatly tied to each submodule.
+
+ //autoinst_crawford_array_a ary [`AUTO_NBR_A_INST-1:0]
+ // (/*XXXAUTOINST*/
+ // // Outputs
+ // .a_valid (a_valid[1:0]),
+ // .a_data (a_data[15:0]),
+ // // Inputs
+ // .a_ready (a_ready[1:0]),
+ // .clk (clk),
+ // .rst_n (rst_n));
+
+ autoinst_crawford_array_a ary [`AUTO_NBR_A_INST-1:0]
+ (/*AUTOINST*/
+ // Outputs
+ .a_valid (a_valid),
+ .a_data (a_data[7:0]),
+ // Inputs
+ .a_ready (a_ready),
+ .clk (clk),
+ .rst_n (rst_n));
+
+ autoinst_crawford_array_a #(.a(a),b) par [`AUTO_NBR_A_INST-1:0]
+ (/*AUTOINST*/
+ // Outputs
+ .a_valid (a_valid),
+ .a_data (a_data[7:0]),
+ // Inputs
+ .a_ready (a_ready),
+ .clk (clk),
+ .rst_n (rst_n));
+
+endmodule
diff --git a/tests_ok/autoinst_crawford_array_a.v b/tests_ok/autoinst_crawford_array_a.v
new file mode 100644
index 0000000..1aee964
--- /dev/null
+++ b/tests_ok/autoinst_crawford_array_a.v
@@ -0,0 +1,39 @@
+`define auto_trq #1 // clock to q delay
+`define auto_tcq #1 // reset to q delay
+
+module autoinst_crawford_array_a(/*AUTOARG*/
+ // Outputs
+ a_valid, a_data,
+ // Inputs
+ a_ready, clk, rst_n
+ );
+
+ // a interface
+ output a_valid;
+ output [7:0] a_data;
+ input a_ready;
+
+ // clock interface
+ input clk;
+ input rst_n;
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg [7:0] a_data;
+ reg a_valid;
+ // End of automatics
+
+ always @(posedge clk or negedge rst_n) begin
+ if(~rst_n) begin
+ a_valid <= `auto_trq 0;
+ a_data <= `auto_trq 0;
+ end
+ else begin
+ if(a_ready) begin
+ a_valid <= `auto_tcq 1;
+ a_data <= `auto_tcq 8'hcc;
+ end
+ end
+ end
+
+endmodule
diff --git a/tests_ok/autoinst_dedefine.v b/tests_ok/autoinst_dedefine.v
new file mode 100644
index 0000000..e768cb0
--- /dev/null
+++ b/tests_ok/autoinst_dedefine.v
@@ -0,0 +1,36 @@
+`define foo 6
+`define bar 0
+
+module autoinst_dedefine;
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [3:1] fourwide; // From sub of bar.v
+ output onewide; // From sub of bar.v
+ output [5:0] varwide; // From sub of bar.v
+ // End of automatics
+ /*AUTOWIRE*/
+
+ /* bar AUTO_TEMPLATE (
+ .\(.*\) (@"(concat vl-name (verilog-symbol-detick-text vl-bits))"),
+ ); */
+
+ bar sub
+ (/*AUTOINST*/
+ // Outputs
+ .onewide (onewide), // Templated
+ .fourwide (fourwide[3:1]), // Templated
+ .varwide (varwide[6-1:0])); // Templated
+
+endmodule
+
+module bar;
+ output onewide;
+ output [3:1] fourwide;
+ output [`foo-1:`bar] varwide;
+endmodule
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
+
diff --git a/tests_ok/autoinst_ding.v b/tests_ok/autoinst_ding.v
new file mode 100644
index 0000000..bc556fd
--- /dev/null
+++ b/tests_ok/autoinst_ding.v
@@ -0,0 +1,88 @@
+module AA(
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ input wire clock,
+ input wire reset,
+ input wire test_enable,
+ input wire afe_ctrl,
+ input wire cpu_wr,
+ input wire [4:0] cpu_addr,
+ input wire [7:0] cpu_wdata,
+ output wire [7:0] core_data,
+ output wire core_code_error,
+ output wire core_code_idle,
+ output wire [7:0] cpu_rdata
+ );
+endmodule
+
+module BB(
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ input wire clock,
+ input wire reset,
+ input wire test_enable,
+ input wire core_code_idle,
+ input wire core_code_error,
+ input wire [7:0] core_data,
+ input wire [8:0] mbist_done,
+ input wire [8:0] mbist_fail,
+ output wire mbist_rst,
+ output reg mbist_test
+ );
+endmodule
+
+module TOP(
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input afe_ctrl, // To AA_U of AA.v
+ input clock, // To AA_U of AA.v, ...
+ input [4:0] cpu_addr, // To AA_U of AA.v
+ input [7:0] cpu_wdata, // To AA_U of AA.v
+ input cpu_wr, // To AA_U of AA.v
+ input [8:0] mbist_done, // To BB_U of BB.v
+ input [8:0] mbist_fail, // To BB_U of BB.v
+ input reset, // To AA_U of AA.v, ...
+ input test_enable, // To AA_U of AA.v, ...
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [7:0] cpu_rdata, // From AA_U of AA.v
+ output mbist_rst, // From BB_U of BB.v
+ output mbist_test // From BB_U of BB.v
+ // End of automatics
+ );
+
+ AA AA_U(/*AUTOINST*/
+ // Outputs
+ .core_data (core_data[7:0]),
+ .core_code_error (core_code_error),
+ .core_code_idle (core_code_idle),
+ .cpu_rdata (cpu_rdata[7:0]),
+ // Inputs
+ .clock (clock),
+ .reset (reset),
+ .test_enable (test_enable),
+ .afe_ctrl (afe_ctrl),
+ .cpu_wr (cpu_wr),
+ .cpu_addr (cpu_addr[4:0]),
+ .cpu_wdata (cpu_wdata[7:0]));
+
+ BB BB_U(/*AUTOINST*/
+ // Outputs
+ .mbist_rst (mbist_rst),
+ .mbist_test (mbist_test),
+ // Inputs
+ .clock (clock),
+ .reset (reset),
+ .test_enable (test_enable),
+ .core_code_idle (core_code_idle),
+ .core_code_error (core_code_error),
+ .core_data (core_data[7:0]),
+ .mbist_done (mbist_done[8:0]),
+ .mbist_fail (mbist_fail[8:0]));
+
+ // Local Variables:
+ // verilog-library-directories:(".")
+ // End:
+
+endmodule
diff --git a/tests_ok/autoinst_for_myers.v b/tests_ok/autoinst_for_myers.v
new file mode 100644
index 0000000..dc7200e
--- /dev/null
+++ b/tests_ok/autoinst_for_myers.v
@@ -0,0 +1,53 @@
+module InstMod ( ins, outs );
+ output [INWIDTH-1:0] ins;
+ output [OUTWIDTH-1:0] outs;
+endmodule
+
+module test_top;
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [n*INWIDTH +: INWIDTH] ins; // From instName of InstMod.v
+ wire [n*INWIDTH +: INWIDTH] ins2; // From instName2 of InstMod.v
+ wire [n*INWIDTH +: INWIDTH] ins3; // From instName3 of InstMod.v, ..., Couldn't Merge
+ wire [n*OUTWIDTH +: OUTWIDTH] outs; // From instName of InstMod.v
+ wire [n*OUTWIDTH +: OUTWIDTH] outs2; // From instName2 of InstMod.v
+ wire [4*OUTWIDTH-1 : 0] outs3; // From instName3 of InstMod.v, ..., Couldn't Merge
+ // End of automatics
+
+ genvar i;
+ generate
+ for (i=0; i<4; i=i+1) begin
+ /*AUTO_LISP(setq vh-n 4)*/
+ /* InstMod AUTO_TEMPLATE
+ (.ins (ins [n*INWIDTH +: INWIDTH]),
+ .outs (outs[n*OUTWIDTH +: OUTWIDTH])); */
+
+ InstMod instName (/*AUTOINST*/
+ // Outputs
+ .ins (ins [n*INWIDTH +: INWIDTH]), // Templated
+ .outs (outs[n*OUTWIDTH +: OUTWIDTH])); // Templated
+
+ InstMod instName2
+ (// Inputs
+ .ins (ins2 [n*INWIDTH +: INWIDTH]),
+ // Outputs
+ .outs (outs2[n*OUTWIDTH +: OUTWIDTH])
+ /*AUTOINST*/);
+
+ // This works but is ugly
+ InstMod instName3
+ (// Inputs
+ .ins (ins3 [n*INWIDTH +: INWIDTH]),
+ // Outputs
+ .outs (outs3[n*OUTWIDTH +: OUTWIDTH])
+`ifdef NEVER
+ // Inouts
+ .ins (ins3 [4*INWIDTH-1 : 0]),
+ .outs (outs3[4*OUTWIDTH-1 : 0])
+`endif
+ /*AUTOINST*/);
+
+ end
+ endgenerate
+endmodule
diff --git a/tests_ok/autoinst_func.v b/tests_ok/autoinst_func.v
new file mode 100644
index 0000000..0682e4c
--- /dev/null
+++ b/tests_ok/autoinst_func.v
@@ -0,0 +1,45 @@
+module autoinst_func;
+
+ /*AUTO_LISP(defun testfunc (sig bits) (let ((result "{"))
+ (setq result (concat result sig "[0" bits "]"))
+ (concat result "}")))*/
+
+ /* autoinst_wildcard_sub AUTO_TEMPLATE (
+ .sd0_adrs@ (myport@"(substring \\"\1\\" 0 1)"),
+ .\(.*\) (@"(testfunc vl-name vl-bits)"),
+ ); */
+
+ autoinst_wildcard_sub sub0
+ (/*AUTOINST*/
+ // Inouts
+ .sd0_adrs0 (myport0), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs1 (myport1), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs10 (myport1), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs11 (myport1), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs2 (myport2), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs3 (myport3), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs4 (myport4), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs5 (myport5), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs6 (myport6), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs7 (myport7), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs8 (myport8), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_adrs9 (myport9), // Templated LHS: ^sd0_adrs\([0-9]+\)$
+ .sd0_ba0 ({sd0_ba0[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_ba1 ({sd0_ba1[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_clk ({sd0_clk[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm0_l ({sd0_dqm0_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm1_l ({sd0_dqm1_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm2_l ({sd0_dqm2_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm3_l ({sd0_dqm3_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm4_l ({sd0_dqm4_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm5_l ({sd0_dqm5_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm6_l ({sd0_dqm6_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd0_dqm7_l ({sd0_dqm7_l[0]}), // Templated LHS: ^\(.*\)$
+ .sd_ras_ ({sd_ras_[0]})); // Templated LHS: ^\(.*\)$
+
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-template-numbers: lhs
+// verilog-auto-inst-sort: t
+// End:
diff --git a/tests_ok/autoinst_gate.v b/tests_ok/autoinst_gate.v
new file mode 100644
index 0000000..126f885
--- /dev/null
+++ b/tests_ok/autoinst_gate.v
@@ -0,0 +1,39 @@
+//bug284
+
+module wrapper
+ (
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [1:0] bout, // From mybuf of buf
+ output [31:0] o, // From u_or of or
+ // End of automatics
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input [1:0] bin, // To mybuf of buf
+ input [31:0] i0, // To u_or of or
+ input [31:0] i1, // To u_or of or
+ input [31:0] i2, // To u_or of or
+ input [31:0] i3 // To u_or of or
+ // End of automatics
+ );
+
+ //--------------------------------------------------------------------------
+
+ // Note input/output comments aren't needed, and multiple signals
+ // per line are ok
+ or u_or [31:0]
+ (o[31:0], i0[31:0], i1[31:0], i2[31:0],
+ // Inputs,
+ i3[31:0]
+ /*AUTOINST*/);
+
+ // bug676
+ buf # 1 mybuf[1:0]
+ (bout[1:0],
+ // Inputs,
+ bin[1:0]
+ /*AUTOINST*/);
+
+ //--------------------------------------------------------------------------
+
+endmodule
diff --git a/tests_ok/autoinst_genvar.v b/tests_ok/autoinst_genvar.v
new file mode 100644
index 0000000..689fe4d
--- /dev/null
+++ b/tests_ok/autoinst_genvar.v
@@ -0,0 +1,54 @@
+module AA(
+ input wire clock,
+ input wire reset,
+ input wire test_enable,
+ input wire afe_ctrl,
+ input wire cpu_wr,
+ input wire [4:0] cpu_addr,
+ input wire [7:0] cpu_wdata,
+ output wire [7:0] core_data,
+ output wire core_code_error,
+ output wire core_code_idle,
+ output wire [7:0] cpu_rdata
+ );
+endmodule
+
+module TOP(
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input afe_ctrl, // To AA_U of AA.v
+ input clock, // To AA_U of AA.v
+ input [4:0] cpu_addr, // To AA_U of AA.v
+ input [7:0] cpu_wdata, // To AA_U of AA.v
+ input cpu_wr, // To AA_U of AA.v
+ input reset, // To AA_U of AA.v
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output core_code_error, // From AA_U of AA.v
+ output core_code_idle, // From AA_U of AA.v
+ output [7:0] core_data, // From AA_U of AA.v
+ output [7:0] cpu_rdata // From AA_U of AA.v
+ // End of automatics
+ );
+
+ genvar x;
+
+ AA AA_U(
+ // Inputs
+ .test_enable (x),
+ /*AUTOINST*/
+ // Outputs
+ .core_data (core_data[7:0]),
+ .core_code_error (core_code_error),
+ .core_code_idle (core_code_idle),
+ .cpu_rdata (cpu_rdata[7:0]),
+ // Inputs
+ .clock (clock),
+ .reset (reset),
+ .afe_ctrl (afe_ctrl),
+ .cpu_wr (cpu_wr),
+ .cpu_addr (cpu_addr[4:0]),
+ .cpu_wdata (cpu_wdata[7:0]));
+
+endmodule
diff --git a/tests_ok/autoinst_iface270_sub.v b/tests_ok/autoinst_iface270_sub.v
new file mode 100644
index 0000000..48f6220
--- /dev/null
+++ b/tests_ok/autoinst_iface270_sub.v
@@ -0,0 +1,9 @@
+// See http://www.veripool.org/issues/show/270
+
+interface autoinst_iface270_sub;
+ logic a;
+ logic b;
+ modport master_mp(input a, output b);
+ modport slave_mp(output a, input b);
+ modport monitor (input a, input b);
+endinterface
diff --git a/tests_ok/autoinst_iface270_top.v b/tests_ok/autoinst_iface270_top.v
new file mode 100644
index 0000000..26f5726
--- /dev/null
+++ b/tests_ok/autoinst_iface270_top.v
@@ -0,0 +1,16 @@
+// See http://www.veripool.org/issues/show/270
+
+module top;
+ /*AUTOWIRE*/
+
+ autoinst_iface270_sub inst_if (/*AUTOINST*/);
+
+ ifio sub (/*AUTOINST*/
+ // Interfaces
+ .inst_if (inst_if));
+
+endmodule
+
+module ifio
+ (autoinst_iface270_sub inst_if);
+endmodule
diff --git a/tests_ok/autoinst_iface270_top_bug429.v b/tests_ok/autoinst_iface270_top_bug429.v
new file mode 100644
index 0000000..e76564c
--- /dev/null
+++ b/tests_ok/autoinst_iface270_top_bug429.v
@@ -0,0 +1,20 @@
+// See http://www.veripool.org/issues/show/429
+
+module top;
+ /*AUTOWIRE*/
+
+ autoinst_iface270_sub inst_if (/*AUTOINST*/);
+
+ ifio sub (/*AUTOINST*/
+ // Interfaces
+ .inst_if (inst_if));
+
+endmodule
+
+module ifio
+ (autoinst_iface270_sub inst_if);
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-interfaced-ports: nil
+// End:
diff --git a/tests_ok/autoinst_ifdef_fredrickson_200503_sub.v b/tests_ok/autoinst_ifdef_fredrickson_200503_sub.v
new file mode 100644
index 0000000..677b97b
--- /dev/null
+++ b/tests_ok/autoinst_ifdef_fredrickson_200503_sub.v
@@ -0,0 +1,15 @@
+module autoinst_ifdef_fredrickson_200503_sub
+ (input a,
+`ifdef TEST
+ input c,
+ output wire d,
+`endif
+ output wire b
+ );
+
+ assign b = a;
+`ifdef TEST
+ assign d = c;
+`endif
+
+endmodule // define_sub
diff --git a/tests_ok/autoinst_ifdef_fredrickson_200503_top.v b/tests_ok/autoinst_ifdef_fredrickson_200503_top.v
new file mode 100644
index 0000000..38f076e
--- /dev/null
+++ b/tests_ok/autoinst_ifdef_fredrickson_200503_top.v
@@ -0,0 +1,12 @@
+module autoinst_ifdef_fredrickson_200503_top();
+
+ autoinst_ifdef_fredrickson_200503_sub sub
+ (/*AUTOINST*/
+ // Outputs
+ .d (d),
+ .b (b),
+ // Inputs
+ .a (a),
+ .c (c));
+
+endmodule // define_top
diff --git a/tests_ok/autoinst_import.v b/tests_ok/autoinst_import.v
new file mode 100644
index 0000000..53816f6
--- /dev/null
+++ b/tests_ok/autoinst_import.v
@@ -0,0 +1,37 @@
+//bug709
+
+module InstModule
+ (input clk,
+ svi.master svi_modport,
+ svi svi_nomodport);
+endmodule // InstModule
+
+module InstModule1 import mdp_pkg::*;
+ (input clk,
+ svi.master svi_modport,
+ svi svi_nomodport);
+endmodule
+
+module top;
+ InstModule instName
+ (/*AUTOINST*/
+ // Interfaces
+ .svi_modport (svi_modport.master),
+ .svi_nomodport (svi_nomodport),
+ // Inputs
+ .clk (clk));
+
+ InstModule1 instName1
+ (/*AUTOINST*/
+ // Interfaces
+ .svi_modport (svi_modport.master),
+ .svi_nomodport (svi_nomodport),
+ // Inputs
+ .clk (clk));
+
+endmodule
+
+// Local Variables:
+// verilog-library-directories:(".")
+// verilog-library-extensions:(".v" ".sv")
+// End:
diff --git a/tests_ok/autoinst_instname_all.v b/tests_ok/autoinst_instname_all.v
new file mode 100644
index 0000000..53c7d82
--- /dev/null
+++ b/tests_ok/autoinst_instname_all.v
@@ -0,0 +1,17 @@
+module ex;
+
+ /* autoinst_paramover_sub AUTO_TEMPLATE (
+ .\(.*\)(@"vl-cell-name"_\1),
+ );*/
+
+ autoinst_paramover_sub u_a0(/*AUTOINST*/
+ // Inouts
+ .a (u_a0_a), // Templated
+ .b (u_a0_b)); // Templated
+
+ autoinst_paramover_sub u_a1(/*AUTOINST*/
+ // Inouts
+ .a (u_a1_a), // Templated
+ .b (u_a1_b)); // Templated
+
+endmodule
diff --git a/tests_ok/autoinst_instname_carlh.v b/tests_ok/autoinst_instname_carlh.v
new file mode 100644
index 0000000..518eea4
--- /dev/null
+++ b/tests_ok/autoinst_instname_carlh.v
@@ -0,0 +1,18 @@
+module ex;
+
+ /* autoinst_paramover_sub AUTO_TEMPLATE (
+ .a(@"vl-cell-name"_in[]),
+ .b(@"(substring inst 2)"_out[]),
+ );*/
+
+ autoinst_paramover_sub u_a0(/*AUTOINST*/
+ // Inouts
+ .a (u_a0_in[bitsa:0]), // Templated
+ .b (a0_out[bitsb:0])); // Templated
+
+ autoinst_paramover_sub u_a1(/*AUTOINST*/
+ // Inouts
+ .a (u_a1_in[bitsa:0]), // Templated
+ .b (a1_out[bitsb:0])); // Templated
+
+endmodule
diff --git a/tests_ok/autoinst_interface.v b/tests_ok/autoinst_interface.v
new file mode 100644
index 0000000..8663970
--- /dev/null
+++ b/tests_ok/autoinst_interface.v
@@ -0,0 +1,50 @@
+// See bug75
+
+module autoinst_interface
+ (/*AUTOINOUTMODULE("autoinst_interface_sub")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output logic [7:0] count,
+ input logic clk,
+ input logic reset,
+ input logic start,
+ my_svi.master my_svi_port,
+ my_svi my_svi_noport,
+ my_svi my_svi_noport_upper_decl
+ // End of automatics
+ );
+endmodule
+
+module autoinst_interface
+ (/*AUTOINOUTCOMP("autoinst_interface_sub")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output logic clk,
+ output logic reset,
+ output logic start,
+ input logic [7:0] count,
+ my_svi.master my_svi_port,
+ my_svi my_svi_noport,
+ my_svi my_svi_noport_upper_decl
+ // End of automatics
+ );
+endmodule
+
+module top;
+ /*AUTOLOGIC*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic [7:0] count; // From submod0 of autoinst_interface_sub.v
+ // End of automatics
+
+ my_svi my_svi_noport_upper_decl ();
+
+ autoinst_interface_sub submod0 (/*AUTOINST*/
+ // Interfaces
+ .my_svi_port (my_svi_port.master),
+ .my_svi_noport (my_svi_noport),
+ .my_svi_noport_upper_decl(my_svi_noport_upper_decl),
+ // Outputs
+ .count (count[7:0]),
+ // Inputs
+ .clk (clk),
+ .reset (reset),
+ .start (start));
+endmodule
diff --git a/tests_ok/autoinst_interface_bug320.v b/tests_ok/autoinst_interface_bug320.v
new file mode 100644
index 0000000..69be62a
--- /dev/null
+++ b/tests_ok/autoinst_interface_bug320.v
@@ -0,0 +1,16 @@
+// See bug320
+
+interface intf1;
+ logic a;
+ logic b;
+ modport mp1 (input a, output b);
+endinterface
+
+interface intf2 (intf1.mp1 c);
+ logic e;
+endinterface
+
+module top;
+ intf1 c(.*);
+ intf2 f(.*);
+endmodule
diff --git a/tests_ok/autoinst_interface_star.v b/tests_ok/autoinst_interface_star.v
new file mode 100644
index 0000000..f74d340
--- /dev/null
+++ b/tests_ok/autoinst_interface_star.v
@@ -0,0 +1,37 @@
+// See bug75
+
+module autoinst_interface
+ (/*AUTOINOUTMODULE("autoinst_interface_sub")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output [7:0] count,
+ input clk,
+ input reset,
+ input start,
+ my_svi.master my_svi_port,
+ my_svi my_svi_noport,
+ my_svi my_svi_noport_upper_decl
+ // End of automatics
+ );
+endmodule
+
+module autoinst_interface
+ (/*AUTOINOUTCOMP("autoinst_interface_sub")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output clk,
+ output reset,
+ output start,
+ input [7:0] count,
+ my_svi.master my_svi_port,
+ my_svi my_svi_noport,
+ my_svi my_svi_noport_upper_decl
+ // End of automatics
+ );
+endmodule
+
+module top;
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [7:0] count; // From submod0 of autoinst_interface_sub.v
+ // End of automatics
+ autoinst_interface_sub submod0 (.*);
+endmodule
diff --git a/tests_ok/autoinst_interface_sub.v b/tests_ok/autoinst_interface_sub.v
new file mode 100644
index 0000000..5b168ae
--- /dev/null
+++ b/tests_ok/autoinst_interface_sub.v
@@ -0,0 +1,20 @@
+interface my_svi;
+ logic enable;
+ logic error;
+ logic [7:0] count2;
+ modport master (
+ input enable,
+ output error,
+ output count2);
+endinterface
+
+module autoinst_interface_sub
+ (input wire clk,
+ input wire reset,
+ input wire start,
+ output reg [7:0] count,
+ my_svi.master my_svi_port,
+ my_svi my_svi_noport,
+ my_svi my_svi_noport_upper_decl
+ );
+endmodule
diff --git a/tests_ok/autoinst_johnson.v b/tests_ok/autoinst_johnson.v
new file mode 100644
index 0000000..2812baa
--- /dev/null
+++ b/tests_ok/autoinst_johnson.v
@@ -0,0 +1,35 @@
+module bfm (/*AUTOARG*/
+ // Inputs
+ name
+ );
+ input [8*5:1] name ;
+endmodule
+
+module tb;
+ // -------------------------------------------------------------------------
+ /*AUTOOUTPUT*/
+ // -------------------------------------------------------------------------
+ /*AUTOINPUT*/
+ // -------------------------------------------------------------------------
+ /*AUTOWIRE*/
+ // -------------------------------------------------------------------------
+ /* AUTO_CONSTANT ( "name0" "name1" "name2" ) */
+ // -------------------------------------------------------------------------
+ /* bfm AUTO_TEMPLATE (
+ // Inputs
+ .name ("name@"));
+ */
+ // -------------------------------------------------------------------------
+ bfm bmf0 (/*AUTOINST*/
+ // Inputs
+ .name ("name0")); // Templated
+ // -------------------------------------------------------------------------
+ bfm bmf1 (/*AUTOINST*/
+ // Inputs
+ .name ("name1")); // Templated
+ // -------------------------------------------------------------------------
+ bfm bmf2 (/*AUTOINST*/
+ // Inputs
+ .name ("name2")); // Templated
+ // -------------------------------------------------------------------------
+endmodule
diff --git a/tests_ok/autoinst_lopaz.v b/tests_ok/autoinst_lopaz.v
new file mode 100644
index 0000000..34662de
--- /dev/null
+++ b/tests_ok/autoinst_lopaz.v
@@ -0,0 +1,76 @@
+module io1_sub(
+ /*AUTOARG*/);
+
+ wire [42:0] bscan_data; // boundary scan stitch
+ parameter bscan_count = 0;
+
+ assign bscan_data[0] = bscan_in;
+
+ /*
+ * Emacs template to auto instaniate MD[31:0] pads
+ */
+ /*
+ autoinst_lopaz_srpad AUTO_TEMPLATE (
+ .pin(MD[@]),
+ .pin_in({SDRAM_DQ_in[@],SDRAM_DQ_in[@]}),
+ .pin_out(SDRAM_DQ_out[@]),
+ .pin_outen(SDRAM_DQ_outen),
+ .sdrmode(SDRAM_single_rate),
+ .hw_enb(SDRAM_upper_word_enb),
+ .ff_rptr(SDRAM_ddr_inff_sel),
+ .ff_wptr(ddr_inff_enbH),
+ .clk(data_strobeH),
+ .bscan_so(bscan_data[@ + 1]),
+ .bscan_si(bscan_data[@]),
+ .bscan_shift(BScanShift),
+ .bscan_clock(BScanClock),
+ .bscan_mode(BScanMode),
+ .bscan_update(BScanUpdate),
+ .bscan_outen(SDRAM_DQ_bscan_outen),
+ );
+ */
+
+ autoinst_lopaz_srpad MD31_pad (/*AUTOINST*/
+ // Outputs
+ .pin_in ({SDRAM_DQ_in[31],SDRAM_DQ_in[31]}), // Templated
+ // Inouts
+ .pin (MD[31]), // Templated
+ // Inputs
+ .clk (data_strobeH), // Templated
+ .pin_out (SDRAM_DQ_out[31]), // Templated
+ .pin_outen (SDRAM_DQ_outen)); // Templated
+
+
+ /* autoinst_lopaz_srpad AUTO_TEMPLATE (
+ .pin(MD[@"num"]),
+ );
+ */
+
+ /*AUTO_LISP(setq num 1)*/
+ autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/
+ // Outputs
+ .pin_in (pin_in[2*w-1:0]),
+ // Inouts
+ .pin (MD[1]), // Templated
+ // Inputs
+ .clk (clk),
+ .pin_out (pin_out[w-1:0]),
+ .pin_outen (pin_outen));
+
+ /* autoinst_lopaz_srpad AUTO_TEMPLATE (
+ .pin(MD[@"num"]),
+ );
+ */
+
+ /*AUTO_LISP(setq num 2)*/
+ autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/
+ // Outputs
+ .pin_in (pin_in[2*w-1:0]),
+ // Inouts
+ .pin (MD[2]), // Templated
+ // Inputs
+ .clk (clk),
+ .pin_out (pin_out[w-1:0]),
+ .pin_outen (pin_outen));
+
+endmodule
diff --git a/tests_ok/autoinst_lopaz_srpad.v b/tests_ok/autoinst_lopaz_srpad.v
new file mode 100644
index 0000000..0a49815
--- /dev/null
+++ b/tests_ok/autoinst_lopaz_srpad.v
@@ -0,0 +1,17 @@
+module autoinst_lopaz_srpad (/*AUTOARG*/
+ // Outputs
+ pin_in,
+ // Inouts
+ pin,
+ // Inputs
+ clk, pin_out, pin_outen
+ );
+ parameter w = 1;
+ input clk;
+
+ inout [w-1:0] pin;
+ output [2*w-1:0] pin_in;
+ input [w-1:0] pin_out;
+ input pin_outen;
+
+endmodule
diff --git a/tests_ok/autoinst_ma_io_prefix.v b/tests_ok/autoinst_ma_io_prefix.v
new file mode 100644
index 0000000..df0969e
--- /dev/null
+++ b/tests_ok/autoinst_ma_io_prefix.v
@@ -0,0 +1,99 @@
+// From: "Ma, Zhenqiang" <Zhenqiang.Ma@caviumnetworks.com>
+
+module test (
+ // Ports for module A
+ input i_A_outsidei,
+ output o_A_outsideo,
+
+ // Ports for module B
+ input i_B_outsidei,
+ output o_B_outsideo );
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire A_internal; // From u0 of moduleA.v
+ wire B_internal; // From u1 of moduleB.v
+ // End of automatics
+
+ //-----------------------------------------------------------------------------
+ // instantiate module A
+ //-----------------------------------------------------------------------------
+
+ /* moduleA AUTO_TEMPLATE (
+ .[iot]_\(.*\) (@"(vl-prefix-i-o \\"\1\\")"\1[]),
+ ); */
+
+ moduleA u0(
+ /*AUTOINST*/
+ // Outputs
+ .o_A_outsideo (o_A_outsideo), // Templated
+ .o_A_internal (A_internal), // Templated
+ // Inputs
+ .i_A_outsidei (i_A_outsidei), // Templated
+ .i_B_internal (B_internal)); // Templated
+
+
+ //-----------------------------------------------------------------------------
+ // instantiate module B
+ //-----------------------------------------------------------------------------
+
+ /* moduleB AUTO_TEMPLATE (
+ .[iot]_\(.*\) (@"(vl-prefix-i-o \\"\1\\")"\1[]),
+ ); */
+
+ moduleB u1(
+ /*AUTOINST*/
+ // Outputs
+ .o_B_outsideo (o_B_outsideo), // Templated
+ .o_B_internal (B_internal), // Templated
+ // Inputs
+ .i_B_outsidei (i_B_outsidei), // Templated
+ .i_A_internal (A_internal)); // Templated
+
+
+endmodule
+
+module moduleA (
+ input i_A_outsidei,
+ output o_A_outsideo,
+
+ input i_B_internal,
+ output o_A_internal
+ );
+ /*AUTOTIEOFF*/
+ // Beginning of automatic tieoffs (for this module's unterminated outputs)
+ wire o_A_internal = 1'h0;
+ wire o_A_outsideo = 1'h0;
+ // End of automatics
+endmodule
+
+module moduleB (
+ input i_B_outsidei,
+ output o_B_outsideo,
+
+ input i_A_internal,
+ output o_B_internal
+ );
+ /*AUTOTIEOFF*/
+ // Beginning of automatic tieoffs (for this module's unterminated outputs)
+ wire o_B_internal = 1'h0;
+ wire o_B_outsideo = 1'h0;
+ // End of automatics
+endmodule
+
+/*
+ Local Variables:
+ eval:
+ (defun vl-prefix-i-o (basename)
+ (cond ((assoc (concat "i_" basename)
+ (verilog-decls-get-inputs moddecls))
+ "i_")
+ ((assoc (concat "o_" basename)
+ (verilog-decls-get-outputs moddecls))
+ "o_")
+ ((assoc (concat "t_" basename)
+ (verilog-decls-get-inouts moddecls))
+ "t_")
+ (t "")))
+ End:
+ */
diff --git a/tests_ok/autoinst_mccoy.v b/tests_ok/autoinst_mccoy.v
new file mode 100644
index 0000000..2f9d3a3
--- /dev/null
+++ b/tests_ok/autoinst_mccoy.v
@@ -0,0 +1,33 @@
+module top
+
+ // no-connecting unused outputs of an interface and tying only inputs to gnd.
+
+ // Requested:
+ //
+ // /* xx AUTO_TEMPLATE (
+ //.TWI_\(.*\) @"(vl-dir (input)" ({@"vl-width"{1'b0}}),
+ //.TWI_\(.*\) @"(vl-dir (output)" (),
+ //);
+ // */
+
+ /* xx AUTO_TEMPLATE (
+ .TWI_\(.*\) (@"(if (equal vl-dir \\"output\\") \\"\\" (concat vl-width \\"'b0\\"))"),
+ );
+ */
+
+ xx XX (/*AUTOINST*/
+ // Outputs
+ .TWI_qb (), // Templated
+ // Inputs
+ .clk (clk),
+ .TWI_ia (1'b0), // Templated
+ .TWI_iw (16'b0)); // Templated
+endmodule
+
+module xx
+ (input clk,
+
+ input TWI_ia,
+ input [15:0] TWI_iw,
+ output TWI_qb);
+endmodule
diff --git a/tests_ok/autoinst_moddefine.v b/tests_ok/autoinst_moddefine.v
new file mode 100644
index 0000000..7be2c0c
--- /dev/null
+++ b/tests_ok/autoinst_moddefine.v
@@ -0,0 +1,60 @@
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008-2008 by Wilson Snyder.
+
+module autoinst_moddefine (/*AUTOARG*/);
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire q; // From `SUBNAME_B of `SUBMOD_A.v, ...
+ // End of automatics
+
+`define SUBMOD_A submod_mod
+`define SUBNAME_B subname_b
+
+ `SUBMOD_A `SUBNAME_B
+ (/*AUTOINST*/
+ // Outputs
+ .q (q),
+ // Inputs
+ .a (a));
+
+ `SUBMOD_UNDEFED subundefed
+ (/*AUTOINST*/
+ // Outputs
+ .q (q));
+
+ submod_decl_from_def subundefed
+ (/*AUTOINST*/
+ // Outputs
+ .q (q));
+
+endmodule
+
+module submod_mod (/*AUTOARG*/
+ // Outputs
+ q,
+ // Inputs
+ a
+ );
+ input a;
+ output q;
+endmodule
+
+module SUBMOD_UNDEFED (/*AUTOARG*/
+ // Outputs
+ q
+ );
+ output q;
+endmodule
+
+`define SUBMOD_DECL submod_decl_from_def
+module `SUBMOD_DECL (/*AUTOARG*/
+ // Outputs
+ q
+ );
+ output q;
+endmodule
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests_ok/autoinst_modport_param.v b/tests_ok/autoinst_modport_param.v
new file mode 100644
index 0000000..2c8d09b
--- /dev/null
+++ b/tests_ok/autoinst_modport_param.v
@@ -0,0 +1,38 @@
+//bug565
+
+module InstModule
+ (svi.master svi_modport,
+ input clk,
+ svi svi_nomodport);
+endmodule
+
+module InstModule1 #
+ (parameter TCQ = 100)
+ (svi.master svi_modport,
+ input clk,
+ svi svi_nomodport);
+endmodule
+
+module top;
+ InstModule instName
+ (/*AUTOINST*/
+ // Interfaces
+ .svi_modport (svi_modport.master),
+ .svi_nomodport (svi_nomodport),
+ // Inputs
+ .clk (clk));
+
+ InstModule1 instName1
+ (/*AUTOINST*/
+ // Interfaces
+ .svi_modport (svi_modport.master),
+ .svi_nomodport (svi_nomodport),
+ // Inputs
+ .clk (clk));
+
+endmodule
+
+// Local Variables:
+// verilog-library-directories:(".")
+// verilog-library-extensions:(".v" ".sv")
+// End:
diff --git a/tests_ok/autoinst_mplist.sv b/tests_ok/autoinst_mplist.sv
new file mode 100644
index 0000000..462ebb9
--- /dev/null
+++ b/tests_ok/autoinst_mplist.sv
@@ -0,0 +1,66 @@
+
+// Parent module
+// Specifies modport for interfaces in header.
+// Has child modules which do the same.
+
+module autoinst_mplist
+ (
+ // --------------------------------------------------------------------------
+ // Port Declarations
+ // --------------------------------------------------------------------------
+
+ input clk,
+ input reset_n,
+
+ // Top-level interfaces
+ mbl_if.master msg_resp_if
+
+ );
+
+ mbl_if msg_req_if; // Some internal interface
+
+ // --------------------------------------------------------------------------
+ // Packages and Local Declarations
+ // --------------------------------------------------------------------------
+
+ /*AUTOLOGIC*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic mem_rd_req; // From child of autoinst_mplist_child.v
+ logic msg_busy; // From child of autoinst_mplist_child.v
+ // End of automatics
+
+
+ // --------------------------------------------------------------------------
+ // Module Body
+ // --------------------------------------------------------------------------
+
+ // For the module instance below, interface ports should be
+ // connected (per standard AUTOINST fashion) but *without*
+ // explicitly specifying the modport.
+ //
+ // VCS (and likely other Synopsys tools) don't expect to see a
+ // modport being "respecified" here.
+
+ autoinst_mplist_child child
+ (/*AUTOINST*/
+ // Interfaces
+ .msg_req_if (msg_req_if.slave),
+ .msg_resp_if (msg_resp_if),
+ // Outputs
+ .msg_busy (msg_busy),
+ .mem_rd_req (mem_rd_req),
+ // Inputs
+ .clk (clk),
+ .reset_n (reset_n),
+ .mem_rd_gnt (mem_rd_gnt));
+
+
+endmodule
+
+/*
+ Local Variables:
+ verilog-typedef-regexp:"_t$"
+ verilog-library-directories:(".")
+ verilog-library-extensions:(".sv")
+ End:
+ */
diff --git a/tests_ok/autoinst_mplist_child.sv b/tests_ok/autoinst_mplist_child.sv
new file mode 100644
index 0000000..2ae7a3e
--- /dev/null
+++ b/tests_ok/autoinst_mplist_child.sv
@@ -0,0 +1,33 @@
+// Child module
+// ... with interface modport specified in module header
+
+module autoinst_mplist_child
+ (
+ // --------------------------------------------------------------------------
+ // Port Declarations
+ // --------------------------------------------------------------------------
+
+ input clk,
+ input reset_n,
+
+ // Yeah, let's have an interface
+ autoinst_mplist_mbl_if.slave msg_req_if,
+ autoinst_mplist_mbl_if.master msg_resp_if,
+
+ // There are likely other signals present, too
+ output logic msg_busy,
+ output logic mem_rd_req,
+ input mem_rd_gnt
+ );
+
+ // Really snazzy RTL follows...
+
+endmodule
+
+/*
+ Local Variables:
+ verilog-typedef-regexp:"_t$"
+ verilog-library-directories:(".")
+ verilog-library-extensions:(".sv")
+ End:
+ */
diff --git a/tests_ok/autoinst_mplist_mbl_if.sv b/tests_ok/autoinst_mplist_mbl_if.sv
new file mode 100644
index 0000000..3810f0d
--- /dev/null
+++ b/tests_ok/autoinst_mplist_mbl_if.sv
@@ -0,0 +1,27 @@
+// Example interface definition with at least one modport.
+
+interface autoinst_mplist_mbl_if ();
+
+ logic sof;
+ logic eof;
+ logic [31:0] data;
+ logic ready;
+ logic valid;
+
+ modport master(
+ output data,
+ output sof,
+ output eof,
+ output valid,
+ input ready
+ );
+
+ modport slave(
+ input data,
+ input sof,
+ input eof,
+ input valid,
+ output ready
+ );
+
+endinterface
diff --git a/tests_ok/autoinst_multidim.v b/tests_ok/autoinst_multidim.v
new file mode 100644
index 0000000..fe4b8f8
--- /dev/null
+++ b/tests_ok/autoinst_multidim.v
@@ -0,0 +1,58 @@
+module top;
+ /*AUTOLOGIC*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic sig1; // From u_x of x.v
+ logic [A-1:0] sig2; // From u_x of x.v
+ logic [A-1:0] [B-1:0] sig3; // From u_x of x.v
+ logic [A-1:0][B-1:0] [C-1:0] sig4; // From u_x of x.v
+ logic [A-1:0][B-1:0][C-1:0] [D-1:0] sig5; // From u_x of x.v
+ logic vsig1; // From u_x of x.v
+ logic vsig2 [W-1:0]; // From u_x of x.v
+ logic vsig3 [W-1:0][X-1:0]; // From u_x of x.v
+ logic vsig4 [W-1:0][X-1:0][Y-1:0];// From u_x of x.v
+ logic vsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];// From u_x of x.v
+ logic zsig1; // From u_x of x.v
+ logic [A-1:0] zsig2 [W-1:0]; // From u_x of x.v
+ logic [A-1:0] [B-1:0] zsig3 [W-1:0][X-1:0]; // From u_x of x.v
+ logic [A-1:0][B-1:0] [C-1:0] zsig4 [W-1:0][X-1:0][Y-1:0];// From u_x of x.v
+ logic [A-1:0][B-1:0][C-1:0] [D-1:0] zsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];// From u_x of x.v
+ // End of automatics
+
+ x u_x (/*AUTOINST*/
+ // Outputs
+ .sig1 (sig1),
+ .sig2 (sig2[A-1:0]),
+ .sig3 (sig3/*[A-1:0][B-1:0]*/),
+ .sig4 (sig4/*[A-1:0][B-1:0][C-1:0]*/),
+ .sig5 (sig5/*[A-1:0][B-1:0][C-1:0][D-1:0]*/),
+ .vsig1 (vsig1),
+ .vsig2 (vsig2/*.[W-1:0]*/),
+ .vsig3 (vsig3/*.[W-1:0][X-1:0]*/),
+ .vsig4 (vsig4/*.[W-1:0][X-1:0][Y-1:0]*/),
+ .vsig5 (vsig5/*.[W-1:0][X-1:0][Y-1:0][Z-1:0]*/),
+ .zsig1 (zsig1),
+ .zsig2 (zsig2/*[A-1:0].[W-1:0]*/),
+ .zsig3 (zsig3/*[A-1:0][B-1:0].[W-1:0][X-1:0]*/),
+ .zsig4 (zsig4/*[A-1:0][B-1:0][C-1:0].[W-1:0][X-1:0][Y-1:0]*/),
+ .zsig5 (zsig5/*[A-1:0][B-1:0][C-1:0][D-1:0].[W-1:0][X-1:0][Y-1:0][Z-1:0]*/));
+endmodule // top
+
+module x;
+ output sig1;
+ output [A-1:0] sig2;
+ output [A-1:0][B-1:0] sig3;
+ output [A-1:0][B-1:0][C-1:0] sig4;
+ output [A-1:0][B-1:0][C-1:0][D-1:0] sig5;
+
+ output vsig1;
+ output vsig2 [W-1:0];
+ output vsig3 [W-1:0][X-1:0];
+ output vsig4 [W-1:0][X-1:0][Y-1:0];
+ output vsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];
+
+ output zsig1;
+ output [A-1:0] zsig2 [W-1:0];
+ output [A-1:0][B-1:0] zsig3 [W-1:0][X-1:0];
+ output [A-1:0][B-1:0][C-1:0] zsig4 [W-1:0][X-1:0][Y-1:0];
+ output [A-1:0][B-1:0][C-1:0][D-1:0] zsig5 [W-1:0][X-1:0][Y-1:0][Z-1:0];
+endmodule
diff --git a/tests_ok/autoinst_multitemplate.v b/tests_ok/autoinst_multitemplate.v
new file mode 100644
index 0000000..716573a
--- /dev/null
+++ b/tests_ok/autoinst_multitemplate.v
@@ -0,0 +1,51 @@
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Wilson Snyder.
+
+// Reported by Julian Gorfajn <jig1@cornell.edu>
+
+module autoinst_multitemplate ();
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input Boo1; // To suba1 of SubA.v
+ input Boo2; // To suba2 of SubB.v
+ input Boo3; // To suba3 of SubC.v
+ input b; // To suba2 of SubB.v
+ input c; // To suba3 of SubC.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+
+ /*AUTOWIRE*/
+
+ wire [3:0] f4_dotnamed;
+
+ /*
+ SubA AUTO_TEMPLATE
+ SubB AUTO_TEMPLATE
+ SubC AUTO_TEMPLATE (
+ .a (Boo@),
+ );*/
+
+ SubA suba1 (/*AUTOINST*/
+ // Inputs
+ .a (Boo1)); // Templated
+ SubB suba2 (/*AUTOINST*/
+ // Inputs
+ .a (Boo2), // Templated
+ .b (b));
+ SubC suba3 (/*AUTOINST*/
+ // Inputs
+ .a (Boo3), // Templated
+ .c (c));
+
+endmodule
+
+module SubA (input a);
+endmodule
+
+module SubB (input a,input b);
+endmodule
+
+module SubC (input a,input c );
+endmodule
diff --git a/tests_ok/autoinst_name_bug245.v b/tests_ok/autoinst_name_bug245.v
new file mode 100644
index 0000000..6f63606
--- /dev/null
+++ b/tests_ok/autoinst_name_bug245.v
@@ -0,0 +1,189 @@
+module autoinst_name_bug245 (
+ );
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input \escaped*dot*named ; // To sub of Sub.v
+ input logic clk; // To sub of Sub.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [2:0] a_NO; // From sub of Sub.v
+ output [1:0] bign2_dotnamed; // From sub of Sub.v
+ output c_dotnamed; // From sub of Sub.v
+ output d_NO; // From sub of Sub.v
+ output etmp_dotnamed; // From sub of Sub.v
+ output [3:0] f4_dotnamed; // From sub of Sub.v
+ // End of automatics
+
+ /*AUTOWIRE*/
+
+ wire [3:0] f4_dotnamed;
+
+ /*Sub AUTO_TEMPLATE (
+ .dtmp_NO (d_NO),
+ .etmp_dotnamed (etmp_dotnamed),
+ );*/
+
+ Sub sub (
+ .bign1_dotnamed,
+ // Outputs
+ .bign2_dotnamed,
+ /*AUTOINST*/
+ // Outputs
+ .a_NO (a_NO[2:0]),
+ .f4_dotnamed,
+ .c_dotnamed,
+ .dtmp_NO (d_NO), // Templated
+ .etmp_dotnamed, // Templated
+ // Inputs
+ .clk,
+ .\escaped*dot*named );
+
+endmodule
+
+module Sub
+ (
+ input logic clk,
+ output [2:0] a_NO,
+ output [3:0] f4_dotnamed,
+ output bign1_dotnamed,
+ output [1:0] bign2_dotnamed,
+ output c_dotnamed,
+ output dtmp_NO,
+ output etmp_dotnamed,
+ input \escaped*dot*named
+ );
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-dot-name: t
+// verilog-auto-inst-vector: nil
+// End:
+module autoinst_name_bug245 (
+ );
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input \escaped*dot*named ; // To sub of Sub.v
+ input logic clk; // To sub of Sub.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [2:0] a_NO; // From sub of Sub.v
+ output [1:0] bign2_dotnamed; // From sub of Sub.v
+ output c_dotnamed; // From sub of Sub.v
+ output d_NO; // From sub of Sub.v
+ output etmp_dotnamed; // From sub of Sub.v
+ output [3:0] f4_dotnamed; // From sub of Sub.v
+ // End of automatics
+
+ /*AUTOWIRE*/
+
+ wire [3:0] f4_dotnamed;
+
+ /*Sub AUTO_TEMPLATE (
+ .dtmp_NO (d_NO),
+ .etmp_dotnamed (etmp_dotnamed),
+ );*/
+
+ Sub sub (
+ .bign1_dotnamed,
+ // Outputs
+ .bign2_dotnamed,
+ /*AUTOINST*/
+ // Outputs
+ .a_NO (a_NO[2:0]),
+ .f4_dotnamed,
+ .c_dotnamed,
+ .dtmp_NO (d_NO), // Templated
+ .etmp_dotnamed, // Templated
+ // Inputs
+ .clk,
+ .\escaped*dot*named );
+
+endmodule
+
+module Sub
+ (
+ input logic clk,
+ output [2:0] a_NO,
+ output [3:0] f4_dotnamed,
+ output bign1_dotnamed,
+ output [1:0] bign2_dotnamed,
+ output c_dotnamed,
+ output dtmp_NO,
+ output etmp_dotnamed,
+ input \escaped*dot*named
+ );
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-dot-name: t
+// verilog-auto-inst-vector: nil
+// End:
+module autoinst_name_bug245 (
+ );
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input \escaped*dot*named ; // To sub of Sub.v
+ input logic clk; // To sub of Sub.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [2:0] a_NO; // From sub of Sub.v
+ output [1:0] bign2_dotnamed; // From sub of Sub.v
+ output c_dotnamed; // From sub of Sub.v
+ output d_NO; // From sub of Sub.v
+ output etmp_dotnamed; // From sub of Sub.v
+ output [3:0] f4_dotnamed; // From sub of Sub.v
+ // End of automatics
+
+ /*AUTOWIRE*/
+
+ wire [3:0] f4_dotnamed;
+
+ /*Sub AUTO_TEMPLATE (
+ .dtmp_NO (d_NO),
+ .etmp_dotnamed (etmp_dotnamed),
+ );*/
+
+ Sub sub (
+ .bign1_dotnamed,
+ // Outputs
+ .bign2_dotnamed,
+ /*AUTOINST*/
+ // Outputs
+ .a_NO (a_NO[2:0]),
+ .f4_dotnamed,
+ .c_dotnamed,
+ .dtmp_NO (d_NO), // Templated
+ .etmp_dotnamed, // Templated
+ // Inputs
+ .clk,
+ .\escaped*dot*named );
+
+endmodule
+
+module Sub
+ (
+ input logic clk,
+ output [2:0] a_NO,
+ output [3:0] f4_dotnamed,
+ output bign1_dotnamed,
+ output [1:0] bign2_dotnamed,
+ output c_dotnamed,
+ output dtmp_NO,
+ output etmp_dotnamed,
+ input \escaped*dot*named
+ );
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-dot-name: t
+// verilog-auto-inst-vector: nil
+// End:
diff --git a/tests_ok/autoinst_nicholl.v b/tests_ok/autoinst_nicholl.v
new file mode 100644
index 0000000..9b5fcab
--- /dev/null
+++ b/tests_ok/autoinst_nicholl.v
@@ -0,0 +1,58 @@
+module sub1 (/*AUTOARG*/
+ // Inputs
+ bus1
+ );
+
+ input [0:3] bus1;
+
+endmodule
+
+module sub2 (/*AUTOARG*/
+ // Inputs
+ bus2
+ );
+
+ input [0:3] bus2;
+
+endmodule
+
+module sub3 (/*AUTOARG*/
+ // Outputs
+ bus1, bus2
+ );
+
+ output [0:3] bus1;
+ output [4:7] bus2;
+
+endmodule
+
+
+module top (/*AUTOARG*/);
+
+ wire [4:7] bus2; // From sub3 of sub3.v
+
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [0:3] bus1; // From sub3 of sub3.v
+ // End of automatics
+
+ sub1 sub1 (/*AUTOINST*/
+ // Inputs
+ .bus1 (bus1[0:3]));
+
+ sub2 sub2 (/*AUTOINST*/
+ // Inputs
+ .bus2 (bus2[0:3]));
+
+ sub3 sub3 (/*AUTOINST*/
+ // Outputs
+ .bus1 (bus1[0:3]),
+ .bus2 (bus2));
+
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-vector:nil
+// End:
diff --git a/tests_ok/autoinst_overflow_bug250.v b/tests_ok/autoinst_overflow_bug250.v
new file mode 100644
index 0000000..633a0c9
--- /dev/null
+++ b/tests_ok/autoinst_overflow_bug250.v
@@ -0,0 +1,429 @@
+module TEST_TOP (
+ );
+ /*TEST AUTO_TEMPLATE
+ (
+
+ .abcd_efgh_ijklmno_f02_out_c(abcdefg_f02_clroilouull[5]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_be_2(abcdefg_f10_eg2_ab_cdefghijklm[49]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_fh_2(abcdefg_f08_eg0_ab_a_fghi[6]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ch(abcdefg_f09_eg1_ab_cdefghijklm[36]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ej_1(abcdefg_f10_eg2_ab_cdefghijklm[14]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ga_1(abcdefg_f10_eg2_ab_cdefghijklm[3]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_fe(abcdefg_f09_eg1_ab_cdefghijklm[9]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bi_2(abcdefg_f08_eg0_ab_cdefghijklm[45]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_24_1(abcdefg_f09_eg1_ab_fghijklm[24]),
+ .abcd_efgh_ijklmno_f01_oilouull_o_0_1(abcdefg_f01_oilouull[0]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_cc_2(abcdefg_f10_eg2_ab_cdefghijklm[41]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_e_2(abcdefg_f11_eg3_ab_cdefghijklm[59]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_54_1(abcdefg_f11_eg3_ab_fghijklm[54]),
+ .abcd_efgh_ijklmno_f03_oilouull_o_3_1(abcdefg_f03_oilouull[3]),
+ .abcd_efgh_ijklmno_f02_out_h_2(abcdefg_f02_a_zxdf[0]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_g_1(abcdefg_f11_eg3_ab_a_fghi[57]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_b_2(abcdefg_f08_eg0_ab_cdefghijklm[62]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_9_1(abcdefg_f11_eg3_ab_fghijklm[9]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_di_1(abcdefg_f09_eg1_ab_a_fghi[25]),
+ .abcd_efgh_ijklmno_f00_out_h_2(abcdefg_f00_a_zxdf[0]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_cg_2(abcdefg_f11_eg3_ab_cdefghijklm[37]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_eh_2(abcdefg_f10_eg2_ab_a_fghi[16]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_di_1(abcdefg_f08_eg0_ab_cdefghijklm[25]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ec_2(abcdefg_f11_eg3_ab_cdefghijklm[21]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_d_1(abcdefg_f11_eg3_ab_a_fghi[60]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_bh_1(abcdefg_f11_eg3_ab_a_fghi[46]),
+ .abcd_efgh_ijklmno_f00_out_f(abcdefg_f00_clroilouull[2]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_52_1(abcdefg_f11_eg3_ab_fghijklm[52]),
+ .abcd_efgh_ijklmno_f02_out_g(abcdefg_f02_clroilouull[1]),
+ .abcd_efgh_ijklmno_f07_out_e(abcdefg_f07_clroilouull[3]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ff_2(abcdefg_f10_eg2_ab_a_fghi[8]),
+ .abcd_efgh_ijklmno_f04_out_h(abcdefg_f04_clroilouull[0]),
+ .abcd_efgh_ijklmno_f04_out_g_2(abcdefg_f04_a_zxdf[1]),
+ .abcd_efgh_ijklmno_f02_out_c_2(abcdefg_f02_a_zxdf[5]),
+ .abcd_efgh_ijklmno_f04_out_a_3(abcdefg_f04_a_zxdf[7]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_fa_1(abcdefg_f08_eg0_ab_cdefghijklm[13]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_ed_2(abcdefg_f08_eg0_ab_a_fghi[20]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ea_2(abcdefg_f10_eg2_ab_a_fghi[23]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_c_2(abcdefg_f10_eg2_ab_cdefghijklm[61]),
+ .abcd_efgh_ijklmno_f03_oilouull_o_0_1(abcdefg_f03_oilouull[0]),
+ .abcd_efgh_ijklmno_f00_out_e_2(abcdefg_f00_a_zxdf[3]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bg_3(abcdefg_f10_eg2_ab_a_fghi[47]),
+ .abcd_efgh_ijklmno_f05_oilouull_o_2_1(abcdefg_f05_oilouull[2]),
+ .abcd_efgh_ijklmno_f01_out_h_2(abcdefg_f01_a_zxdf[0]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_44_1(abcdefg_f10_eg2_ab_fghijklm[44]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_j_3(abcdefg_f08_eg0_ab_a_fghi[54]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_39_1(abcdefg_f08_eg0_ab_fghijklm[39]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_fj_2(abcdefg_f08_eg0_ab_a_fghi[4]),
+ .abcd_efgh_ijklmno_f05_out_h(abcdefg_f05_clroilouull[0]),
+ .abcd_efgh_ijklmno_f05_out_d_2(abcdefg_f05_a_zxdf[4]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_gb_2(abcdefg_f10_eg2_ab_a_fghi[2]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_cb_3(abcdefg_f10_eg2_ab_a_fghi[42]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_52_1(abcdefg_f10_eg2_ab_fghijklm[52]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_be_2(abcdefg_f11_eg3_ab_cdefghijklm[49]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_42_1(abcdefg_f11_eg3_ab_fghijklm[42]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ci_1(abcdefg_f11_eg3_ab_a_fghi[35]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fh_1(abcdefg_f10_eg2_ab_cdefghijklm[6]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_24_1(abcdefg_f08_eg0_ab_fghijklm[24]),
+ .abcd_efgh_ijklmno_f02_out_g_2(abcdefg_f02_a_zxdf[1]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_d_2(abcdefg_f11_eg3_ab_cdefghijklm[60]),
+ .abcd_efgh_ijklmno_f06_out_d_2(abcdefg_f06_a_zxdf[4]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ea_1(abcdefg_f09_eg1_ab_a_fghi[23]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_dh_2(abcdefg_f11_eg3_ab_cdefghijklm[26]),
+ .abcd_efgh_ijklmno_f04_oilouull_o_7_2(abcdefg_f04_oilouull[7]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_dh_1(abcdefg_f09_eg1_ab_a_fghi[26]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_18_1(abcdefg_f08_eg0_ab_fghijklm[18]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ba_2(abcdefg_f11_eg3_ab_cdefghijklm[53]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ce_1(abcdefg_f11_eg3_ab_a_fghi[39]),
+ .abcd_efgh_ijklmno_f03_oilouull_o_5_1(abcdefg_f03_oilouull[5]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ef_1(abcdefg_f09_eg1_ab_a_fghi[18]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_cj_2(abcdefg_f08_eg0_ab_cdefghijklm[34]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_j_2(abcdefg_f08_eg0_ab_cdefghijklm[54]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bh_3(abcdefg_f08_eg0_ab_a_fghi[46]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_cb_1(abcdefg_f09_eg1_ab_a_fghi[42]),
+ .abcd_efgh_ijklmno_f01_oilouull_o_6_2(abcdefg_f01_oilouull[6]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ba_3(abcdefg_f10_eg2_ab_a_fghi[53]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_0_1(abcdefg_f11_eg3_ab_fghijklm[0]),
+ .abcd_efgh_ijklmno_f06_out_h_2(abcdefg_f06_a_zxdf[0]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_51_1(abcdefg_f08_eg0_ab_fghijklm[51]),
+ .abcd_efgh_ijklmno_f06_oilouull_o_4_1(abcdefg_f06_oilouull[4]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_10_1(abcdefg_f08_eg0_ab_fghijklm[10]),
+ .abcd_efgh_ijklmno_f01_oilouull_o_7_2(abcdefg_f01_oilouull[7]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_da_2(abcdefg_f11_eg3_ab_cdefghijklm[33]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_e_1(abcdefg_f09_eg1_ab_a_fghi[59]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_22_1(abcdefg_f08_eg0_ab_fghijklm[22]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_db_2(abcdefg_f11_eg3_ab_cdefghijklm[32]),
+ .abcd_efgh_ijklmno_f01_oilouull_o_2_1(abcdefg_f01_oilouull[2]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_ci_3(abcdefg_f08_eg0_ab_a_fghi[35]),
+ .abcd_efgh_ijklmno_f07_oilouull_o_6_2(abcdefg_f07_oilouull[6]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_62_1(abcdefg_f11_eg3_ab_fghijklm[62]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_34_1(abcdefg_f10_eg2_ab_fghijklm[34]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_9_1(abcdefg_f10_eg2_ab_fghijklm[9]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_13_1(abcdefg_f10_eg2_ab_fghijklm[13]),
+ .abcd_efgh_ijklmno_f05_oilouull_o_7_2(abcdefg_f05_oilouull[7]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ch_1(abcdefg_f11_eg3_ab_a_fghi[36]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fd_1(abcdefg_f10_eg2_ab_cdefghijklm[10]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fc_2(abcdefg_f10_eg2_ab_a_fghi[11]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ei_1(abcdefg_f09_eg1_ab_a_fghi[15]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_37_1(abcdefg_f08_eg0_ab_fghijklm[37]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_gb(abcdefg_f09_eg1_ab_cdefghijklm[2]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_7_1(abcdefg_f10_eg2_ab_fghijklm[7]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_dg_2(abcdefg_f11_eg3_ab_cdefghijklm[27]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ce(abcdefg_f09_eg1_ab_cdefghijklm[39]),
+ .abcd_efgh_ijklmno_f07_out_d_2(abcdefg_f07_a_zxdf[4]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_cd_2(abcdefg_f08_eg0_ab_cdefghijklm[40]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_57_1(abcdefg_f10_eg2_ab_fghijklm[57]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_63_1(abcdefg_f10_eg2_ab_fghijklm[63]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_j_1(abcdefg_f09_eg1_ab_a_fghi[54]),
+ .abcd_efgh_ijklmno_f00_out_a(abcdefg_f00_clroilouull[7]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_46_1(abcdefg_f09_eg1_ab_fghijklm[46]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_39_1(abcdefg_f10_eg2_ab_fghijklm[39]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_28_1(abcdefg_f08_eg0_ab_fghijklm[28]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_20_1(abcdefg_f08_eg0_ab_fghijklm[20]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_51_1(abcdefg_f11_eg3_ab_fghijklm[51]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ci_1(abcdefg_f09_eg1_ab_a_fghi[35]),
+ .abcd_efgh_ijklmno_f04_out_h_2(abcdefg_f04_a_zxdf[0]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_bd(abcdefg_f09_eg1_ab_cdefghijklm[50]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_dg_1(abcdefg_f10_eg2_ab_cdefghijklm[27]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_23_1(abcdefg_f09_eg1_ab_fghijklm[23]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_1_2(abcdefg_f09_eg1_ab_fghijklm[1]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bc_2(abcdefg_f08_eg0_ab_cdefghijklm[51]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bc_3(abcdefg_f10_eg2_ab_a_fghi[51]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_62_1(abcdefg_f08_eg0_ab_fghijklm[62]),
+ .abcd_efgh_ijklmno_f01_out_g_2(abcdefg_f01_a_zxdf[1]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_23_1(abcdefg_f11_eg3_ab_fghijklm[23]),
+ .abcd_efgh_ijklmno_f03_out_e_2(abcdefg_f03_a_zxdf[3]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_b_1(abcdefg_f09_eg1_ab_a_fghi[62]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_eh(abcdefg_f09_eg1_ab_cdefghijklm[16]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_dh_1(abcdefg_f10_eg2_ab_cdefghijklm[26]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_34_1(abcdefg_f09_eg1_ab_fghijklm[34]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_gc_1(abcdefg_f10_eg2_ab_cdefghijklm[1]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_cg_2(abcdefg_f08_eg0_ab_cdefghijklm[37]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_13_1(abcdefg_f11_eg3_ab_fghijklm[13]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_2_1(abcdefg_f08_eg0_ab_fghijklm[2]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_fb(abcdefg_f09_eg1_ab_cdefghijklm[12]),
+ .abcd_efgh_ijklmno_f00_oilouull_o_6_2(abcdefg_f00_oilouull[6]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_h_3(abcdefg_f08_eg0_ab_a_fghi[56]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_38_1(abcdefg_f09_eg1_ab_fghijklm[38]),
+ .abcd_efgh_ijklmno_f00_out_c(abcdefg_f00_clroilouull[5]),
+ .abcd_efgh_ijklmno_f06_out_a_3(abcdefg_f06_a_zxdf[7]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_60_1(abcdefg_f09_eg1_ab_fghijklm[60]),
+ .abcd_efgh_ijklmno_f06_oilouull_o_2_1(abcdefg_f06_oilouull[2]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_8_1(abcdefg_f09_eg1_ab_fghijklm[8]),
+ .abcd_efgh_ijklmno_f03_out_f(abcdefg_f03_clroilouull[2]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_dj_1(abcdefg_f08_eg0_ab_cdefghijklm[24]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bg_2(abcdefg_f08_eg0_ab_cdefghijklm[47]),
+ .abcd_efgh_ijklmno_f01_oilouull_o_4_1(abcdefg_f01_oilouull[4]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ef_2(abcdefg_f10_eg2_ab_a_fghi[18]),
+ .abcd_efgh_ijklmno_f01_out_a_3(abcdefg_f01_a_zxdf[7]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_12_1(abcdefg_f08_eg0_ab_fghijklm[12]),
+ .abcd_efgh_ijklmno_f07_out_c_2(abcdefg_f07_a_zxdf[5]),
+ .abcd_efgh_ijklmno_f00_out_e(abcdefg_f00_clroilouull[3]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ca_1(abcdefg_f09_eg1_ab_a_fghi[43]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_eg_2(abcdefg_f08_eg0_ab_a_fghi[17]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_be_1(abcdefg_f11_eg3_ab_a_fghi[49]),
+ .abcd_efgh_ijklmno_f06_out_d(abcdefg_f06_clroilouull[4]),
+ .abcd_efgh_ijklmno_f00_out_g(abcdefg_f00_clroilouull[1]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_b(abcdefg_f09_eg1_ab_cdefghijklm[62]),
+ .abcd_efgh_ijklmno_f00_out_f_2(abcdefg_f00_a_zxdf[2]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_gc_1(abcdefg_f09_eg1_ab_a_fghi[1]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ca_1(abcdefg_f11_eg3_ab_a_fghi[43]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ea(abcdefg_f09_eg1_ab_cdefghijklm[23]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_12_1(abcdefg_f10_eg2_ab_fghijklm[12]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_gd_2(abcdefg_f11_eg3_ab_cdefghijklm[0]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_i_1(abcdefg_f09_eg1_ab_a_fghi[55]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_e_2(abcdefg_f08_eg0_ab_cdefghijklm[59]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ff(abcdefg_f09_eg1_ab_cdefghijklm[8]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_17_1(abcdefg_f11_eg3_ab_fghijklm[17]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_be_3(abcdefg_f10_eg2_ab_a_fghi[49]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_20_1(abcdefg_f11_eg3_ab_fghijklm[20]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_bc_1(abcdefg_f11_eg3_ab_a_fghi[51]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_43_1(abcdefg_f09_eg1_ab_fghijklm[43]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_54_1(abcdefg_f09_eg1_ab_fghijklm[54]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_be_2(abcdefg_f08_eg0_ab_cdefghijklm[49]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_36_1(abcdefg_f10_eg2_ab_fghijklm[36]),
+ .abcd_efgh_ijklmno_f05_out_h_2(abcdefg_f05_a_zxdf[0]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_cc(abcdefg_f09_eg1_ab_cdefghijklm[41]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_3_1(abcdefg_f11_eg3_ab_fghijklm[3]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ff_1(abcdefg_f11_eg3_ab_a_fghi[8]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_19_2(abcdefg_f11_eg3_ab_fghijklm[19]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_bi_1(abcdefg_f11_eg3_ab_a_fghi[45]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_49_1(abcdefg_f08_eg0_ab_fghijklm[49]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ee_1(abcdefg_f10_eg2_ab_cdefghijklm[19]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_29_1(abcdefg_f08_eg0_ab_fghijklm[29]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_29_1(abcdefg_f09_eg1_ab_fghijklm[29]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ed(abcdefg_f09_eg1_ab_cdefghijklm[20]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_de(abcdefg_f09_eg1_ab_cdefghijklm[29]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_dg_2(abcdefg_f10_eg2_ab_a_fghi[27]),
+ .abcd_efgh_ijklmno_f04_oilouull_o_2_1(abcdefg_f04_oilouull[2]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_eb_2(abcdefg_f10_eg2_ab_a_fghi[22]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ea_2(abcdefg_f11_eg3_ab_cdefghijklm[23]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fc_1(abcdefg_f10_eg2_ab_cdefghijklm[11]),
+ .abcd_efgh_ijklmno_f06_out_g(abcdefg_f06_clroilouull[1]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_61_1(abcdefg_f09_eg1_ab_fghijklm[61]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ee_2(abcdefg_f10_eg2_ab_a_fghi[19]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_47_1(abcdefg_f11_eg3_ab_fghijklm[47]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_36_1(abcdefg_f08_eg0_ab_fghijklm[36]),
+ .abcd_efgh_ijklmno_f07_oilouull_o_0_1(abcdefg_f07_oilouull[0]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_j_1(abcdefg_f11_eg3_ab_a_fghi[54]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_52_1(abcdefg_f08_eg0_ab_fghijklm[52]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_gd_1(abcdefg_f11_eg3_ab_a_fghi[0]),
+ .abcd_efgh_ijklmno_f07_out_h_2(abcdefg_f07_a_zxdf[0]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_cg_1(abcdefg_f09_eg1_ab_a_fghi[37]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_8_1(abcdefg_f10_eg2_ab_fghijklm[8]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_fh_1(abcdefg_f11_eg3_ab_a_fghi[6]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_52_1(abcdefg_f09_eg1_ab_fghijklm[52]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ci_2(abcdefg_f11_eg3_ab_cdefghijklm[35]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_15_1(abcdefg_f10_eg2_ab_fghijklm[15]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_df(abcdefg_f09_eg1_ab_cdefghijklm[28]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ee(abcdefg_f09_eg1_ab_cdefghijklm[19]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_bd_1(abcdefg_f11_eg3_ab_a_fghi[50]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_fe_1(abcdefg_f11_eg3_ab_a_fghi[9]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_di_2(abcdefg_f08_eg0_ab_a_fghi[25]),
+ .abcd_efgh_ijklmno_f00_out_d(abcdefg_f00_clroilouull[4]),
+ .abcd_efgh_ijklmno_f07_oilouull_o_5_1(abcdefg_f07_oilouull[5]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_41_1(abcdefg_f09_eg1_ab_fghijklm[41]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_cf_2(abcdefg_f08_eg0_ab_cdefghijklm[38]),
+ .abcd_efgh_ijklmno_f05_out_b_3(abcdefg_f05_a_zxdf[6]),
+ .abcd_efgh_ijklmno_f03_oilouull_o_1_1(abcdefg_f03_oilouull[1]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_dg_1(abcdefg_f09_eg1_ab_a_fghi[27]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_eg(abcdefg_f09_eg1_ab_cdefghijklm[17]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ce_1(abcdefg_f09_eg1_ab_a_fghi[39]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_fi_2(abcdefg_f11_eg3_ab_cdefghijklm[5]),
+ .abcd_efgh_ijklmno_f05_out_g(abcdefg_f05_clroilouull[1]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bj_2(abcdefg_f10_eg2_ab_cdefghijklm[44]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_db(abcdefg_f09_eg1_ab_cdefghijklm[32]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_g_1(abcdefg_f09_eg1_ab_a_fghi[57]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bf_2(abcdefg_f08_eg0_ab_cdefghijklm[48]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bh_2(abcdefg_f08_eg0_ab_cdefghijklm[46]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_23_1(abcdefg_f10_eg2_ab_fghijklm[23]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_61_1(abcdefg_f10_eg2_ab_fghijklm[61]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_db_1(abcdefg_f09_eg1_ab_a_fghi[32]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_f(abcdefg_f09_eg1_ab_cdefghijklm[58]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_57_1(abcdefg_f09_eg1_ab_fghijklm[57]),
+ .abcd_efgh_ijklmno_f01_oilouull_o_1_1(abcdefg_f01_oilouull[1]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_eh_2(abcdefg_f08_eg0_ab_a_fghi[16]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_41_1(abcdefg_f11_eg3_ab_fghijklm[41]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_c_2(abcdefg_f08_eg0_ab_cdefghijklm[61]),
+ .abcd_efgh_ijklmno_f06_out_e(abcdefg_f06_clroilouull[3]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ej_1(abcdefg_f11_eg3_ab_a_fghi[14]),
+ .abcd_efgh_ijklmno_f02_oilouull_o_1_1(abcdefg_f02_oilouull[1]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_bd_2(abcdefg_f11_eg3_ab_cdefghijklm[50]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_6_1(abcdefg_f08_eg0_ab_fghijklm[6]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ee_1(abcdefg_f09_eg1_ab_a_fghi[19]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_fc_2(abcdefg_f11_eg3_ab_cdefghijklm[11]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bd_3(abcdefg_f10_eg2_ab_a_fghi[50]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_df_1(abcdefg_f08_eg0_ab_cdefghijklm[28]),
+ .abcd_efgh_ijklmno_f03_out_a(abcdefg_f03_clroilouull[7]),
+ .abcd_efgh_ijklmno_f02_oilouull_o_0_1(abcdefg_f02_oilouull[0]),
+ .abcd_efgh_ijklmno_f00_out_g_2(abcdefg_f00_a_zxdf[1]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_43_1(abcdefg_f08_eg0_ab_fghijklm[43]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_59_1(abcdefg_f08_eg0_ab_fghijklm[59]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ff_1(abcdefg_f09_eg1_ab_a_fghi[8]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bh_2(abcdefg_f10_eg2_ab_cdefghijklm[46]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_0_1(abcdefg_f09_eg1_ab_fghijklm[0]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_ec_2(abcdefg_f08_eg0_ab_a_fghi[21]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_33_1(abcdefg_f09_eg1_ab_fghijklm[33]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_fh_1(abcdefg_f09_eg1_ab_a_fghi[6]),
+ .abcd_efgh_ijklmno_f02_oilouull_o_4_1(abcdefg_f02_oilouull[4]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_31_1(abcdefg_f10_eg2_ab_fghijklm[31]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fa_1(abcdefg_f10_eg2_ab_cdefghijklm[13]),
+ .abcd_efgh_ijklmno_f05_out_f(abcdefg_f05_clroilouull[2]),
+ .abcd_efgh_ijklmno_f04_out_e_2(abcdefg_f04_a_zxdf[3]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_dd_1(abcdefg_f09_eg1_ab_a_fghi[30]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_12_1(abcdefg_f11_eg3_ab_fghijklm[12]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_bf_1(abcdefg_f09_eg1_ab_a_fghi[48]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_23_1(abcdefg_f08_eg0_ab_fghijklm[23]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_dj_2(abcdefg_f08_eg0_ab_a_fghi[24]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ci_3(abcdefg_f10_eg2_ab_a_fghi[35]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_17_1(abcdefg_f08_eg0_ab_fghijklm[17]),
+ .abcd_efgh_ijklmno_f02_out_f_2(abcdefg_f02_a_zxdf[2]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_bb_1(abcdefg_f11_eg3_ab_a_fghi[52]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_cc_1(abcdefg_f11_eg3_ab_a_fghi[41]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_f_1(abcdefg_f11_eg3_ab_a_fghi[58]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_fi(abcdefg_f09_eg1_ab_cdefghijklm[5]),
+ .abcd_efgh_ijklmno_f03_out_h(abcdefg_f03_clroilouull[0]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_e_1(abcdefg_f11_eg3_ab_a_fghi[59]),
+ .abcd_efgh_ijklmno_f01_out_b_3(abcdefg_f01_a_zxdf[6]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_55_1(abcdefg_f08_eg0_ab_fghijklm[55]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bj_3(abcdefg_f10_eg2_ab_a_fghi[44]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_d_2(abcdefg_f08_eg0_ab_cdefghijklm[60]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bi_3(abcdefg_f08_eg0_ab_a_fghi[45]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_fg_1(abcdefg_f09_eg1_ab_a_fghi[7]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ej_2(abcdefg_f10_eg2_ab_a_fghi[14]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_cb_2(abcdefg_f08_eg0_ab_cdefghijklm[42]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fi_1(abcdefg_f10_eg2_ab_cdefghijklm[5]),
+ .abcd_efgh_ijklmno_f01_out_c(abcdefg_f01_clroilouull[5]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_fa_2(abcdefg_f11_eg3_ab_cdefghijklm[13]),
+ .abcd_efgh_ijklmno_f07_out_b_3(abcdefg_f07_a_zxdf[6]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_2_1(abcdefg_f09_eg1_ab_fghijklm[2]),
+ .abcd_efgh_ijklmno_f07_oilouull_o_2_1(abcdefg_f07_oilouull[2]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ed_2(abcdefg_f10_eg2_ab_a_fghi[20]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_32_1(abcdefg_f08_eg0_ab_fghijklm[32]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_29_1(abcdefg_f10_eg2_ab_fghijklm[29]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ef_1(abcdefg_f11_eg3_ab_a_fghi[18]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_15_1(abcdefg_f09_eg1_ab_fghijklm[15]),
+ .abcd_efgh_ijklmno_f04_out_c_2(abcdefg_f04_a_zxdf[5]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_cd(abcdefg_f09_eg1_ab_cdefghijklm[40]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_57_1(abcdefg_f08_eg0_ab_fghijklm[57]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ee_2(abcdefg_f11_eg3_ab_cdefghijklm[19]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_3_1(abcdefg_f09_eg1_ab_fghijklm[3]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_20_1(abcdefg_f10_eg2_ab_fghijklm[20]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_16_1(abcdefg_f08_eg0_ab_fghijklm[16]),
+ .abcd_efgh_ijklmno_f06_oilouull_o_1_1(abcdefg_f06_oilouull[1]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_cg(abcdefg_f09_eg1_ab_cdefghijklm[37]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_cd_3(abcdefg_f10_eg2_ab_a_fghi[40]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_35_1(abcdefg_f10_eg2_ab_fghijklm[35]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_j_3(abcdefg_f10_eg2_ab_a_fghi[54]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_dc_2(abcdefg_f10_eg2_ab_a_fghi[31]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_34_1(abcdefg_f08_eg0_ab_fghijklm[34]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bi_2(abcdefg_f10_eg2_ab_cdefghijklm[45]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_48_1(abcdefg_f09_eg1_ab_fghijklm[48]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_1_2(abcdefg_f10_eg2_ab_fghijklm[1]),
+ .abcd_efgh_ijklmno_f07_out_g(abcdefg_f07_clroilouull[1]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_c_2(abcdefg_f11_eg3_ab_cdefghijklm[61]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_24_1(abcdefg_f10_eg2_ab_fghijklm[24]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fj_2(abcdefg_f10_eg2_ab_a_fghi[4]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_bi_1(abcdefg_f09_eg1_ab_a_fghi[45]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_eb_2(abcdefg_f11_eg3_ab_cdefghijklm[22]),
+ .abcd_efgh_ijklmno_f00_oilouull_o_5_1(abcdefg_f00_oilouull[5]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_30_1(abcdefg_f08_eg0_ab_fghijklm[30]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_11_1(abcdefg_f11_eg3_ab_fghijklm[11]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_26_1(abcdefg_f11_eg3_ab_fghijklm[26]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_45_1(abcdefg_f08_eg0_ab_fghijklm[45]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_dj_1(abcdefg_f10_eg2_ab_cdefghijklm[24]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_gd_1(abcdefg_f10_eg2_ab_cdefghijklm[0]),
+ .abcd_efgh_ijklmno_f05_out_b(abcdefg_f05_clroilouull[6]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_ef_2(abcdefg_f08_eg0_ab_a_fghi[18]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_dg(abcdefg_f09_eg1_ab_cdefghijklm[27]),
+ .abcd_efgh_ijklmno_f02_oilouull_o_6_2(abcdefg_f02_oilouull[6]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_39_1(abcdefg_f11_eg3_ab_fghijklm[39]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_bh_3(abcdefg_f10_eg2_ab_a_fghi[46]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_fc_1(abcdefg_f08_eg0_ab_cdefghijklm[11]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_fa(abcdefg_f09_eg1_ab_cdefghijklm[13]),
+ .abcd_efgh_ijklmno_f04_out_b_3(abcdefg_f04_a_zxdf[6]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_21_1(abcdefg_f08_eg0_ab_fghijklm[21]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_bc_3(abcdefg_f08_eg0_ab_a_fghi[51]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_dd_1(abcdefg_f08_eg0_ab_cdefghijklm[30]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_fc_1(abcdefg_f09_eg1_ab_a_fghi[11]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_22_1(abcdefg_f11_eg3_ab_fghijklm[22]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_14_1(abcdefg_f11_eg3_ab_fghijklm[14]),
+ .abcd_efgh_ijklmno_f02_out_d_2(abcdefg_f02_a_zxdf[4]),
+ .abcd_efgh_ijklmno_f06_out_h(abcdefg_f06_clroilouull[0]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_37_1(abcdefg_f09_eg1_ab_fghijklm[37]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_eh_1(abcdefg_f09_eg1_ab_a_fghi[16]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_12_1(abcdefg_f09_eg1_ab_fghijklm[12]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_cd_1(abcdefg_f09_eg1_ab_a_fghi[40]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_60_1(abcdefg_f11_eg3_ab_fghijklm[60]),
+ .abcd_efgh_ijklmno_f03_out_f_2(abcdefg_f03_a_zxdf[2]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_43_1(abcdefg_f11_eg3_ab_fghijklm[43]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_dc_2(abcdefg_f08_eg0_ab_a_fghi[31]),
+ .abcd_efgh_ijklmno_f07_out_b(abcdefg_f07_clroilouull[6]),
+ .abcd_efgh_ijklmno_f03_out_b_3(abcdefg_f03_a_zxdf[6]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ea_1(abcdefg_f10_eg2_ab_cdefghijklm[23]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_eg_1(abcdefg_f08_eg0_ab_cdefghijklm[17]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_fc_2(abcdefg_f08_eg0_ab_a_fghi[11]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_gc_1(abcdefg_f08_eg0_ab_cdefghijklm[1]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_da(abcdefg_f09_eg1_ab_cdefghijklm[33]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_gb_2(abcdefg_f11_eg3_ab_cdefghijklm[2]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_ba_2(abcdefg_f10_eg2_ab_cdefghijklm[53]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fb_2(abcdefg_f10_eg2_ab_a_fghi[12]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_ee_1(abcdefg_f11_eg3_ab_a_fghi[19]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_32_1(abcdefg_f09_eg1_ab_fghijklm[32]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_gc_2(abcdefg_f11_eg3_ab_cdefghijklm[1]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_ee_1(abcdefg_f08_eg0_ab_cdefghijklm[19]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_36_1(abcdefg_f09_eg1_ab_fghijklm[36]),
+ .abcd_efgh_ijklmno_f02_out_a(abcdefg_f02_clroilouull[7]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_9_1(abcdefg_f08_eg0_ab_fghijklm[9]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_5_1(abcdefg_f09_eg1_ab_fghijklm[5]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_bh_2(abcdefg_f11_eg3_ab_cdefghijklm[46]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_35_1(abcdefg_f09_eg1_ab_fghijklm[35]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ca(abcdefg_f09_eg1_ab_cdefghijklm[43]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_47_1(abcdefg_f08_eg0_ab_fghijklm[47]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_gc_1(abcdefg_f11_eg3_ab_a_fghi[1]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_ba_2(abcdefg_f08_eg0_ab_cdefghijklm[53]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_44_1(abcdefg_f11_eg3_ab_fghijklm[44]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_9_1(abcdefg_f09_eg1_ab_fghijklm[9]),
+ .abcd_efgh_ijklmno_f00_oilouull_o_3_1(abcdefg_f00_oilouull[3]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_fe_2(abcdefg_f11_eg3_ab_cdefghijklm[9]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_ec_1(abcdefg_f09_eg1_ab_a_fghi[21]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_de_2(abcdefg_f10_eg2_ab_a_fghi[29]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_29_1(abcdefg_f11_eg3_ab_fghijklm[29]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_g_3(abcdefg_f08_eg0_ab_a_fghi[57]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fi_2(abcdefg_f10_eg2_ab_a_fghi[5]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_27_1(abcdefg_f08_eg0_ab_fghijklm[27]),
+ .abcd_efgh_ijklmno_f11_eg3_ge_out_fc_1(abcdefg_f11_eg3_ab_a_fghi[11]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_42_1(abcdefg_f10_eg2_ab_fghijklm[42]),
+ .abcd_efgh_ijklmno_f04_oilouull_o_4_1(abcdefg_f04_oilouull[4]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_30_1(abcdefg_f09_eg1_ab_fghijklm[30]),
+ .abcd_efgh_ijklmno_f01_oilouull_o_3_1(abcdefg_f01_oilouull[3]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_fj_1(abcdefg_f10_eg2_ab_cdefghijklm[4]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_55_1(abcdefg_f11_eg3_ab_fghijklm[55]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_42_1(abcdefg_f08_eg0_ab_fghijklm[42]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_gd(abcdefg_f09_eg1_ab_cdefghijklm[0]),
+ .abcd_efgh_ijklmno_f09_eg1_ge_out_eg_1(abcdefg_f09_eg1_ab_a_fghi[17]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_8_1(abcdefg_f08_eg0_ab_fghijklm[8]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_50_1(abcdefg_f11_eg3_ab_fghijklm[50]),
+ .abcd_efgh_ijklmno_f06_out_f_2(abcdefg_f06_a_zxdf[2]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_26_1(abcdefg_f09_eg1_ab_fghijklm[26]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_30_1(abcdefg_f11_eg3_ab_fghijklm[30]),
+ .abcd_efgh_ijklmno_f10_eg2_ab_fghijklm_o_55_1(abcdefg_f10_eg2_ab_fghijklm[55]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_df_2(abcdefg_f08_eg0_ab_a_fghi[28]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_28_1(abcdefg_f09_eg1_ab_fghijklm[28]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_22_1(abcdefg_f09_eg1_ab_fghijklm[22]),
+ .abcd_efgh_ijklmno_f09_eg1_ab_fghijklm_o_45_1(abcdefg_f09_eg1_ab_fghijklm[45]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_46_1(abcdefg_f08_eg0_ab_fghijklm[46]),
+ .abcd_efgh_ijklmno_f01_out_f(abcdefg_f01_clroilouull[2]),
+ .abcd_efgh_ijklmno_f11_eg3_ab_fghijklm_o_36_1(abcdefg_f11_eg3_ab_fghijklm[36]),
+ .abcd_efgh_ijklmno_f05_out_f_2(abcdefg_f05_a_zxdf[2]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_ch_2(abcdefg_f08_eg0_ab_cdefghijklm[36]),
+ .abcd_efgh_ijklmno_f10_eg2_ge_out_cj_3(abcdefg_f10_eg2_ab_a_fghi[34]),
+ .abcd_efgh_ijklmno_f04_oilouull_o_3_1(abcdefg_f04_oilouull[3]),
+ .abcd_efgh_ijklmno_f08_eg0_ge_out_cd_3(abcdefg_f08_eg0_ab_a_fghi[40]),
+ .abcd_efgh_ijklmno_f08_eg0_ab_fghijklm_o_56_1(abcdefg_f08_eg0_ab_fghijklm[56]),
+
+
+ );*/
+ TEST TEST (/*AUTOINST*/);
+
+endmodule
+
+module TEST (/*AUTOARG*/);
+ parameter NO = 6456;
+endmodule
diff --git a/tests_ok/autoinst_param_2d.v b/tests_ok/autoinst_param_2d.v
new file mode 100644
index 0000000..f14be72
--- /dev/null
+++ b/tests_ok/autoinst_param_2d.v
@@ -0,0 +1,101 @@
+// bug981
+
+module a(
+ parameter AUM=80;
+ parameter BUM=70;
+ parameter VUM=1;
+ parameter V2=2;
+ input my_data_z;
+ input my_data_v[VUM];
+ input my_data_vv[VUM][V2];
+ input [AUM-1:0] my_data_av[VUM];
+ input [AUM-1:0][BUM-1:0] my_data_ab;
+ input [AUM-1:0][BUM-1:0] my_data_abv[VUM];
+
+ input [XUM-1:0][YUM-1:0] my_data_xyz[ZUM];
+
+ input PARAMS0__t params0 [1:0];
+ input PARAMS1__t params1 [1:0];
+ );
+endmodule
+
+module top (/*AUTOARG*/
+ // Inputs
+ TEST1_params1, TEST1_params0, TEST1_my_data_z, TEST1_my_data_xyz, TEST1_my_data_vv,
+ TEST1_my_data_v, TEST1_my_data_av, TEST1_my_data_abv, TEST1_my_data_ab, TEST0_params1,
+ TEST0_params0, TEST0_my_data_z, TEST0_my_data_xyz, TEST0_my_data_vv, TEST0_my_data_v,
+ TEST0_my_data_av, TEST0_my_data_abv, TEST0_my_data_ab
+ )
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input [TEST0_AUM-1:0] [TEST0_BUM-1:0] TEST0_my_data_ab;// To a_0 of a.v
+ input [TEST0_AUM-1:0] [TEST0_BUM-1:0] TEST0_my_data_abv [TEST0_VUM];// To a_0 of a.v
+ input [TEST0_AUM-1:0] TEST0_my_data_av [TEST0_VUM];// To a_0 of a.v
+ input TEST0_my_data_v [VUM]; // To a_0 of a.v
+ input TEST0_my_data_vv [VUM][V2];// To a_0 of a.v
+ input [XUM-1:0] [YUM-1:0] TEST0_my_data_xyz [ZUM];// To a_0 of a.v
+ input TEST0_my_data_z; // To a_0 of a.v
+ input PARAMS0__t TEST0_params0 [1:0]; // To a_0 of a.v
+ input PARAMS1__t TEST0_params1 [1:0]; // To a_0 of a.v
+ input [TEST1_AUM-1:0] [TEST1_BUM-1:0] TEST1_my_data_ab;// To a_1 of a.v
+ input [TEST1_AUM-1:0] [TEST1_BUM-1:0] TEST1_my_data_abv [TEST1_VUM];// To a_1 of a.v
+ input [TEST1_AUM-1:0] TEST1_my_data_av [TEST1_VUM];// To a_1 of a.v
+ input TEST1_my_data_v [VUM]; // To a_1 of a.v
+ input TEST1_my_data_vv [VUM][V2];// To a_1 of a.v
+ input [XUM-1:0] [YUM-1:0] TEST1_my_data_xyz [ZUM];// To a_1 of a.v
+ input TEST1_my_data_z; // To a_1 of a.v
+ input PARAMS0__t TEST1_params0 [1:0]; // To a_1 of a.v
+ input PARAMS1__t TEST1_params1 [1:0]; // To a_1 of a.v
+ // End of automatics
+ /*AUTOOUTPUT*/
+ /*AUTOWIRE*/
+
+ /*
+ a AUTO_TEMPLATE
+ (
+ .\(.*\) (TEST@_\1[][]),
+ );
+ */
+ a #(/*AUTOINSTPARAM*/
+ // Parameters
+ .AUM (TEST0_AUM), // Templated
+ .BUM (TEST0_BUM), // Templated
+ .VUM (TEST0_VUM), // Templated
+ .V2 (TEST0_V2)) // Templated
+ a_0 (/*AUTOINST*/
+ // Inputs
+ .my_data_z (TEST0_my_data_z), // Templated
+ .my_data_v (TEST0_my_data_v/*.[VUM]*/), // Templated
+ .my_data_vv (TEST0_my_data_vv/*.[VUM][V2]*/), // Templated
+ .my_data_av (TEST0_my_data_av/*[TEST0_AUM-1:0].[TEST0_VUM]*/), // Templated
+ .my_data_ab (TEST0_my_data_ab/*[TEST0_AUM-1:0][TEST0_BUM-1:0]*/), // Templated
+ .my_data_abv (TEST0_my_data_abv/*[TEST0_AUM-1:0][TEST0_BUM-1:0].[TEST0_VUM]*/), // Templated
+ .my_data_xyz (TEST0_my_data_xyz/*[XUM-1:0][YUM-1:0].[ZUM]*/), // Templated
+ .params0 (TEST0_params0/*.[1:0]*/), // Templated
+ .params1 (TEST0_params1/*.[1:0]*/)); // Templated
+
+
+ a #(/*AUTOINSTPARAM*/
+ // Parameters
+ .AUM (TEST1_AUM), // Templated
+ .BUM (TEST1_BUM), // Templated
+ .VUM (TEST1_VUM), // Templated
+ .V2 (TEST1_V2)) // Templated
+ a_1 (/*AUTOINST*/
+ // Inputs
+ .my_data_z (TEST1_my_data_z), // Templated
+ .my_data_v (TEST1_my_data_v/*.[VUM]*/), // Templated
+ .my_data_vv (TEST1_my_data_vv/*.[VUM][V2]*/), // Templated
+ .my_data_av (TEST1_my_data_av/*[TEST1_AUM-1:0].[TEST1_VUM]*/), // Templated
+ .my_data_ab (TEST1_my_data_ab/*[TEST1_AUM-1:0][TEST1_BUM-1:0]*/), // Templated
+ .my_data_abv (TEST1_my_data_abv/*[TEST1_AUM-1:0][TEST1_BUM-1:0].[TEST1_VUM]*/), // Templated
+ .my_data_xyz (TEST1_my_data_xyz/*[XUM-1:0][YUM-1:0].[ZUM]*/), // Templated
+ .params0 (TEST1_params0/*.[1:0]*/), // Templated
+ .params1 (TEST1_params1/*.[1:0]*/)); // Templated
+
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-param-value:t
+// verilog-typedef-regexp: "_t$"
+// End:
diff --git a/tests_ok/autoinst_param_cmt.v b/tests_ok/autoinst_param_cmt.v
new file mode 100644
index 0000000..041648e
--- /dev/null
+++ b/tests_ok/autoinst_param_cmt.v
@@ -0,0 +1,24 @@
+module InstMod ( ins, outs );
+ output [INWIDTH-1:0] ins;
+endmodule
+
+module test (/*AUTOARG*/) ;
+ parameter foo=1;
+ /*
+ parameter foo=2;
+ */
+
+ //bug647
+
+ /* InstMod AUTO_TEMPLATE
+ (.ins (a@"vh-foo")); */
+
+ InstMod instName (/*AUTOINST*/
+ // Outputs
+ .ins (a1)); // Templated
+
+endmodule
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests_ok/autoinst_param_type.v b/tests_ok/autoinst_param_type.v
new file mode 100644
index 0000000..b12f6ec
--- /dev/null
+++ b/tests_ok/autoinst_param_type.v
@@ -0,0 +1,88 @@
+
+//bug1061
+
+//typedef logic [7:0] foo_t;
+module ptype
+ (
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input foo_t a, // To b0 of ptype_buf.v, ...
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output foo_t y0, // From b0 of ptype_buf.v
+ output logic [7:0] y1, // From b1 of ptype_buf.v
+ output TYPE_T y2 // From b2 of ptype_buf.v
+ // End of automatics
+ );
+
+ ptype_buf #(.TYPE_T(foo_t)) b0
+ (// Outputs
+ .y (y0),
+ /*AUTOINST*/
+ // Inputs
+ .a (a));
+
+ ptype_buf #(.TYPE_T(logic [7:0])) b1
+ (// Outputs
+ .y (y1),
+ /*AUTOINST*/
+ // Inputs
+ .a (a));
+
+ ptype_buf #(.WIDTH(8)) b2
+ (// Outputs
+ .y (y2),
+ /*AUTOINST*/
+ // Inputs
+ .a (a));
+
+endmodule
+
+module ptype_buf
+ #(parameter WIDTH = 1,
+ parameter type TYPE_T = logic [WIDTH-1:0])
+ (output TYPE_T y,
+ input TYPE_T a);
+ assign y = a;
+endmodule
+
+///--------------
+
+// Example in docs
+
+module InstModule (o,i);
+ parameter WIDTH;
+ input [WIDTH-1:0] i;
+ parameter type OUT_t;
+ output OUT_t o;
+endmodule
+
+module ExampInst;
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input [9:0] i; // To instName of InstModule.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output upper_t o; // From instName of InstModule.v
+ // End of automatics
+
+ InstModule
+ #(.WIDTH(10),
+ ,.OUT_t(upper_t))
+ instName
+ (/*AUTOINST*/
+ // Outputs
+ .o (o),
+ // Inputs
+ .i (i[9:0]));
+endmodule
+
+// Local Variables:
+// verilog-typedef-regexp: "_[tT]$"
+// verilog-auto-inst-param-value:t
+// verilog-auto-inst-param-value-type:t
+// End:
diff --git a/tests_ok/autoinst_paramover.v b/tests_ok/autoinst_paramover.v
new file mode 100644
index 0000000..5478d57
--- /dev/null
+++ b/tests_ok/autoinst_paramover.v
@@ -0,0 +1,22 @@
+module autoinst_paramover (/*AUTOARG*/
+ // Inouts
+ a, b
+ );
+
+ //======================================================================
+ // Inputs/Outputs
+ //======================================================================
+
+ parameter bitsa = 20;
+ parameter bitsb = 20;
+
+ inout [20:0] a; // SDRAM Channel 0 Row Address Strobe
+ inout [20:0] b; // SDRAM Channel 0 Row Address Strobe
+
+ autoinst_paramover_sub #(bitsa,bitsb ) mod
+ (/*AUTOINST*/
+ // Inouts
+ .a (a[bitsa:0]),
+ .b (b[bitsb:0]));
+
+endmodule
diff --git a/tests_ok/autoinst_paramover_sub.v b/tests_ok/autoinst_paramover_sub.v
new file mode 100644
index 0000000..fb63124
--- /dev/null
+++ b/tests_ok/autoinst_paramover_sub.v
@@ -0,0 +1,16 @@
+module autoinst_paramover_sub (/*AUTOARG*/
+ // Inouts
+ a, b
+ );
+
+ //======================================================================
+ // Inputs/Outputs
+ //======================================================================
+
+ parameter bitsa;
+ parameter bitsb;
+
+ inout [bitsa:0] a; // SDRAM Channel 0 Row Address Strobe
+ inout [bitsb:0] b; // SDRAM Channel 0 Row Address Strobe
+
+endmodule
diff --git a/tests_ok/autoinst_paramvalue.v b/tests_ok/autoinst_paramvalue.v
new file mode 100644
index 0000000..580dd1b
--- /dev/null
+++ b/tests_ok/autoinst_paramvalue.v
@@ -0,0 +1,68 @@
+module testmuxpv();
+ # (parameter WIDTH = 32)
+ (
+ input wire [2:0] /* synopsys enum cur_info */ sel,
+ input wire [WIDTH-1:0] a,
+ output reg [WIDTH-1:0] out
+ );
+endmodule
+
+module top_test();
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [WIDTH-1:0] out; // From testmuxpv_boo of testmuxpv.v, ..., Couldn't Merge
+ // End of automatics
+
+ //======================================================================
+
+ /* testmuxpv AUTO_TEMPLATE (
+ ) */
+
+ testmuxpv #(.IGNORE((1)),
+ .WIDTH( 16 ),
+ .IGNORE2(2))
+ testmuxpv_boo
+ (/*AUTOINST*/
+ // Outputs
+ .out (out[15:0]),
+ // Inputs
+ .sel (sel[2:0]),
+ .a (a[15:0]));
+
+ //======================================================================
+
+ testmuxpv #(.IGNORE((1)),
+ .WIDTH(WIDTH), // Make sure we don't recurse!
+ .IGNORE2(2))
+ testmuxpv_boo
+ (/*AUTOINST*/
+ // Outputs
+ .out (out[WIDTH-1:0]),
+ // Inputs
+ .sel (sel[2:0]),
+ .a (a[WIDTH-1:0]));
+
+ //======================================================================
+ // bug331: vl-width should correct when param values propagating
+
+ /* testmuxpv AUTO_TEMPLATE (
+ .a ({@"vl-width"{1'b0}}),
+ ) */
+
+ testmuxpv #(.IGNORE((1)),
+ .WIDTH(16),
+ .IGNORE2(2))
+ testmuxpv_boo
+ (/*AUTOINST*/
+ // Outputs
+ .out (out[15:0]),
+ // Inputs
+ .sel (sel[2:0]),
+ .a ({16{1'b0}})); // Templated
+
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-param-value:t
+// End:
diff --git a/tests_ok/autoinst_podolsky.v b/tests_ok/autoinst_podolsky.v
new file mode 100644
index 0000000..09cc18c
--- /dev/null
+++ b/tests_ok/autoinst_podolsky.v
@@ -0,0 +1,21 @@
+module io1_sub(
+ /*AUTOARG*/);
+
+ /* autoinst_lopaz_srpad AUTO_TEMPLATE (
+ .pin_in(),
+ // Inputs
+ .pin_out (),
+ ); */
+
+ autoinst_lopaz_srpad i_ctrl
+ (/*AUTOINST*/
+ // Outputs
+ .pin_in (), // Templated
+ // Inouts
+ .pin (pin[w-1:0]),
+ // Inputs
+ .clk (clk),
+ .pin_out (), // Templated
+ .pin_outen (pin_outen));
+
+endmodule
diff --git a/tests_ok/autoinst_precomment.v b/tests_ok/autoinst_precomment.v
new file mode 100644
index 0000000..52943de
--- /dev/null
+++ b/tests_ok/autoinst_precomment.v
@@ -0,0 +1,40 @@
+module autoinst_precomment (
+ why,
+ /*AUTOARG*/
+ // Inputs
+ nnnot
+ );
+ input why;
+ input nnnot;
+
+ autoinst_wildcard_sub sub0
+ (
+ .sd_ras_ (foobar_ras_),
+ //.sd0_dqm7_l (dontdome),
+ /*AUTOINST*/
+ // Inouts
+ .sd0_dqm7_l (sd0_dqm7_l),
+ .sd0_dqm6_l (sd0_dqm6_l),
+ .sd0_dqm5_l (sd0_dqm5_l),
+ .sd0_dqm4_l (sd0_dqm4_l),
+ .sd0_dqm3_l (sd0_dqm3_l),
+ .sd0_dqm2_l (sd0_dqm2_l),
+ .sd0_dqm1_l (sd0_dqm1_l),
+ .sd0_dqm0_l (sd0_dqm0_l),
+ .sd0_ba1 (sd0_ba1),
+ .sd0_ba0 (sd0_ba0),
+ .sd0_adrs11 (sd0_adrs11),
+ .sd0_adrs10 (sd0_adrs10),
+ .sd0_adrs9 (sd0_adrs9),
+ .sd0_adrs8 (sd0_adrs8),
+ .sd0_adrs7 (sd0_adrs7),
+ .sd0_adrs6 (sd0_adrs6),
+ .sd0_adrs5 (sd0_adrs5),
+ .sd0_adrs4 (sd0_adrs4),
+ .sd0_adrs3 (sd0_adrs3),
+ .sd0_adrs2 (sd0_adrs2),
+ .sd0_adrs1 (sd0_adrs1),
+ .sd0_adrs0 (sd0_adrs0),
+ .sd0_clk (sd0_clk));
+
+endmodule
diff --git a/tests_ok/autoinst_rao.v b/tests_ok/autoinst_rao.v
new file mode 100644
index 0000000..29931c0
--- /dev/null
+++ b/tests_ok/autoinst_rao.v
@@ -0,0 +1,29 @@
+module temp2(/*AUTOARG*/);
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [5:0] out; // From adc_3 of adc.v
+ // End of automatics
+
+ adc adc_3 (
+ // Outputs
+ .out (out[5:0]),
+ // Inputs
+ .Vi (Vi),
+ // Inputs
+ .evalClk (evalClk),
+ /*AUTOINST*/);
+
+endmodule // temp
+
+
+module adc(/*AUTOARG*/
+ // Outputs
+ out,
+ // Inputs
+ Vi, evalClk
+ );
+ output [5:0] out;
+ input Vi;
+ input evalClk;
+endmodule
diff --git a/tests_ok/autoinst_regexp_match.v b/tests_ok/autoinst_regexp_match.v
new file mode 100644
index 0000000..8c1c25c
--- /dev/null
+++ b/tests_ok/autoinst_regexp_match.v
@@ -0,0 +1,89 @@
+module autoinst_wildcard;
+
+ /*AUTOINOUT*/
+ // Beginning of automatic inouts (from unused autoinst inouts)
+ inout [0] [9:0] SD_ADRS; // To/From sub0 of autoinst_wildcard_sub.v, ...
+ inout [0] [1:0] SD_ADRS1; // To/From sub0 of autoinst_wildcard_sub.v, ...
+ inout [0] [1:0] SD_BA; // To/From sub0 of autoinst_wildcard_sub.v, ...
+ inout [0] [7:0] SD_DQM_L; // To/From sub0 of autoinst_wildcard_sub.v, ...
+ inout sd0_clk; // To/From sub0 of autoinst_wildcard_sub.v, ...
+ inout [0] [9:0] sd_adrs; // To/From sub1 of autoinst_wildcard_sub.v, ...
+ inout [0] [1:0] sd_adrs1; // To/From sub1 of autoinst_wildcard_sub.v, ...
+ inout [0] [1:0] sd_ba; // To/From sub1 of autoinst_wildcard_sub.v, ...
+ inout [0] [7:0] sd_dqm_l; // To/From sub1 of autoinst_wildcard_sub.v, ...
+ inout sd_ras_; // To/From sub0 of autoinst_wildcard_sub.v, ...
+ // End of automatics
+
+ /* autoinst_wildcard_sub AUTO_TEMPLATE (
+ .sd\([0-9]\)_\(.*\)\([0-9]+\)\(.*\) (@"(uc \\"sd_\2\4[\1][\3]\\")"),
+ ); */
+
+ /*AUTOOUTPUT*/
+
+ autoinst_wildcard_sub sub0
+ (/*AUTOINST*/
+ // Inouts
+ .sd_ras_ (sd_ras_),
+ .sd0_dqm7_l (SD_DQM_L[0][7]), // Templated
+ .sd0_dqm6_l (SD_DQM_L[0][6]), // Templated
+ .sd0_dqm5_l (SD_DQM_L[0][5]), // Templated
+ .sd0_dqm4_l (SD_DQM_L[0][4]), // Templated
+ .sd0_dqm3_l (SD_DQM_L[0][3]), // Templated
+ .sd0_dqm2_l (SD_DQM_L[0][2]), // Templated
+ .sd0_dqm1_l (SD_DQM_L[0][1]), // Templated
+ .sd0_dqm0_l (SD_DQM_L[0][0]), // Templated
+ .sd0_ba1 (SD_BA[0][1]), // Templated
+ .sd0_ba0 (SD_BA[0][0]), // Templated
+ .sd0_adrs11 (SD_ADRS1[0][1]), // Templated
+ .sd0_adrs10 (SD_ADRS1[0][0]), // Templated
+ .sd0_adrs9 (SD_ADRS[0][9]), // Templated
+ .sd0_adrs8 (SD_ADRS[0][8]), // Templated
+ .sd0_adrs7 (SD_ADRS[0][7]), // Templated
+ .sd0_adrs6 (SD_ADRS[0][6]), // Templated
+ .sd0_adrs5 (SD_ADRS[0][5]), // Templated
+ .sd0_adrs4 (SD_ADRS[0][4]), // Templated
+ .sd0_adrs3 (SD_ADRS[0][3]), // Templated
+ .sd0_adrs2 (SD_ADRS[0][2]), // Templated
+ .sd0_adrs1 (SD_ADRS[0][1]), // Templated
+ .sd0_adrs0 (SD_ADRS[0][0]), // Templated
+ .sd0_clk (sd0_clk));
+
+ /* autoinst_wildcard_sub AUTO_TEMPLATE (
+ .sd\([0-9]\)_\(.*\)\([0-9]+\)\(.*\) (sd_\2\4[\1][\3]),
+ ); */
+
+ /*AUTOOUTPUT*/
+
+ autoinst_wildcard_sub sub1
+ (/*AUTOINST*/
+ // Inouts
+ .sd_ras_ (sd_ras_),
+ .sd0_dqm7_l (sd_dqm_l[0][7]), // Templated
+ .sd0_dqm6_l (sd_dqm_l[0][6]), // Templated
+ .sd0_dqm5_l (sd_dqm_l[0][5]), // Templated
+ .sd0_dqm4_l (sd_dqm_l[0][4]), // Templated
+ .sd0_dqm3_l (sd_dqm_l[0][3]), // Templated
+ .sd0_dqm2_l (sd_dqm_l[0][2]), // Templated
+ .sd0_dqm1_l (sd_dqm_l[0][1]), // Templated
+ .sd0_dqm0_l (sd_dqm_l[0][0]), // Templated
+ .sd0_ba1 (sd_ba[0][1]), // Templated
+ .sd0_ba0 (sd_ba[0][0]), // Templated
+ .sd0_adrs11 (sd_adrs1[0][1]), // Templated
+ .sd0_adrs10 (sd_adrs1[0][0]), // Templated
+ .sd0_adrs9 (sd_adrs[0][9]), // Templated
+ .sd0_adrs8 (sd_adrs[0][8]), // Templated
+ .sd0_adrs7 (sd_adrs[0][7]), // Templated
+ .sd0_adrs6 (sd_adrs[0][6]), // Templated
+ .sd0_adrs5 (sd_adrs[0][5]), // Templated
+ .sd0_adrs4 (sd_adrs[0][4]), // Templated
+ .sd0_adrs3 (sd_adrs[0][3]), // Templated
+ .sd0_adrs2 (sd_adrs[0][2]), // Templated
+ .sd0_adrs1 (sd_adrs[0][1]), // Templated
+ .sd0_adrs0 (sd_adrs[0][0]), // Templated
+ .sd0_clk (sd0_clk));
+
+endmodule
+
+// Local Variables:
+// eval:(defun uc (x) (upcase x))
+// End:
diff --git a/tests_ok/autoinst_rogoff.v b/tests_ok/autoinst_rogoff.v
new file mode 100644
index 0000000..a2a0a5f
--- /dev/null
+++ b/tests_ok/autoinst_rogoff.v
@@ -0,0 +1,77 @@
+module testmux();
+ # (parameter WIDTH = 32)
+ (
+ input wire [2:0] /* synopsys enum cur_info */ sel,
+ input wire [WIDTH-1:0] a,
+ output reg [WIDTH-1:0] out
+ );
+endmodule
+
+module top_test();
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [WIDTH-1:0] boo_out_symbolic; // From testmux_boo of testmux.v
+ wire [WIDTH-1:0] boo_out_value; // From testmux_boo of testmux.v, ...
+ wire [WIDTH-1:0] defaultwidth_out_symbolic;// From testmux_defaultwidth of testmux.v
+ // End of automatics
+
+ /*AUTO_LISP(setq verilog-auto-inst-param-value nil)*/
+
+ /* testmux AUTO_TEMPLATE "testmux_\(.*\)" (
+ .a (@_a_symbolic[]),
+ .out (@_out_symbolic[]),
+ );
+ */
+
+ testmux #(.WIDTH( 16 )) testmux_boo
+ (/*AUTOINST*/
+ // Outputs
+ .out (boo_out_symbolic[WIDTH-1:0]), // Templated
+ // Inputs
+ .sel (sel[2:0]),
+ .a (boo_a_symbolic[WIDTH-1:0])); // Templated
+
+ testmux testmux_defaultwidth
+ (/*AUTOINST*/
+ // Outputs
+ .out (defaultwidth_out_symbolic[WIDTH-1:0]), // Templated
+ // Inputs
+ .sel (sel[2:0]),
+ .a (defaultwidth_a_symbolic[WIDTH-1:0])); // Templated
+
+ //======================================================================
+
+ /*AUTO_LISP(setq verilog-auto-inst-param-value t)*/
+
+ /* testmux AUTO_TEMPLATE "testmux_\(.*\)" (
+ .a (@_a_value[]),
+ .out (@_out_value[]),
+ );
+ */
+
+ testmux #(.IGNORE((1)),
+ .WIDTH( 16 ),
+ .IGNORE2(2))
+ testmux_boo
+ (/*AUTOINST*/
+ // Outputs
+ .out (boo_out_value[15:0]), // Templated
+ // Inputs
+ .sel (sel[2:0]),
+ .a (boo_a_value[15:0])); // Templated
+
+ //======================================================================
+
+ testmux #(.IGNORE((1)),
+ .WIDTH(WIDTH), // Make sure we don't recurse!
+ .IGNORE2(2))
+ testmux_boo
+ (/*AUTOINST*/
+ // Outputs
+ .out (boo_out_value[WIDTH-1:0]), // Templated
+ // Inputs
+ .sel (sel[2:0]),
+ .a (boo_a_value[WIDTH-1:0])); // Templated
+
+endmodule
diff --git a/tests_ok/autoinst_rons.v b/tests_ok/autoinst_rons.v
new file mode 100644
index 0000000..a3ff4d4
--- /dev/null
+++ b/tests_ok/autoinst_rons.v
@@ -0,0 +1,23 @@
+module autoinst_rons;
+ dwrr dwrr_inst (/*AUTOINST*/
+ // Outputs
+ .dwell_count_out (dwell_count_out[6:0]),
+ .eligible_flag (eligible_flag[47:0]),
+ .dwrr_state (dwrr_state[5:0]),
+ // Inputs
+ .data_avail (data_avail[47:0]),
+ .cell_eof (cell_eof[47:0]));
+endmodule
+
+// module declaration
+module dwrr (
+ //Inputs
+ input [47:0] data_avail,
+ input [47:0] cell_eof,
+
+ //Outputs
+ output reg [6:0] dwell_count_out,
+ output reg [47:0] eligible_flag,
+ output [5:0] dwrr_state );
+
+endmodule
diff --git a/tests_ok/autoinst_signed.v b/tests_ok/autoinst_signed.v
new file mode 100644
index 0000000..e49a76f
--- /dev/null
+++ b/tests_ok/autoinst_signed.v
@@ -0,0 +1,43 @@
+module autoinst_signed
+ (/*AUTOARG*/
+ // Outputs
+ another_output2, another_output, an_outputpre, an_output2
+ );
+
+ /*AUTOOUTPUTEVERY*/
+ // Beginning of automatic outputs (every signal)
+ output [1:0] an_output2; // From u_fubar2 of autoinst_signed_fubar2.v
+ output signed [1:0] an_outputpre; // From u_fubar of autoinst_signed_fubar.v
+ output signed [1:0] another_output; // From u_fubar of autoinst_signed_fubar.v
+ output [1:0] another_output2; // From u_fubar2 of autoinst_signed_fubar2.v
+ // End of automatics
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [1:0] an_output2; // From u_fubar2 of autoinst_signed_fubar2.v
+ wire signed [1:0] an_outputpre; // From u_fubar of autoinst_signed_fubar.v
+ wire signed [1:0] another_output; // From u_fubar of autoinst_signed_fubar.v
+ wire [1:0] another_output2; // From u_fubar2 of autoinst_signed_fubar2.v
+ // End of automatics
+
+ autoinst_signed_fubar u_fubar
+ (
+ // Outputs
+ .an_output (an_outputpre[1:0]),
+ .plover (plump),
+ /*AUTOINST*/
+ // Outputs
+ .another_output (another_output[1:0]),
+ // Inputs
+ .an_input (an_input[1:0]));
+
+ autoinst_signed_fubar2 u_fubar2
+ (
+ /*AUTOINST*/
+ // Outputs
+ .an_output2 (an_output2[1:0]),
+ .another_output2 (another_output2[1:0]),
+ // Inputs
+ .an_input2 (an_input2[1:0]));
+
+endmodule
diff --git a/tests_ok/autoinst_signed_fubar.v b/tests_ok/autoinst_signed_fubar.v
new file mode 100644
index 0000000..3382b16
--- /dev/null
+++ b/tests_ok/autoinst_signed_fubar.v
@@ -0,0 +1,15 @@
+
+module autoinst_signed_fubar
+ (
+ input signed [1:0] an_input,
+ output signed [1:0] an_output
+ output signed [1:0] another_output
+ );
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg signed [1:0] an_output;
+ reg signed [1:0] another_output;
+ // End of automatics
+
+endmodule
diff --git a/tests_ok/autoinst_signed_fubar2.v b/tests_ok/autoinst_signed_fubar2.v
new file mode 100644
index 0000000..a0cd115
--- /dev/null
+++ b/tests_ok/autoinst_signed_fubar2.v
@@ -0,0 +1,15 @@
+
+module autoinst_signed_fubar2
+ (
+ input [1:0] an_input2,
+ output [1:0] an_output2
+ output [1:0] another_output2
+ );
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg [1:0] an_output2;
+ reg [1:0] another_output2;
+ // End of automatics
+
+endmodule
diff --git a/tests_ok/autoinst_star.v b/tests_ok/autoinst_star.v
new file mode 100644
index 0000000..2cb5423
--- /dev/null
+++ b/tests_ok/autoinst_star.v
@@ -0,0 +1,46 @@
+module io1_sub (/*AUTOARG*/);
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [w-1:0] pin; // To/From MD31_pad of autoinst_lopaz_srpad.v
+ wire [2*w-1:0] pin_in; // From MD31_pad of autoinst_lopaz_srpad.v, ...
+ wire templated; // To/From MD31_pad of autoinst_lopaz_srpad.v
+ // End of automatics
+
+ autoinst_lopaz_srpad MD31_pad
+ (.*,
+ .foo (touch_this_not_my_pretty));
+
+ /* autoinst_lopaz_srpad AUTO_TEMPLATE (
+ ); */
+
+ autoinst_lopaz_srpad MD31_pad
+ (.*);
+
+ /* autoinst_lopaz_srpad AUTO_TEMPLATE (
+ .pin (templated));
+ */
+
+ autoinst_lopaz_srpad MD31_pad
+ (.*,
+ // Outputs
+ // Inouts
+ .pin (templated) // Templated
+ );
+
+ // And .name with auto inst
+ autoinst_lopaz_srpad MD31_pad22
+ (.pin,
+ .clk,
+ /*AUTOINST*/
+ // Outputs
+ .pin_in (pin_in[2*w-1:0]),
+ // Inputs
+ .pin_out (pin_out[w-1:0]),
+ .pin_outen (pin_outen));
+
+ always @(posedge clk) begin
+ $display ("This .* shouldn't expand.\n");
+ end
+
+endmodule
diff --git a/tests_ok/autoinst_sv_kulkarni.v b/tests_ok/autoinst_sv_kulkarni.v
new file mode 100644
index 0000000..c0211b7
--- /dev/null
+++ b/tests_ok/autoinst_sv_kulkarni.v
@@ -0,0 +1,81 @@
+`timescale 1ns/100ps
+
+// -----------------------------------------------------------------------------
+// One-level up Hierarchical module
+// -----------------------------------------------------------------------------
+module a_h
+ // Verilog 2001 style
+ #(parameter M=5, N=3)
+ (
+ // Outputs
+ output [N-1:0] [M-1:0] a_o1 // From Ia of autoinst_sv_kulkarni_base.v
+ // End of automatics
+ // AUTOINPUT*/
+ );
+
+ /*AUTOWIRE*/
+
+ autoinst_sv_kulkarni_base
+ #(/*AUTOINSTPARAM*/
+ // Parameters
+ .M (M),
+ .N (N))
+ Ia
+ (/*AUTOINST*/
+ // Outputs
+ .a_o1 (a_o1/*[N-1:0][M-1:0]*/),
+ // Inputs
+ .a_i1 (a_i1/*[N-1:0][M-1:0]*/)); // <---- BUG?
+
+endmodule
+
+// -----------------------------------------------------------------------------
+// Top-level module or Testbench
+// -----------------------------------------------------------------------------
+module top;
+ parameter M=4;
+ parameter N=2;
+
+ wire [N-1:0] a_o1;
+ logic [N-1:0][M-1:0] a_i1;
+
+ logic temp;
+
+ /*AUTOWIRE*/
+
+ // Workaround to fix multi-dimensional port problem
+ // a) Set "verilog-auto-inst-vector = nil"
+ // b) ----> a_h AUTO_TEMPLATE ( .\(.*\) (\1), ); */
+
+ a_h #(/*AUTOINSTPARAM*/
+ // Parameters
+ .M (M),
+ .N (N))
+ Ua_h
+ (/*AUTOINST*/
+ // Outputs
+ .a_o1 (a_o1/*[N-1:0][M-1:0]*/)); // <---- BUG?
+
+ // Stimulus
+ initial begin
+ a_i1 = { 4'h0, 4'h2 };
+ #5;
+ $display("Loop Init: a_i1 = { %h, %h } a_o1 = %h\n",
+ a_i1[1], a_i1[0], a_o1);
+ #5;
+ for (int i=0; i<1; i++) begin
+ for (int j=0; j<N; j++) begin
+ temp = 1'b0;
+ for (int k=0; k<M; k++) begin
+ a_i1[j][k] = temp;
+ temp = ~temp;
+ end
+ end
+ #5;
+ $display("Loop %0d: a_i1 = { %h, %h } a_o1 = %h\n",
+ i, a_i1[1], a_i1[0], a_o1);
+ #5;
+ end
+ end
+
+endmodule
diff --git a/tests_ok/autoinst_sv_kulkarni_base.v b/tests_ok/autoinst_sv_kulkarni_base.v
new file mode 100644
index 0000000..a456035
--- /dev/null
+++ b/tests_ok/autoinst_sv_kulkarni_base.v
@@ -0,0 +1,21 @@
+`timescale 1ns/100ps
+
+// -----------------------------------------------------------------------------
+// Leaf module using multi-dimensional array ports
+// -----------------------------------------------------------------------------
+module autoinst_sv_kulkarni_base
+ // Verilog 2001 style
+ #(parameter M=5, N=3)
+ (
+ output logic [N-1:0][M-1:0] a_o1,
+ input [N-1:0][M-1:0] a_i1
+ );
+
+ // -----------------------------------------------------------------------------
+ // Main Code
+ always_comb begin
+ for (int i=0; i<N; i++)
+ a_o1[i] = ^(a_i1[i]);
+ end
+
+endmodule
diff --git a/tests_ok/autoinst_sv_kulkarni_wire.v b/tests_ok/autoinst_sv_kulkarni_wire.v
new file mode 100644
index 0000000..9aa17ff
--- /dev/null
+++ b/tests_ok/autoinst_sv_kulkarni_wire.v
@@ -0,0 +1,24 @@
+`timescale 1ns/100ps
+
+module a_h
+ #(parameter M=5, N=3)
+ ();
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic [N-1:0] [M-1:0] a_o1; // From Ia of autoinst_sv_kulkarni_base.v
+ // End of automatics
+
+ autoinst_sv_kulkarni_base
+ #(/*AUTOINSTPARAM*/
+ // Parameters
+ .M (M),
+ .N (N))
+ Ia
+ (/*AUTOINST*/
+ // Outputs
+ .a_o1 (a_o1/*[N-1:0][M-1:0]*/),
+ // Inputs
+ .a_i1 (a_i1/*[N-1:0][M-1:0]*/)); // <---- BUG?
+
+endmodule
diff --git a/tests_ok/autoinst_sv_shaw.v b/tests_ok/autoinst_sv_shaw.v
new file mode 100644
index 0000000..897c9e5
--- /dev/null
+++ b/tests_ok/autoinst_sv_shaw.v
@@ -0,0 +1,23 @@
+module autoinst_sv_shaw
+ (
+ /*AUTOINOUTMODULE("Example_mod")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ input logic clk,
+ input logic reset_b
+ // End of automatics
+ );
+
+ Example_mod Ex1 (/*AUTOINST*/
+ // Inputs
+ .clk (clk),
+ .reset_b (reset_b));
+
+endmodule
+
+module Example_mod
+ (
+ input logic clk,
+ input logic reset_b,
+ );
+endmodule
+
diff --git a/tests_ok/autoinst_template_lint.v b/tests_ok/autoinst_template_lint.v
new file mode 100644
index 0000000..f079c3b
--- /dev/null
+++ b/tests_ok/autoinst_template_lint.v
@@ -0,0 +1,55 @@
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2011 by Wilson Snyder.
+
+// Reported by Julian Gorfajn <jig1@cornell.edu>
+
+module autoinst_multitemplate ();
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input Boo2; // To suba2 of SubB.v
+ input Boo3; // To suba3 of SubB.v
+ input a; // To suba2 of SubB.v
+ input b; // To suba3 of SubB.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+
+ /*AUTOWIRE*/
+
+ wire [3:0] f4_dotnamed;
+
+ /*
+ SubB AUTO_TEMPLATE (
+ .b (Boo@),
+ );*/
+
+ SubB suba2 (/*AUTOINST*/
+ // Inputs
+ .a (a),
+ .b (Boo2)); // Templated
+
+ /*
+ SubB AUTO_TEMPLATE (
+ .a (Boo@),
+ );*/
+
+ SubB suba3 (/*AUTOINST*/
+ // Inputs
+ .a (Boo3), // Templated
+ .b (b));
+
+ // Test harness doesn't support expected errors
+ // /*
+ // SubUnused AUTO_TEMPLATE (
+ // .subunused (Boo@),
+ // );*/
+
+endmodule
+
+module SubB (input a,input b);
+endmodule
+
+// Local Variables:
+// verilog-auto-template-warn-unused: t
+// End:
diff --git a/tests_ok/autoinst_tennant.v b/tests_ok/autoinst_tennant.v
new file mode 100644
index 0000000..af66127
--- /dev/null
+++ b/tests_ok/autoinst_tennant.v
@@ -0,0 +1,109 @@
+typedef logic [3:0][1:0] sometype_t;
+
+module top
+ #(parameter X=4,
+ parameter Y=1)
+
+ (input clk,
+ input rstb,
+
+ /*AUTOINPUT("^x.*\|v.*")*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input [X-1:0] xb, // To XX of xx.v, ...
+ // End of automatics
+ /*AUTOOUTPUT("^c.*\|k.*")*/
+
+ /*AUTOOUTPUT("^y.*")*/
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input [X-1:0] cb, // To XX of xx.v, ...
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output foobar, // From XX of xx.v
+ output [4:0] [2:0] foobar2 // From YY of yy.v
+ // End of automatics
+ );
+
+ xx (/*AUTOINSTPARAM*/
+ // Parameters
+ .X (X),
+ .Y (Y))
+ XX(/*AUTOINST*/
+ // Outputs
+ .st (st[1:0]),
+ .foobar (foobar),
+ // Inputs
+ .clk (clk),
+ .rstb (rstb),
+ .xc (xc/*[X-1:0][1:0]*/),
+ .xa (xa[X-1:0]),
+ .xb (xb[X-1:0]),
+ .cb (cb[X-1:0]),
+ .yb (yb[X*Y-1:0]));
+
+ yy (/*AUTOINSTPARAM*/
+ // Parameters
+ .X (X),
+ .Y (Y))
+ YY(/*AUTOINST*/
+ // Outputs
+ .xc (xc/*[X-1:0][1:0]*/),
+ .xa (xa[X-1:0]),
+ .yb (yb[X*Y-1:0]),
+ .foobar2 (foobar2/*[4:0][2:0]*/),
+ // Inputs
+ .clk (clk),
+ .rstb (rstb),
+ .xb (xb[X-1:0]),
+ .cb (cb[X-1:0]),
+ .st (st[1:0]));
+
+endmodule // top
+
+module xx
+ #(parameter X=4,
+ parameter Y=1)
+ (input clk,
+ input rstb,
+
+ input [X-1:0][1:0] xc,
+ input [X-1:0] xa,
+ input [X-1:0] xb,
+
+ input [X-1:0] cb,
+ output sometype_t [1:0] st,
+
+ input [X*Y-1:0] yb,
+
+ output foobar
+ );
+
+endmodule // xx
+
+module yy
+ #(parameter X=4,
+ parameter Y=1)
+ (input clk,
+ input rstb,
+
+ output [X-1:0][1:0] xc,
+ output [X-1:0] xa,
+ input [X-1:0] xb,
+
+ input [X-1:0] cb,
+ input sometype_t [1:0] st,
+
+ output [X*Y-1:0] yb,
+
+ output [4:0][2:0] foobar2
+ );
+
+endmodule // xx
+
+// Local Variables:
+// verilog-typedef-regexp:"_t$"
+// verilog-library-directories:("." )
+// verilog-library-extensions:(".v" ".sv" ".h" ".vr" ".vm")
+// End:
diff --git a/tests_ok/autoinst_unsigned_bug302.v b/tests_ok/autoinst_unsigned_bug302.v
new file mode 100644
index 0000000..53886bf
--- /dev/null
+++ b/tests_ok/autoinst_unsigned_bug302.v
@@ -0,0 +1,30 @@
+module autoinst_unsigned_bug302;
+
+ Sub #(/*AUTOINSTPARAM*/
+ // Parameters
+ .No1 (No1),
+ .No2 (No2),
+ .No3 (No3/*.[No1:0][No2-1:0]*/)) u_Abc
+ (/*AUTOINST*/
+ // Inputs
+ .ck (ck),
+ .abc (abc/*[No1-1:0][31:0]*/));
+
+endmodule
+
+module Sub
+ #(
+ parameter No1 = 6,
+ parameter int unsigned No2 // Parameter no. 2
+ = pa_Abc::No2,
+ parameter bit No3 [No1:0][No2-1:0] // Parameter no. 3
+ = pa_Abc::No3
+ )
+
+ (
+ input logic ck,
+ input logic [No1-1:0][31:0] abc
+ input logic [No1-1:0][31:0] abc
+ );
+
+endmodule
diff --git a/tests_ok/autoinst_vertrees.v b/tests_ok/autoinst_vertrees.v
new file mode 100644
index 0000000..15b3e42
--- /dev/null
+++ b/tests_ok/autoinst_vertrees.v
@@ -0,0 +1,126 @@
+module autoinst_vertrees
+ (/*AUTOARG*/
+ // Outputs
+ slv_b_put, slv_b_bit_st, slv_a_put, slv_a_bit_st, i2c_b_strobe, i2c_b_start, i2c_b_spc_stop,
+ i2c_b_spc_start, i2c_b_spc_sda_state, i2c_b_spc_scl_state, i2c_b_spc_scl_fall, i2c_b_slv_sda_out,
+ i2c_b_slv_scl_out, i2c_b_read, i2c_b_mst_data, i2c_a_strobe, i2c_a_start, i2c_a_spc_stop,
+ i2c_a_spc_start, i2c_a_spc_sda_state, i2c_a_spc_scl_state, i2c_a_spc_scl_fall, i2c_a_slv_sda_out,
+ i2c_a_slv_scl_out, i2c_a_read, i2c_a_mst_data,
+ // Inputs
+ test_mode, rst_ref, rpt_b_sda, rpt_b_hold, rpt_a_sda, rpt_a_hold, r_i2c_spc_scl_low,
+ i2c_b_slv_sda_in, i2c_b_slv_scl_in, i2c_b_slv_data, i2c_a_slv_sda_in, i2c_a_slv_scl_in,
+ i2c_a_slv_data, ck_ref
+ );
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input ck_ref; // To u_slv_a of autoinst_vertrees_slv.v, ...
+ input i2c_a_slv_data; // To u_slv_a of autoinst_vertrees_slv.v
+ input i2c_a_slv_scl_in; // To u_slv_a of autoinst_vertrees_slv.v
+ input i2c_a_slv_sda_in; // To u_slv_a of autoinst_vertrees_slv.v
+ input i2c_b_slv_data; // To u_slv_b of autoinst_vertrees_slv.v
+ input i2c_b_slv_scl_in; // To u_slv_b of autoinst_vertrees_slv.v
+ input i2c_b_slv_sda_in; // To u_slv_b of autoinst_vertrees_slv.v
+ input [4:0] r_i2c_spc_scl_low; // To u_slv_a of autoinst_vertrees_slv.v, ...
+ input rpt_a_hold; // To u_slv_a of autoinst_vertrees_slv.v
+ input rpt_a_sda; // To u_slv_a of autoinst_vertrees_slv.v
+ input rpt_b_hold; // To u_slv_b of autoinst_vertrees_slv.v
+ input rpt_b_sda; // To u_slv_b of autoinst_vertrees_slv.v
+ input rst_ref; // To u_slv_a of autoinst_vertrees_slv.v, ...
+ input test_mode; // To u_slv_a of autoinst_vertrees_slv.v, ...
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output i2c_a_mst_data; // From u_slv_a of autoinst_vertrees_slv.v
+ output i2c_a_read; // From u_slv_a of autoinst_vertrees_slv.v
+ output i2c_a_slv_scl_out; // From u_slv_a of autoinst_vertrees_slv.v
+ output i2c_a_slv_sda_out; // From u_slv_a of autoinst_vertrees_slv.v
+ output i2c_a_spc_scl_fall; // From u_slv_a of autoinst_vertrees_slv.v
+ output i2c_a_spc_scl_state; // From u_slv_a of autoinst_vertrees_slv.v
+ output i2c_a_spc_sda_state; // From u_slv_a of autoinst_vertrees_slv.v
+ output i2c_a_spc_start; // From u_slv_a of autoinst_vertrees_slv.v
+ output i2c_a_spc_stop; // From u_slv_a of autoinst_vertrees_slv.v
+ output i2c_a_start; // From u_slv_a of autoinst_vertrees_slv.v
+ output i2c_a_strobe; // From u_slv_a of autoinst_vertrees_slv.v
+ output i2c_b_mst_data; // From u_slv_b of autoinst_vertrees_slv.v
+ output i2c_b_read; // From u_slv_b of autoinst_vertrees_slv.v
+ output i2c_b_slv_scl_out; // From u_slv_b of autoinst_vertrees_slv.v
+ output i2c_b_slv_sda_out; // From u_slv_b of autoinst_vertrees_slv.v
+ output i2c_b_spc_scl_fall; // From u_slv_b of autoinst_vertrees_slv.v
+ output i2c_b_spc_scl_state; // From u_slv_b of autoinst_vertrees_slv.v
+ output i2c_b_spc_sda_state; // From u_slv_b of autoinst_vertrees_slv.v
+ output i2c_b_spc_start; // From u_slv_b of autoinst_vertrees_slv.v
+ output i2c_b_spc_stop; // From u_slv_b of autoinst_vertrees_slv.v
+ output i2c_b_start; // From u_slv_b of autoinst_vertrees_slv.v
+ output i2c_b_strobe; // From u_slv_b of autoinst_vertrees_slv.v
+ output slv_a_bit_st; // From u_slv_a of autoinst_vertrees_slv.v
+ output slv_a_put; // From u_slv_a of autoinst_vertrees_slv.v
+ output slv_b_bit_st; // From u_slv_b of autoinst_vertrees_slv.v
+ output slv_b_put; // From u_slv_b of autoinst_vertrees_slv.v
+ // End of automatics
+
+ /*AUTOWIRE*/
+
+ /*
+ autoinst_vertrees_slv AUTO_TEMPLATE "u_slv_\([a-z]\)"
+ (.i2c_\(.*\) (i2c_@_\1),
+ .slv_\(.*\) (slv_@_\1),
+ .rpt_\(.*\) (rpt_@_\1),
+ )
+ */
+ autoinst_vertrees_slv u_slv_a
+ (/*AUTOINST*/
+ // Outputs
+ .i2c_mst_data (i2c_a_mst_data), // Templated
+ .i2c_read (i2c_a_read), // Templated
+ .i2c_slv_scl_out (i2c_a_slv_scl_out), // Templated
+ .i2c_slv_sda_out (i2c_a_slv_sda_out), // Templated
+ .i2c_spc_scl_state (i2c_a_spc_scl_state), // Templated
+ .i2c_start (i2c_a_start), // Templated
+ .i2c_strobe (i2c_a_strobe), // Templated
+ .slv_bit_st (slv_a_bit_st), // Templated
+ .slv_put (slv_a_put), // Templated
+ .i2c_spc_scl_fall (i2c_a_spc_scl_fall), // Templated
+ .i2c_spc_sda_state (i2c_a_spc_sda_state), // Templated
+ .i2c_spc_start (i2c_a_spc_start), // Templated
+ .i2c_spc_stop (i2c_a_spc_stop), // Templated
+ // Inputs
+ .ck_ref (ck_ref),
+ .i2c_slv_data (i2c_a_slv_data), // Templated
+ .i2c_slv_scl_in (i2c_a_slv_scl_in), // Templated
+ .i2c_slv_sda_in (i2c_a_slv_sda_in), // Templated
+ .r_i2c_spc_scl_low (r_i2c_spc_scl_low[4:0]),
+ .rpt_hold (rpt_a_hold), // Templated
+ .rpt_sda (rpt_a_sda), // Templated
+ .rst_ref (rst_ref),
+ .test_mode (test_mode));
+
+ autoinst_vertrees_slv u_slv_b
+ (/*AUTOINST*/
+ // Outputs
+ .i2c_mst_data (i2c_b_mst_data), // Templated
+ .i2c_read (i2c_b_read), // Templated
+ .i2c_slv_scl_out (i2c_b_slv_scl_out), // Templated
+ .i2c_slv_sda_out (i2c_b_slv_sda_out), // Templated
+ .i2c_spc_scl_state (i2c_b_spc_scl_state), // Templated
+ .i2c_start (i2c_b_start), // Templated
+ .i2c_strobe (i2c_b_strobe), // Templated
+ .slv_bit_st (slv_b_bit_st), // Templated
+ .slv_put (slv_b_put), // Templated
+ .i2c_spc_scl_fall (i2c_b_spc_scl_fall), // Templated
+ .i2c_spc_sda_state (i2c_b_spc_sda_state), // Templated
+ .i2c_spc_start (i2c_b_spc_start), // Templated
+ .i2c_spc_stop (i2c_b_spc_stop), // Templated
+ // Inputs
+ .ck_ref (ck_ref),
+ .i2c_slv_data (i2c_b_slv_data), // Templated
+ .i2c_slv_scl_in (i2c_b_slv_scl_in), // Templated
+ .i2c_slv_sda_in (i2c_b_slv_sda_in), // Templated
+ .r_i2c_spc_scl_low (r_i2c_spc_scl_low[4:0]),
+ .rpt_hold (rpt_b_hold), // Templated
+ .rpt_sda (rpt_b_sda), // Templated
+ .rst_ref (rst_ref),
+ .test_mode (test_mode));
+
+endmodule // ddc
diff --git a/tests_ok/autoinst_vertrees_slv.v b/tests_ok/autoinst_vertrees_slv.v
new file mode 100644
index 0000000..7a857c2
--- /dev/null
+++ b/tests_ok/autoinst_vertrees_slv.v
@@ -0,0 +1,37 @@
+
+module autoinst_vertrees_slv
+ (/*AUTOARG*/
+ // Outputs
+ i2c_mst_data, i2c_read, i2c_slv_scl_out, i2c_slv_sda_out, i2c_spc_scl_state, i2c_start,
+ i2c_strobe, slv_bit_st, slv_put, i2c_spc_scl_fall, i2c_spc_sda_state, i2c_spc_start,
+ i2c_spc_stop,
+ // Inputs
+ ck_ref, i2c_slv_data, i2c_slv_scl_in, i2c_slv_sda_in, r_i2c_spc_scl_low, rpt_hold, rpt_sda,
+ rst_ref, test_mode
+ );
+
+ input ck_ref; // To u_spc of i2c_slv_pin_ctrl.v, ...
+ input [7:0] i2c_slv_data; // To u_misc of ddc_slv_misc.v
+ input i2c_slv_scl_in; // To u_spc of i2c_slv_pin_ctrl.v
+ input i2c_slv_sda_in; // To u_spc of i2c_slv_pin_ctrl.v
+ input [4:0] r_i2c_spc_scl_low; // To u_spc of i2c_slv_pin_ctrl.v
+ input rpt_hold; // To u_misc of ddc_slv_misc.v
+ input rpt_sda; // To u_misc of ddc_slv_misc.v
+ input rst_ref; // To u_spc of i2c_slv_pin_ctrl.v, ...
+ input test_mode; // To u_spc of i2c_slv_pin_ctrl.v
+
+ output [7:0] i2c_mst_data; // From u_misc of ddc_slv_misc.v
+ output i2c_read; // From u_misc of ddc_slv_misc.v
+ output i2c_slv_scl_out; // From u_spc of i2c_slv_pin_ctrl.v
+ output i2c_slv_sda_out; // From u_spc of i2c_slv_pin_ctrl.v
+ output i2c_spc_scl_state; // From u_spc of i2c_slv_pin_ctrl.v
+ output i2c_start; // From u_misc of ddc_slv_misc.v
+ output i2c_strobe; // From u_misc of ddc_slv_misc.v
+ output slv_bit_st; // From u_misc of ddc_slv_misc.v
+ output slv_put; // From u_misc of ddc_slv_misc.v
+ output i2c_spc_scl_fall; // From u_spc of i2c_slv_pin_ctrl.v
+ output i2c_spc_sda_state; // From u_spc of i2c_slv_pin_ctrl.v
+ output i2c_spc_start; // From u_spc of i2c_slv_pin_ctrl.v
+ output i2c_spc_stop; // From u_spc of i2c_slv_pin_ctrl.v
+
+endmodule // ddc_slv
diff --git a/tests_ok/autoinst_vkadamby.v b/tests_ok/autoinst_vkadamby.v
new file mode 100644
index 0000000..f652a55
--- /dev/null
+++ b/tests_ok/autoinst_vkadamby.v
@@ -0,0 +1,18 @@
+module autoinst_vkadamby ( /*AUTOARG*/);
+
+ child1 #(.lengthM2(100)) I34 (/*AUTOINST*/
+ // Inputs
+ .x (x));
+
+endmodule
+
+module child1 (/*AUTOARG*/
+ // Inputs
+ x
+ );
+
+ input x;
+ parameter lengthM2;
+
+endmodule
+
diff --git a/tests_ok/autoinst_width.v b/tests_ok/autoinst_width.v
new file mode 100644
index 0000000..736948e
--- /dev/null
+++ b/tests_ok/autoinst_width.v
@@ -0,0 +1,32 @@
+module ex;
+
+ /* subwidth AUTO_TEMPLATE (
+ .bus1a(@"vl-width"'b0),
+ .bus1b(@"vl-width"'b0),
+ .bus4a(@"vl-width"'b0),
+ .bus4b(@"vl-width"'b0),
+ .busdef(@"vl-width"'b0),
+ );*/
+
+ subwidth u_a2(/*AUTOINST*/
+ // Outputs
+ .bus4a (4'b0), // Templated
+ .bus4b (4'b0), // Templated
+ .bus1a (1'b0), // Templated
+ .bus1b (1'b0), // Templated
+ .busdef ((1+(`defa)-(`defb))'b0)); // Templated
+
+endmodule
+
+module subwidth (/*AUTOARG*/
+ // Outputs
+ bus4a, bus4b, bus1a, bus1b, busdef
+ );
+
+ output [0:3] bus4a;
+ output [7:4] bus4b;
+ output bus1a;
+ output [0:0] bus1b;
+ output [`defa:`defb] busdef;
+
+endmodule
diff --git a/tests_ok/autoinst_wildcard.v b/tests_ok/autoinst_wildcard.v
new file mode 100644
index 0000000..3832a1c
--- /dev/null
+++ b/tests_ok/autoinst_wildcard.v
@@ -0,0 +1,49 @@
+module autoinst_wildcard;
+
+ /*AUTOOUTPUT*/
+
+ // Newline between AUTO_TEMPLATE and ( gave a templated line number bug
+ /* autoinst_wildcard_sub AUTO_TEMPLATE
+ (
+ .sd0_clk (sd_clk),
+ .sd0_dqm\(.*\)_l (c@_sd_dqm_[\1]),
+ .sd0_ba\([0-9]+\) (c@_sd_ba[\1]),
+ .sd0_adrs@ (c@_sd_adrs[\1]),
+ .ics@ (c@_ics[\1]),
+ ); */
+
+ /*AUTOOUTPUT*/
+
+ autoinst_wildcard_sub sub0
+ (/*AUTOINST*/
+ // Inouts
+ .sd_ras_ (sd_ras_),
+ .sd0_dqm7_l (c0_sd_dqm_[7]), // Templated 9
+ .sd0_dqm6_l (c0_sd_dqm_[6]), // Templated 9
+ .sd0_dqm5_l (c0_sd_dqm_[5]), // Templated 9
+ .sd0_dqm4_l (c0_sd_dqm_[4]), // Templated 9
+ .sd0_dqm3_l (c0_sd_dqm_[3]), // Templated 9
+ .sd0_dqm2_l (c0_sd_dqm_[2]), // Templated 9
+ .sd0_dqm1_l (c0_sd_dqm_[1]), // Templated 9
+ .sd0_dqm0_l (c0_sd_dqm_[0]), // Templated 9
+ .sd0_ba1 (c0_sd_ba[1]), // Templated 10
+ .sd0_ba0 (c0_sd_ba[0]), // Templated 10
+ .sd0_adrs11 (c0_sd_adrs[11]), // Templated 11
+ .sd0_adrs10 (c0_sd_adrs[10]), // Templated 11
+ .sd0_adrs9 (c0_sd_adrs[9]), // Templated 11
+ .sd0_adrs8 (c0_sd_adrs[8]), // Templated 11
+ .sd0_adrs7 (c0_sd_adrs[7]), // Templated 11
+ .sd0_adrs6 (c0_sd_adrs[6]), // Templated 11
+ .sd0_adrs5 (c0_sd_adrs[5]), // Templated 11
+ .sd0_adrs4 (c0_sd_adrs[4]), // Templated 11
+ .sd0_adrs3 (c0_sd_adrs[3]), // Templated 11
+ .sd0_adrs2 (c0_sd_adrs[2]), // Templated 11
+ .sd0_adrs1 (c0_sd_adrs[1]), // Templated 11
+ .sd0_adrs0 (c0_sd_adrs[0]), // Templated 11
+ .sd0_clk (sd_clk)); // Templated 8
+
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-template-numbers: t
+// End:
diff --git a/tests_ok/autoinst_wildcard_sub.v b/tests_ok/autoinst_wildcard_sub.v
new file mode 100644
index 0000000..a5fcba8
--- /dev/null
+++ b/tests_ok/autoinst_wildcard_sub.v
@@ -0,0 +1,42 @@
+module autoinst_wildcard_sub (/*AUTOARG*/
+ // Inouts
+ sd_ras_, sd0_dqm7_l, sd0_dqm6_l, sd0_dqm5_l, sd0_dqm4_l, sd0_dqm3_l,
+ sd0_dqm2_l, sd0_dqm1_l, sd0_dqm0_l, sd0_ba1, sd0_ba0, sd0_adrs11,
+ sd0_adrs10, sd0_adrs9, sd0_adrs8, sd0_adrs7, sd0_adrs6, sd0_adrs5,
+ sd0_adrs4, sd0_adrs3, sd0_adrs2, sd0_adrs1, sd0_adrs0, sd0_clk
+ );
+
+ //======================================================================
+ // Inputs/Outputs
+ //======================================================================
+
+ inout sd_ras_; // SDRAM Channel 0 Row Address Strobe
+ inout sd0_dqm7_l; // SDRAM Channel 0 DQM Mask Bits
+ inout sd0_dqm6_l;
+ inout sd0_dqm5_l;
+ inout sd0_dqm4_l;
+ inout sd0_dqm3_l;
+ inout sd0_dqm2_l;
+ inout sd0_dqm1_l;
+ inout sd0_dqm0_l;
+ inout sd0_ba1;
+ inout sd0_ba0;
+ inout sd0_adrs11; // SDRAM Channel 0 Address
+ inout sd0_adrs10;
+ inout sd0_adrs9;
+ inout sd0_adrs8;
+ inout sd0_adrs7;
+ inout sd0_adrs6;
+ inout sd0_adrs5;
+ inout sd0_adrs4;
+ inout sd0_adrs3;
+ inout sd0_adrs2;
+ inout sd0_adrs1;
+ inout sd0_adrs0;
+ inout sd0_clk; // SDRAM Channel 0 Clocks
+
+endmodule
+
+// Local Variables:
+// fill-column: 79
+// End:
diff --git a/tests_ok/autoinst_wildcell.v b/tests_ok/autoinst_wildcell.v
new file mode 100644
index 0000000..f27cad4
--- /dev/null
+++ b/tests_ok/autoinst_wildcell.v
@@ -0,0 +1,69 @@
+module autoinst_wildcard;
+
+ /* sub AUTO_TEMPLATE (
+ .a\(.\)\(.\) (@"(substring vl-cell-name 4 5)"_@"(substring vl-cell-name 6 7)"_a_\1_\2),
+ ); */
+
+ sub sub_0_0 (/*AUTOINST*/
+ // Inputs
+ .a33 (0_0_a_3_3), // Templated 4
+ .a34 (0_0_a_3_4), // Templated 4
+ .a44 (0_0_a_4_4), // Templated 4
+ .a43 (0_0_a_4_3)); // Templated 4
+ sub sub_0_1 (/*AUTOINST*/
+ // Inputs
+ .a33 (0_1_a_3_3), // Templated 4
+ .a34 (0_1_a_3_4), // Templated 4
+ .a44 (0_1_a_4_4), // Templated 4
+ .a43 (0_1_a_4_3)); // Templated 4
+ sub sub_1_0 (/*AUTOINST*/
+ // Inputs
+ .a33 (1_0_a_3_3), // Templated 4
+ .a34 (1_0_a_3_4), // Templated 4
+ .a44 (1_0_a_4_4), // Templated 4
+ .a43 (1_0_a_4_3)); // Templated 4
+ sub sub_1_1 (/*AUTOINST*/
+ // Inputs
+ .a33 (1_1_a_3_3), // Templated 4
+ .a34 (1_1_a_3_4), // Templated 4
+ .a44 (1_1_a_4_4), // Templated 4
+ .a43 (1_1_a_4_3)); // Templated 4
+
+ /* sub AUTO_TEMPLATE (
+ .a\(.\)\(.\) (b_\1_\2),
+ ); */
+
+ sub sub_0_0 (/*AUTOINST*/
+ // Inputs
+ .a33 (b_3_3), // Templated 33
+ .a34 (b_3_4), // Templated 33
+ .a44 (b_4_4), // Templated 33
+ .a43 (b_4_3)); // Templated 33
+ sub sub_0_1 (/*AUTOINST*/
+ // Inputs
+ .a33 (b_3_3), // Templated 33
+ .a34 (b_3_4), // Templated 33
+ .a44 (b_4_4), // Templated 33
+ .a43 (b_4_3)); // Templated 33
+ sub sub_1_0 (/*AUTOINST*/
+ // Inputs
+ .a33 (b_3_3), // Templated 33
+ .a34 (b_3_4), // Templated 33
+ .a44 (b_4_4), // Templated 33
+ .a43 (b_4_3)); // Templated 33
+ sub sub_1_1 (/*AUTOINST*/
+ // Inputs
+ .a33 (b_3_3), // Templated 33
+ .a34 (b_3_4), // Templated 33
+ .a44 (b_4_4), // Templated 33
+ .a43 (b_4_3)); // Templated 33
+
+endmodule
+
+module sub;
+ input a33, a34, a44, a43;
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-template-numbers: t
+// End:
diff --git a/tests_ok/autoinstparam_belkind.v b/tests_ok/autoinstparam_belkind.v
new file mode 100644
index 0000000..9c5c343
--- /dev/null
+++ b/tests_ok/autoinstparam_belkind.v
@@ -0,0 +1,23 @@
+module autoinstparam_belkind (/*AUTOARG*/) ;
+
+ parameter X = 8;
+ /*
+ autoinstparam_belkind_leaf AUTO_TEMPLATE (
+ .P (X),
+ .a (b[]),
+ );
+ */
+
+ autoinstparam_belkind_leaf (/*AUTOINSTPARAM*/
+ // Parameters
+ .P (X)) // Templated
+ leaf(/*AUTOINST*/
+ // Inputs
+ .a (b[P-1:0])); // Templated
+
+endmodule // tree
+
+// Local Variables:
+// eval:(verilog-read-defines)
+// eval:(verilog-read-defines "autoinstparam_belkind_leaf.v")
+// End:
diff --git a/tests_ok/autoinstparam_belkind_leaf.v b/tests_ok/autoinstparam_belkind_leaf.v
new file mode 100644
index 0000000..a078968
--- /dev/null
+++ b/tests_ok/autoinstparam_belkind_leaf.v
@@ -0,0 +1,12 @@
+module autoinstparam_belkind_leaf (/*AUTOARG*/
+ // Inputs
+ a
+ ) ;
+
+ parameter P =3D 4;
+ input [P-1:0] a;
+
+endmodule // leaf
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests_ok/autoinstparam_bug287.v b/tests_ok/autoinstparam_bug287.v
new file mode 100644
index 0000000..713ac83
--- /dev/null
+++ b/tests_ok/autoinstparam_bug287.v
@@ -0,0 +1,21 @@
+module Ptest #(
+ parameter I_CONTROL = 8'h 00, R_CONTROL = 8'h00)
+ (
+ input scanTest,
+ input scanArst);
+endmodule
+
+module t;
+
+ Ptest
+ #(/*AUTOINSTPARAM*/
+ // Parameters
+ .I_CONTROL (I_CONTROL),
+ .R_CONTROL (R_CONTROL))
+ u_Ptest
+ (/*AUTOINST*/
+ // Inputs
+ .scanTest (scanTest),
+ .scanArst (scanArst));
+
+endmodule
diff --git a/tests_ok/autoinstparam_first.v b/tests_ok/autoinstparam_first.v
new file mode 100644
index 0000000..0446cb6
--- /dev/null
+++ b/tests_ok/autoinstparam_first.v
@@ -0,0 +1,63 @@
+module autoinstparam_first ();
+
+ parameter BITSCHANGED;
+ parameter BITSA;
+ parameter type BITSB_t;
+ typedef [2:0] my_bitsb_t;
+
+ /* autoinstparam_first_sub AUTO_TEMPLATE (
+ .BITSA (BITSCHANGED),
+ ); */
+
+ autoinstparam_first_sub
+ #(/*AUTOINSTPARAM*/
+ // Parameters
+ .BITSA (BITSCHANGED), // Templated
+ .BITSB_t (BITSB_t))
+ sub
+ (/*AUTOINST*/
+ // Inouts
+ .a (a[BITSA:0]),
+ .b (b));
+
+ autoinstparam_first_sub
+ #(
+ .BITSB_t (my_bitsb_t),
+ /*AUTOINSTPARAM*/
+ // Parameters
+ .BITSA (BITSCHANGED)) // Templated
+ sub1
+ (/*AUTOINST*/
+ // Inouts
+ .a (a[BITSA:0]),
+ .b (b));
+
+ autoinstparam_first_sub
+ #(
+ .BITSA (1),
+ .BITSB_t (my_bitsb_t)
+ /*AUTOINSTPARAM*/)
+ sub2
+ (/*AUTOINST*/
+ // Inouts
+ .a (a[BITSA:0]),
+ .b (b));
+
+ autoinstparam_first_sub
+ #(
+ /*AUTOINSTPARAM*/
+ // Parameters
+ .BITSA (BITSCHANGED), // Templated
+ .BITSB_t (BITSB_t))
+ sub3
+ (/*AUTOINST*/
+ // Inouts
+ .a (a[BITSA:0]),
+ .b (b));
+
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-param-value:nil
+// verilog-typedef-regexp: "_t$"
+// End:
diff --git a/tests_ok/autoinstparam_first_sub.v b/tests_ok/autoinstparam_first_sub.v
new file mode 100644
index 0000000..cb3e45c
--- /dev/null
+++ b/tests_ok/autoinstparam_first_sub.v
@@ -0,0 +1,21 @@
+module autoinstparam_first_sub (/*AUTOARG*/
+ // Inouts
+ a, b
+ );
+
+ //======================================================================
+ // Inputs/Outputs
+ //======================================================================
+
+ localparam IGNORED;
+ parameter BITSA;
+ parameter type BITSB_t = bit; // See bug340
+
+ inout [BITSA:0] a;
+ inout BITSB_t b;
+
+endmodule
+
+// Local Variables:
+// verilog-typedef-regexp: "_t$"
+// End:
diff --git a/tests_ok/autoinstparam_iface_bruce.v b/tests_ok/autoinstparam_iface_bruce.v
new file mode 100644
index 0000000..0fbc14e
--- /dev/null
+++ b/tests_ok/autoinstparam_iface_bruce.v
@@ -0,0 +1,23 @@
+module top;
+ /*AUTOWIRE*/
+ sub0 #(/*AUTOINSTPARAM*/
+ // Parameters
+ .testit2 (testit2),
+ .TESTIT (TESTIT))
+ s0 (/*AUTOINST*/
+ // Inputs
+ .side_clk (side_clk),
+ .side_rst_b (side_rst_b));
+endmodule
+
+module sub0
+ #(
+ parameter string testit2 = 0,
+ int TESTIT = 0
+ ) (
+ // clk and resets
+ input logic side_clk,
+ input logic side_rst_b,
+ );
+
+endmodule
diff --git a/tests_ok/autoinstparam_int.v b/tests_ok/autoinstparam_int.v
new file mode 100644
index 0000000..59bed79
--- /dev/null
+++ b/tests_ok/autoinstparam_int.v
@@ -0,0 +1,46 @@
+module xyz
+ #(parameter int FOO=1, BAR=2,
+ parameter logic [5:0] BLUP=3, ZOT=4,
+ parameter LDWRDS=5)
+ ( input x1, x2,
+ input int i1, i2,
+ input logic [5:0] i3, i4,
+ input i5,
+ output y);
+endmodule
+
+module pdq;
+ input x; output y;
+ parameter int FOO=1;
+endmodule
+
+module abc;
+ xyz XYZ
+ #(/*AUTOINSTPARAM*/
+ // Parameters
+ .FOO (FOO),
+ .BAR (BAR),
+ .BLUP (BLUP[5:0]),
+ .ZOT (ZOT[5:0]),
+ .LDWRDS (LDWRDS))
+ (/*AUTOINST*/
+ // Outputs
+ .y (y),
+ // Inputs
+ .x1 (x1),
+ .x2 (x2),
+ .i1 (i1),
+ .i2 (i2),
+ .i3 (i3[5:0]),
+ .i4 (i4[5:0]),
+ .i5 (i5));
+ pdq PDQ
+ #(/*AUTOINSTPARAM*/
+ // Parameters
+ .FOO (FOO))
+ (/*AUTOINST*/
+ // Outputs
+ .y (y),
+ // Inputs
+ .x (x));
+endmodule
diff --git a/tests_ok/autoinstparam_local.v b/tests_ok/autoinstparam_local.v
new file mode 100644
index 0000000..0babde5
--- /dev/null
+++ b/tests_ok/autoinstparam_local.v
@@ -0,0 +1,26 @@
+//bug889
+
+module leaf #(
+ parameter DATA_WIDTH = 256,
+ localparam STRB_WIDTH_SHOULD_BE_HIDDEN = DATA_WIDTH/8 )
+ ();
+endmodule
+
+module test;
+ parameter integer DATA_WIDTH = 256;
+ parameter integer STRB_WIDTH = DATA_WIDTH/8;
+
+ /* leaf AUTO_TEMPLATE (
+ .DATA_WIDTH( DATA_WIDTH ),
+ .STRB_WIDTH_SHOULD_BE_HIDDEN ( STRB_WIDTH ),
+ .\(.*\) ( \1 ),
+ );*/
+
+ leaf
+ #( /*AUTOINSTPARAM*/
+ // Parameters
+ .DATA_WIDTH ( DATA_WIDTH )) // Templated
+ u_leaf
+ ( /*AUTOINST*/);
+
+endmodule
diff --git a/tests_ok/autolisp_include.v b/tests_ok/autolisp_include.v
new file mode 100644
index 0000000..6f07e6b
--- /dev/null
+++ b/tests_ok/autolisp_include.v
@@ -0,0 +1,21 @@
+// See forum topic 176
+module autolisp_include (/*AUTOARG*/
+ // Outputs
+ foo,
+ // Inputs
+ bar
+ );
+
+ //`include "autolisp_include_inc.vh"
+ /*AUTOINSERTLISP(verilog-library-filenames (insert-file "autolisp_include_inc.vh"))*/
+ // Beginning of automatic insert lisp
+ input bar;
+ output foo;
+ // End of automatics
+
+ assign foo = bar;
+
+ // This doesn't need commentary
+ /*AUTOINSERTLISP(when nil)*/
+
+endmodule
diff --git a/tests_ok/autolisp_include_inc.vh b/tests_ok/autolisp_include_inc.vh
new file mode 100644
index 0000000..f9be85f
--- /dev/null
+++ b/tests_ok/autolisp_include_inc.vh
@@ -0,0 +1,2 @@
+input bar;
+output foo;
diff --git a/tests_ok/autolisp_order_bug356.v b/tests_ok/autolisp_order_bug356.v
new file mode 100644
index 0000000..d99075a
--- /dev/null
+++ b/tests_ok/autolisp_order_bug356.v
@@ -0,0 +1,47 @@
+module autolisp_top (/*AUTOARG*/);
+
+ /* autolisp_inst AUTO_TEMPLATE (
+ .\(.*\)A (\1_@"(eval tense)"_A),
+ .\(.*\)B (\1_@"(eval tense)"_B),
+ );
+ */
+ /* AUTO_LISP(setq tense "is") */
+ autolisp_inst AUTOLISP_INST_I0
+ (/*AUTOINST*/
+ // Outputs
+ .result (result),
+ // Inputs
+ .portA (port_is_A), // Templated
+ .busA (bus_is_A), // Templated
+ .portB (port_is_B), // Templated
+ .busB (bus_is_B)); // Templated
+
+ /* AUTO_LISP(setq tense "was") */
+ autolisp_inst AUTOLISP_INST_I1
+ (/*AUTOINST*/
+ // Outputs
+ .result (result),
+ // Inputs
+ .portA (port_was_A), // Templated
+ .busA (bus_was_A), // Templated
+ .portB (port_was_B), // Templated
+ .busB (bus_was_B)); // Templated
+
+endmodule
+
+
+module autolisp_inst (/*AUTOARG*/
+ // Outputs
+ result,
+ // Inputs
+ portA, busA, portB, busB
+ );
+
+ input portA;
+ input [3:0] busA;
+ input portB;
+ input [1:0] busB;
+
+ output result;
+
+endmodule
diff --git a/tests_ok/autolisp_truex.v b/tests_ok/autolisp_truex.v
new file mode 100644
index 0000000..6401d80
--- /dev/null
+++ b/tests_ok/autolisp_truex.v
@@ -0,0 +1,24 @@
+module ExampInsertLisp;
+
+ /*AUTOINSERTLISP(my-verilog-insert-hello "world")*/
+ // Beginning of automatic insert lisp
+ initial $write("hello world");
+ // End of automatics
+
+ // Try an empty insert
+ /*AUTOINSERTLISP(+ 1)*/
+
+ // Try a shell command
+ /*AUTOINSERTLISP(insert (shell-command-to-string "echo //hello"))*/
+ // Beginning of automatic insert lisp
+ //hello
+ // End of automatics
+
+endmodule
+/*
+ Local Variables:
+ eval:
+ (defun my-verilog-insert-hello (who)
+ (insert (concat "initial $write(\"hello " who "\");\n")))
+ End:
+ */
diff --git a/tests_ok/autologic.sv b/tests_ok/autologic.sv
new file mode 100644
index 0000000..7332fbd
--- /dev/null
+++ b/tests_ok/autologic.sv
@@ -0,0 +1,91 @@
+module top
+ #(parameter COLS = 4
+ )
+ ( input logic clk,
+ input logic rstb,
+ input logic [COLS-1:0] ival,
+ input logic [COLS-1:0][1:0] idata_some_extra_sig_length,
+ output logic reg_assigned
+ );
+
+ // Request: AUTOLOGIC instead of AUTOWIRE
+ // Request: AUTOLOGIC would substitute all 3 existing macros AUTOWIRE/AUTOREG/AUTOREGINPUT, one would use AUTOLOGIC instead of AUTOWIRE/AUTOREG or AUTOWIRE/AUTOREGINPUT.
+
+ // Could use AU-TOLOGIC
+ // Or AU-TOWIRE(logic)
+ // And-or (setq verilog-auto-sv t)
+ // And-or (setq verilog-auto-wire-type 'logic')
+
+ /*AUTOOUTPUTEVERY*/
+ // Beginning of automatic outputs (every signal)
+ output logic COLS;
+ output logic in1a; // To isub2 of sub2.v, ...
+ output logic in1b; // To isub1 of sub1.v
+ output logic in2b; // To isub2 of sub2.v
+ output logic out1a; // From isub1 of sub1.v
+ output logic [1:0] out1b; // From isub1 of sub1.v
+ output logic [1:0] out2b; // From isub2 of sub2.v
+ // End of automatics
+
+ /*AUTOREG*/
+
+ /*AUTOREGINPUT*/
+ // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+ logic in1a; // To isub2 of sub2.v, ...
+ logic in1b; // To isub1 of sub1.v
+ logic in2b; // To isub2 of sub2.v
+ // End of automatics
+
+ /*AUTOLOGIC*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic out1a; // From isub1 of sub1.v
+ logic [1:0] out1b; // From isub1 of sub1.v
+ logic [1:0] out2b; // From isub2 of sub2.v
+ // End of automatics
+
+ /* sub2 AUTO_TEMPLATE(
+ .idata_some_extra_sig_length ( s1_odata),
+ .ival ( s1_oval),
+ );*/
+ sub2 isub2 (/*AUTOINST*/
+ // Outputs
+ .out2b (out2b[1:0]),
+ // Inputs
+ .in1a (in1a),
+ .in2b (in2b),
+ .out1a (out1a));
+
+
+ sub1 isub1(/*AUTOINST*/
+ // Outputs
+ .out1a (out1a),
+ .out1b (out1b[1:0]),
+ // Inputs
+ .in1a (in1a),
+ .in1b (in1b));
+
+ always @(posedge clk) begin
+ reg_assigned <= 1;
+ end
+
+endmodule
+
+module sub1
+ ( input logic in1a,
+ input logic in1b,
+ output logic out1a,
+ output logic [1:0] out1b
+ );
+endmodule
+
+module sub2
+ ( input logic in1a,
+ input logic in2b,
+ input logic out1a,
+ output logic [1:0] out2b
+ );
+endmodule
+
+// Local Variables:
+// verilog-auto-wire-type: "logic"
+// End:
diff --git a/tests_ok/automodport_ex.v b/tests_ok/automodport_ex.v
new file mode 100644
index 0000000..e77b6bc
--- /dev/null
+++ b/tests_ok/automodport_ex.v
@@ -0,0 +1,27 @@
+interface ExampIf
+ ( input logic clk );
+ logic req_val;
+ logic [7:0] req_dat;
+ clocking mon_clkblk @(posedge clk);
+ input req_val;
+ input req_dat;
+ endclocking
+ modport mp(clocking mon_clkblk);
+endinterface
+
+module ExampMain
+ ( input clk,
+ /*AUTOINOUTMODPORT("ExampIf" "mp")*/
+ // Beginning of automatic in/out/inouts (from modport)
+ input req_val,
+ input [7:0] req_dat
+ // End of automatics
+ );
+
+ /*AUTOASSIGNMODPORT("ExampIf" "mp" "inst")*/
+ // Beginning of automatic assignments from modport
+ assign inst.req_dat = req_dat;
+ assign inst.req_val = req_val;
+ // End of automatics
+
+endmodule
diff --git a/tests_ok/automodport_full.v b/tests_ok/automodport_full.v
new file mode 100755
index 0000000..1606550
--- /dev/null
+++ b/tests_ok/automodport_full.v
@@ -0,0 +1,81 @@
+
+module auto_module
+ ( input my_clk,
+ input my_rst_n,
+
+
+ output manually_listed,
+
+ /*AUTOINOUTMODPORT("automodport_if" "pure_mp")*/
+ // Beginning of automatic in/out/inouts (from modport)
+ output out_pure,
+ input in_pure,
+ // End of automatics
+ //ex: input in_pure;
+ //ex: output out_pure;
+
+ /*AUTOINOUTMODPORT("automodport_if" "req_mon_mp")*/
+ // Beginning of automatic in/out/inouts (from modport)
+ input req_val,
+ input [63:0] req_dat,
+ input req_credit,
+ // End of automatics
+ //ex: input req_credit, // To auto_i of auto_intf.sv
+ //ex: input [63:0] req_data, // To auto_i of auto_intf.sv
+ //ex: input req_val, // To auto_i of auto_intf.sv
+
+ /*AUTOINOUTMODPORT("automodport_if" "rsp_drv_mp")*/
+ // Beginning of automatic in/out/inouts (from modport)
+ output [1:0] rsp_cmd,
+ output [63:0] rsp_data,
+ input rsp_credit
+ // End of automatics
+ //ex: output [1:0] rsp_cmd, // From auto_i of auto_intf.sv
+ //ex: input rsp_credit, // To auto_i of auto_intf.sv
+ //ex: output [63:0] rsp_data // From auto_i of auto_intf.sv
+ );
+
+ auto_intf auto_i
+ (// Inputs
+ .clk (my_clk),
+ .rst_n (my_rst_n));
+
+ /*AUTOASSIGNMODPORT("automodport_if" "req_mon_mp" "auto_i" )*/
+ // Beginning of automatic assignments from modport
+ assign auto_i.manually_listed = manually_listed;
+ assign auto_i.req_credit = req_credit;
+ assign auto_i.req_dat = req_dat;
+ assign auto_i.req_val = req_val;
+ // End of automatics
+ //ex: assign auto_i.req_credit = req_credit;
+ //ex: assign auto_i.req_data = req_data;
+ //ex: assign auto_i.req_val = req_val;
+
+ /*AUTOASSIGNMODPORT("automodport_if" "rsp_drv_mp" "auto_i" )*/
+ // Beginning of automatic assignments from modport
+ assign rsp_cmd = auto_i.rsp_cmd;
+ assign rsp_data = auto_i.rsp_data;
+ assign auto_i.rsp_credit = rsp_credit;
+ // End of automatics
+ //ex: assign rsp_cmd = auto_i.rsp_cmd;
+ //ex: assign rsp_data = auto_i.rsp_data;
+ //ex: assign auto_i.rsp_credit = rsp_credit;
+
+ /*AUTOASSIGNMODPORT("automodport_if" "r.*" "auto_i" )*/
+ // Beginning of automatic assignments from modport
+ assign rsp_cmd = auto_i.rsp_cmd;
+ assign rsp_data = auto_i.rsp_data;
+ assign auto_i.manually_listed = manually_listed;
+ assign auto_i.req_credit = req_credit;
+ assign auto_i.req_dat = req_dat;
+ assign auto_i.req_val = req_val;
+ assign auto_i.rsp_credit = rsp_credit;
+ // End of automatics
+
+
+ initial begin
+ `cn_set_intf(virtual auto_intf.req_mon_mp, "auto_pkg::auto_intf", "req_mon_vi", auto_i.req_mon_mp );
+ `cn_set_intf(virtual auto_intf.rsp_drv_mp, "auto_pkg::auto_intf", "rsp_drv_vi", auto_i.rsp_drv_mp );
+ end
+
+endmodule
diff --git a/tests_ok/automodport_if.v b/tests_ok/automodport_if.v
new file mode 100644
index 0000000..ecaf079
--- /dev/null
+++ b/tests_ok/automodport_if.v
@@ -0,0 +1,67 @@
+interface automodport_if
+ ( input logic clk,
+ input logic rst_n
+ );
+
+ //----------------------------------------------------------------------------------------
+ // Group: Signals
+ logic req_val;
+ logic [63:0] req_dat;
+ logic req_credit;
+
+ logic [1:0] rsp_cmd;
+ logic [63:0] rsp_data;
+ logic rsp_credit;
+
+ logic in_pure;
+ logic out_pure;
+ logic manually_listed;
+
+ //----------------------------------------------------------------------------------------
+ // Group: Clocking blocks
+ clocking req_mon_cb @(posedge clk);
+ input rst_n;
+ input req_val;
+ input req_dat;
+ input req_credit;
+ input manually_listed;
+ endclocking : req_mon_cb
+
+ clocking rsp_drv_cb @(posedge clk);
+ input rst_n;
+ output rsp_cmd;
+ output rsp_data;
+ input rsp_credit;
+ endclocking : rsp_drv_cb
+
+ //----------------------------------------------------------------------------------------
+ // Group: Modports
+ modport req_mon_mp(clocking req_mon_cb);
+ modport rsp_drv_mp(clocking rsp_drv_cb, import rsp_reset);
+ modport pure_mp(input in_pure, output out_pure);
+
+ //----------------------------------------------------------------------------------------
+ // Group: Methods
+ function void rsp_reset();
+ rsp_cmd = 2'b0;
+ rsp_data = 64'b0;
+ endfunction : rsp_reset
+
+ //----------------------------------------------------------------------------------------
+ // Group: Assertions
+ logic [1:0] cmd_m1;
+
+ always @(posedge clk) begin
+ cmd_m1 <= rsp_cmd;
+ if(rst_n) begin
+ if($isunknown(req_val)) `cn_err_intf(("Signal req_data_cycle is an X."));
+ if(req_val==1'b1 & $isunknown(req_data)) `cn_err_intf(("Signal req_data is an X."));
+ if($isunknown(req_credit)) `cn_err_intf(("Signal req_credit is an X."));
+
+ if($isunknown(rsp_cmd)) `cn_err_intf(("Signal rsp_cmd is an X."));
+ if(cmd_m1!=2'b0 & $isunknown(rsp_data)) `cn_err_intf(("Signal rsp_data is an X."));
+ if($isunknown(rsp_credit)) `cn_err_intf(("Signal rsp_credit is an X."));
+ end
+ end
+
+endinterface
diff --git a/tests_ok/autooutput_comma.v b/tests_ok/autooutput_comma.v
new file mode 100644
index 0000000..9d8110a
--- /dev/null
+++ b/tests_ok/autooutput_comma.v
@@ -0,0 +1,57 @@
+module top
+ (input [(`WIDTH):0] a, /* This comma gets deleted */
+ /*AUTOOUTPUT*/
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input b // To child of child.v
+ // End of automatics
+ );
+
+ child child(/*AUTOINST*/
+ // Inputs
+ .b (b));
+endmodule
+
+module nocomma
+ (/*AUTOOUTPUT*/
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input b // To child of child.v
+ // End of automatics
+ );
+ child child(/*AUTOINST*/
+ // Inputs
+ .b (b));
+endmodule
+
+module ifdefcomma
+ (
+`ifdef a
+ input foo,
+`endif
+ /*AUTOOUTPUT*/
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input b // To child of child.v
+ // End of automatics
+ );
+ child child(/*AUTOINST*/
+ // Inputs
+ .b (b));
+endmodule
+
+module ifdefnocomma
+ (
+`ifdef a
+ // It's up to the user to deal with the , themself
+ input foo,
+`endif
+ /*AUTOOUTPUT*/
+ );
+ child child(/*AUTOINST*/
+ // Inputs
+ .b (b));
+endmodule
+
+module child(input b);
+endmodule
diff --git a/tests_ok/autooutput_regexp.v b/tests_ok/autooutput_regexp.v
new file mode 100644
index 0000000..9a41be4
--- /dev/null
+++ b/tests_ok/autooutput_regexp.v
@@ -0,0 +1,26 @@
+module ex_output_every (/*AUTOARG*/
+ // Outputs
+ sub1_out_pixel
+ )
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output pixel24_t sub1_out_pixel; // From i1 of v2k_typedef_yee_sub1.v
+ // End of automatics
+
+ v2k_typedef_yee_sub1 i1
+ (/*AUTOINST*/
+ // Outputs
+ .sub1_out_pixel (sub1_out_pixel),
+ .sub1_to_sub2 (sub1_to_sub2),
+ .sub1_to_sub2_and_top (sub1_to_sub2_and_top),
+ // Inputs
+ .sub1_in_pixel (sub1_in_pixel),
+ .cp (cp),
+ .reset (reset));
+
+endmodule
+
+// Local Variables:
+// verilog-auto-output-ignore-regexp:"^sub1_to_sub2"
+// End:
diff --git a/tests_ok/autooutputevery_assign.v b/tests_ok/autooutputevery_assign.v
new file mode 100644
index 0000000..f7c615e
--- /dev/null
+++ b/tests_ok/autooutputevery_assign.v
@@ -0,0 +1,18 @@
+module ex_output_every (o,i,tempa,tempb)
+ output o;
+ input i;
+
+ /*AUTOOUTPUTEVERY*/
+ // Beginning of automatic outputs (every signal)
+ output tempa;
+ output tempb;
+ // End of automatics
+
+ wire tempa;
+ wire tempb;
+ wire o;
+
+ assign tempa = i;
+ assign tempb = tempa;
+ assign o = tempb;
+endmodule
diff --git a/tests_ok/autooutputevery_example.v b/tests_ok/autooutputevery_example.v
new file mode 100644
index 0000000..4d46e60
--- /dev/null
+++ b/tests_ok/autooutputevery_example.v
@@ -0,0 +1,15 @@
+module ex_output_every (o,i,tempa,tempb)
+ output o;
+ input i;
+
+ /*AUTOOUTPUTEVERY*/
+ // Beginning of automatic outputs (every signal)
+ output tempa;
+ output tempb;
+ // End of automatics
+
+ wire tempa = i;
+ wire tempb = tempa;
+ wire o = tempb;
+
+endmodule
diff --git a/tests_ok/autooutputevery_regexp.v b/tests_ok/autooutputevery_regexp.v
new file mode 100644
index 0000000..a7d1b65
--- /dev/null
+++ b/tests_ok/autooutputevery_regexp.v
@@ -0,0 +1,13 @@
+module top
+ (
+ /*AUTOOUTPUTEVERY("^a")*/
+ // Beginning of automatic outputs (every signal)
+ output aa,
+ output ab
+ // End of automatics
+ );
+
+ wire aa;
+ wire ab;
+ wire cc;
+endmodule
diff --git a/tests_ok/autooutputevery_wire.v b/tests_ok/autooutputevery_wire.v
new file mode 100644
index 0000000..433017e
--- /dev/null
+++ b/tests_ok/autooutputevery_wire.v
@@ -0,0 +1,65 @@
+module test (/*AUTOARG*/
+ // Outputs
+ stage2_bus, stage3_bus,
+ // Inputs
+ stage1_bus
+ );
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output logic [7:0] stage3_bus; // From i_second of sub_module.v
+ // End of automatics
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input logic [7:0] stage1_bus; // To i_first of sub_module.v
+ // End of automatics
+ /*AUTOOUTPUTEVERY("^stage")*/
+ // Beginning of automatic outputs (every signal)
+ output logic [7:0] stage2_bus; // From i_first of sub_module.v
+ // End of automatics
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic [7:0] stage2_bus; // From i_first of sub_module.v
+ // End of automatics
+ /*AUTOREG*/
+
+ /* sub_module AUTO_TEMPLATE
+ (
+ .i_\(.*\) (stage1_\1[]),
+ .o_\(.*\) (stage2_\1[]),
+ ); */
+
+ sub_module i_first (/*AUTOINST*/
+ // Outputs
+ .o_bus (stage2_bus[7:0]), // Templated
+ // Inputs
+ .i_bus (stage1_bus[7:0])); // Templated
+
+ /* sub_module AUTO_TEMPLATE
+ (
+ .i_\(.*\) (stage2_\1[]),
+ .o_\(.*\) (stage3_\1[]),
+ ); */
+
+ sub_module i_second (/*AUTOINST*/
+ // Outputs
+ .o_bus (stage3_bus[7:0]), // Templated
+ // Inputs
+ .i_bus (stage2_bus[7:0])); // Templated
+
+endmodule // test
+
+module sub_module (/*AUTOARG*/
+ // Outputs
+ o_bus,
+ // Inputs
+ i_bus
+ );
+
+ input logic [7:0] i_bus ;
+ output logic [7:0] o_bus ;
+
+ assign o_bus = i_bus;
+
+endmodule // sub_module
diff --git a/tests_ok/autoreg_outreg.v b/tests_ok/autoreg_outreg.v
new file mode 100644
index 0000000..49775ec
--- /dev/null
+++ b/tests_ok/autoreg_outreg.v
@@ -0,0 +1,22 @@
+module foo
+ #(parameter
+ PARAM3_P=99)
+ (
+ output sig3,// Here, I've hit "tab" twice and this line is correct
+ output reg [PARAM2_P-1:0] s4, // Comment here which should be at "comment-column"
+ output wire [PARAM2_P-1:0] sig5,// Comment here which should be at "comment-column"
+ input reset_L// module reset: global register
+ );
+
+ /*AUTOWIRE*/
+
+ // AUTOREG here is somewhat illegal, as outputs when a type is declared
+ // in a V2K decl list are automatically "reg'ed".
+ // However some simulators take it, so be sane and only do undeclared ones...
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg sig3;
+ // End of automatics
+
+endmodule
diff --git a/tests_ok/autoreg_smith_multiassign.v b/tests_ok/autoreg_smith_multiassign.v
new file mode 100644
index 0000000..f3c70d9
--- /dev/null
+++ b/tests_ok/autoreg_smith_multiassign.v
@@ -0,0 +1,19 @@
+module test(/*AUTOARG*/
+ // Outputs
+ a1, b1, c1, one
+ );
+
+ output [5:0] a1;
+ output [5:0] b1;
+ output [5:0] c1;
+
+ /*AUTOREG*/
+
+ //wire [5:0] a2,b2,c2;
+
+ assign {a1,b1,c1} = {a2,b2,c2};
+
+ output [1:0] one;
+ assign one = a2[0];
+
+endmodule
diff --git a/tests_ok/autoreginput.v b/tests_ok/autoreginput.v
new file mode 100644
index 0000000..52e03d1
--- /dev/null
+++ b/tests_ok/autoreginput.v
@@ -0,0 +1,21 @@
+module autoreginput;
+
+ /*AUTOREGINPUT*/
+ // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+ reg lower_ina; // To inst of inst.v
+ reg lower_inb; // To inst of inst.v
+ // End of automatics
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire lower_out; // From inst of inst.v
+ // End of automatics
+
+ inst inst (/*AUTOINST*/
+ // Outputs
+ .lower_out (lower_out),
+ // Inputs
+ .lower_inb (lower_inb),
+ .lower_ina (lower_ina));
+
+endmodule
+
diff --git a/tests_ok/autoreset_assert.v b/tests_ok/autoreset_assert.v
new file mode 100644
index 0000000..471904c
--- /dev/null
+++ b/tests_ok/autoreset_assert.v
@@ -0,0 +1,22 @@
+module foo;
+
+ reg [1:0] a;
+
+ assert property (@(posedge clk) e |-> f);
+
+ reg [1:0] b;
+
+ always @(posedge clk, negedge rst)
+ if (~rst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ a <= 2'h0;
+ b <= 2'h0;
+ // End of automatics
+ end
+ else begin
+ a<=b;
+ b<=a;
+ end
+
+endmodule
diff --git a/tests_ok/autoreset_cond.v b/tests_ok/autoreset_cond.v
new file mode 100644
index 0000000..3a505c7
--- /dev/null
+++ b/tests_ok/autoreset_cond.v
@@ -0,0 +1,20 @@
+module x;
+ reg [1:0] idx_sel_2a;
+ always @(posedge usclk or negedge srst_0a_n) begin
+ if (~srst_0a_n) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ bar <= 1'h0;
+ foo <= 1'h0;
+ // End of automatics
+ end
+ else begin
+ foo <= idx_adr_1a[1:0];
+ bar <= (idx_sel_2a == 2'h0 ? idx_rd_dat0_2a[12:0] :
+ idx_sel_2a == 2'h1 ? idx_rd_dat1_2a[12:0] :
+ idx_sel_2a == 2'h2 ? idx_rd_dat2_2a[12:0] :
+ /**/ idx_rd_dat3_2a[12:0]);
+ end
+ end
+
+endmodule
diff --git a/tests_ok/autoreset_define_colon.v b/tests_ok/autoreset_define_colon.v
new file mode 100644
index 0000000..9cd800d
--- /dev/null
+++ b/tests_ok/autoreset_define_colon.v
@@ -0,0 +1,33 @@
+// bug594
+`define TABADR_EGR_MOD_MAP 7:0
+
+module test (
+ /*AUTOARG*/
+ // Inputs
+ clk, rst, addr
+ );
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+
+ input clk;
+ input rst;
+ input [`TABADR_EGR_MOD_MAP] addr;
+
+
+ reg [`TABADR_EGR_MOD_MAP] addrD1;
+ reg [`TABADR_EGR_MOD_MAP] addrD2;
+
+ always @(posedge clk or posedge rst) begin
+ if (rst_l) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ addrD1 <= `0/*NOWIDTH*/;
+ addrD2 <= `0/*NOWIDTH*/;
+ // End of automatics
+ end
+ else begin
+ addrD1 <= addr ;
+ addrD2 <= addrD1;
+ end
+ end
+endmodule
diff --git a/tests_ok/autoreset_dever.v b/tests_ok/autoreset_dever.v
new file mode 100644
index 0000000..8aa8a6d
--- /dev/null
+++ b/tests_ok/autoreset_dever.v
@@ -0,0 +1,52 @@
+module x;
+ always @(posedge piclk) begin
+ if (k_i_reset) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ idat_ICErrData_i3 <= 1'h0;
+ // End of automatics
+ end
+ else begin
+ idat_ICErrData_i3 <= idat_way0_i2[1*OPCWID-1:0*OPCWID];
+ end
+ end
+
+ // 2010-04-08
+ localparam MPND = 5;
+ always @(posedge usclk)
+ if (~sso_srst_n) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rd_dat_s4 <= 1'h0;
+ sel_s3 <= 1'h0;
+ // End of automatics
+ end
+ else begin
+ sel_s3 <= adr_s2[MIDX];
+ rd_dat_s4 <= (sel_s3 == 1'h0 ? rd_dat0_s3[MPND:0]
+ : rd_dat1_s3[MPND:0]);
+ end
+
+ // 2010-04-15
+ integer i;
+ always @(posedge usclk)
+ if (~sso_srst_n) begin
+ for (int j=0; j<10; j++) blob[j] <= 0;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ zsv <= 1'h0;
+ zz <= 1'h0;
+ // End of automatics
+ end
+ else begin
+ for (i=0; i<10; i++) blob[i] <= blob[i+1];
+ for (i=0; i<10; i++) zz <= 1;
+ for (int isv=0; isv<10; isv++) zsv <= 1;
+ end
+
+ always @(/*AS*/in) begin
+ for (i=0; i<10; i++) zz <= in;
+ for (int isv=0; isv<10; isv++) zsv <= in;
+ end
+
+endmodule
diff --git a/tests_ok/autoreset_eq_bug381.v b/tests_ok/autoreset_eq_bug381.v
new file mode 100644
index 0000000..7bfead8
--- /dev/null
+++ b/tests_ok/autoreset_eq_bug381.v
@@ -0,0 +1,29 @@
+module t();
+
+ logic [31:0] sum;
+ logic [31:0] a;
+ logic [31:0] b;
+ reg [32:0] tmp;
+
+ always @(posedge clk or negedge rst) begin
+ if (!rst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ sum <= 32'h0;
+ // End of automatics
+ end
+ else begin
+ //reg [32:0] tmp;
+ tmp = a + b;
+ if (tmp[32])
+ sum <= 32'hffffffff;
+ else
+ sum <= tmp[31:0];
+ end
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-reset-blocking-in-non: nil
+// End:
diff --git a/tests_ok/autoreset_eq_bug381_non.v b/tests_ok/autoreset_eq_bug381_non.v
new file mode 100644
index 0000000..162d862
--- /dev/null
+++ b/tests_ok/autoreset_eq_bug381_non.v
@@ -0,0 +1,30 @@
+module t();
+
+ logic [31:0] sum;
+ logic [31:0] a;
+ logic [31:0] b;
+ reg [32:0] tmp;
+
+ always @(posedge clk or negedge rst) begin
+ if (!rst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ sum <= 32'h0;
+ tmp = 33'h0;
+ // End of automatics
+ end
+ else begin
+ //reg [32:0] tmp;
+ tmp = a + b;
+ if (tmp[32])
+ sum <= 32'hffffffff;
+ else
+ sum <= tmp[31:0];
+ end
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-reset-blocking-in-non: t
+// End:
diff --git a/tests_ok/autoreset_equal_extra.v b/tests_ok/autoreset_equal_extra.v
new file mode 100644
index 0000000..d8f7524
--- /dev/null
+++ b/tests_ok/autoreset_equal_extra.v
@@ -0,0 +1,41 @@
+module autoreset_equal_extra ();
+
+ always_ff @(posedge csclk) begin
+ if( ~srst_n | !val_tx_to_csi ) begin
+ csi.cmd <= ncbo_cmd_t'('0);
+ // vvvvvv fifo.data.cb_req.req.cmd = '0; should not be below
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ csi.src <= 1'h0;
+ csi.wr <= 1'h0;
+ // End of automatics
+ end
+ else begin
+ if (fifo.sot) begin
+ csi.src <= fifo.src;
+ csi.wr <= (fifo.data.cb_req.req.cmd == ncb_defs::NCBO_RSVD_LMTST
+ | fifo.data.cb_req.req.cmd == ncb_defs::NCBO_IOBST
+ );
+ csi.cmd <= fifo.data.cb_req.req.cmd;
+ end
+ end
+ end
+
+ always_ff @(posedge csclk) begin
+ if (~srst_n) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ sdp__x2p.bval <= 1'h0;
+ sdp__x2p.err <= 1'h0;
+ // End of automatics
+ end
+ else begin
+ sdp__x2p.err <= (x2p_fifo_rdat.err & x2p_fifo_pop_d3_sk)
+ ? x2p_p2x_roc_rtl_pkg::X2P_PKT_ERR_RCVERR
+ : x2p_p2x_roc_rtl_pkg::X2P_PKT_ERR_NONE;
+ sdp__x2p.bval <= x2p_fifo_rdat.bval & {4{x2p_fifo_pop_d3_sk}};
+ //FOO::bar <= 1; // Legal, though not typically used in RTL
+ end
+ end
+
+endmodule
diff --git a/tests_ok/autoreset_if.v b/tests_ok/autoreset_if.v
new file mode 100644
index 0000000..b7edfdc
--- /dev/null
+++ b/tests_ok/autoreset_if.v
@@ -0,0 +1,74 @@
+//From: "Chris Kappler" <ckappler@hhnetwk.com>
+
+//Verilint 440 off // WARNING: Clock is used as a reset
+//Verilint 394 off // WARNING: Multiple clocks in the always block
+//Verilint 71 off // WARNING: Case statement without default clause
+
+module x (/*AUTOARG*/
+ // Outputs
+ a, b, c,
+ // Inputs
+ clk, reset_l, in_a, in_b, in_c
+ );
+
+ input clk, reset_l, in_a,in_b,in_c;
+ output a,b,c;
+ reg a,b,c;
+
+ always @(posedge clk or negedge reset_l) begin
+ if (!reset_l) begin
+ c <= 1;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ a <= #1 0;
+ b <= #1 0;
+ // End of automatics
+ end
+ else begin
+ a <= in_a;
+ b <= in_b;
+ c <= in_c;
+ end
+ end
+
+ always @(posedge clk or negedge reset_l) begin
+ casex ({reset_l,in_a})
+ 2'b1_x: begin
+ a <= in_a;
+ b <= in_b;
+ c <= in_c;
+ end
+ 2'b0_x: begin
+ c <= 1;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ a <= #1 0;
+ b <= #1 0;
+ // End of automatics
+ end
+ endcase
+ end
+
+ always @(/*AS*/in_a or in_b or reset_l) begin
+ casex ({reset_l,in_a})
+ 2'b1_x: begin
+ a = in_a;
+ b = in_b;
+ end
+ 2'b0_x: begin
+ c = 1;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ a = 0;
+ b = 0;
+ // End of automatics
+ end
+ endcase
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-reset-widths: nil
+// verilog-assignment-delay: "#1 "
+// End:
diff --git a/tests_ok/autoreset_ifndef_dc.v b/tests_ok/autoreset_ifndef_dc.v
new file mode 100644
index 0000000..ad5407d
--- /dev/null
+++ b/tests_ok/autoreset_ifndef_dc.v
@@ -0,0 +1,21 @@
+module x;
+ always @(posedge clk or negedge reset_l) begin
+ if (!reset_l) begin
+ c <= 1;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ a <= 1'h0;
+ b <= 1'h0;
+ x <= 1'h0;
+ // End of automatics
+ end
+ else begin
+ a <= in_a;
+ b <= in_b;
+ c <= in_c;
+`ifndef DC
+ x <= 1'b1;
+`endif
+ end
+ end
+endmodule
diff --git a/tests_ok/autoreset_inf_bug325.v b/tests_ok/autoreset_inf_bug325.v
new file mode 100644
index 0000000..2bc0efa
--- /dev/null
+++ b/tests_ok/autoreset_inf_bug325.v
@@ -0,0 +1,9 @@
+module aaa();
+ always @(a) begin
+ if (a) begin
+ /*AUTORESET*/
+ end
+ // note missing e-n-d
+ always @(*) begin
+ end
+endmodule
diff --git a/tests_ok/autoreset_label_gorfajn.v b/tests_ok/autoreset_label_gorfajn.v
new file mode 100644
index 0000000..1b2c3d7
--- /dev/null
+++ b/tests_ok/autoreset_label_gorfajn.v
@@ -0,0 +1,16 @@
+module autoreset_label_gorfajn;
+
+ always_ff @(posedge clk or negedge reset)
+ if (~reset) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ a <= 1'h0;
+ z <= 1'h0;
+ // End of automatics
+ end else begin
+ a<=b;
+ foo: assert (b==4);
+ bar: z<=1;
+ end
+
+endmodule
diff --git a/tests_ok/autoreset_latch.v b/tests_ok/autoreset_latch.v
new file mode 100644
index 0000000..dac52d1
--- /dev/null
+++ b/tests_ok/autoreset_latch.v
@@ -0,0 +1,79 @@
+//bug844
+module device(
+ input clk,
+ output logic [7:0] Q, out0,
+ output logic pass, fail
+ input [7:0] D, in0,in1 );
+
+ enum logic [2:0] {IDLE, START, RUN, PASS, FAIL } state, next_state;
+ logic ready, next_ready;
+ logic next_pass, next_fail;
+
+ always_ff @(posedge clk, negedge rstn)
+ if (!rstn) begin
+ state <= IDLE;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ fail <= 1'h0;
+ pass <= 1'h0;
+ ready <= 1'h0;
+ // End of automatics
+ end
+ else begin
+ state <= next_state;
+ ready <= next_ready;
+ pass <= next_pass;
+ fail <= next_fail;
+ end
+
+ always @* begin
+ if (!ready) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ out0 = 8'h0;
+ // End of automatics
+ end
+ else begin
+ out0 = sel ? in1 : in0;
+ end
+ end
+
+ always_comb begin
+ next_state = state;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ next_fail = 1'h0;
+ next_pass = 1'h0;
+ next_ready = 1'h0;
+ // End of automatics
+ case (state)
+ IDLE : begin
+ // stuff ...
+ end
+ /* Other states */
+ PASS: begin
+ next_state = IDLE;
+ // stuff ...
+ next_pass = 1'b1;
+ next_ready = 1'b1;
+ end
+ FAIL: begin
+ next_state = IDLE;
+ // stuff ...
+ next_fail = 1'b1;
+ end
+ endcase
+ end
+
+ always_latch begin
+ if (!rstn) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ Q <= 8'h0;
+ // End of automatics
+ end
+ else if (clk) begin
+ Q <= D;
+ end
+ end
+endmodule
diff --git a/tests_ok/autoreset_reed.v b/tests_ok/autoreset_reed.v
new file mode 100644
index 0000000..39602e1
--- /dev/null
+++ b/tests_ok/autoreset_reed.v
@@ -0,0 +1,34 @@
+module x;
+ reg a;
+ reg b;
+ reg c;
+ always @(/*AUTOSENSE*/a or b or rst) begin
+ if ( rst ) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ c = 1'h0;
+ // End of automatics
+ end
+ else begin
+ if ( a <= b ) begin
+ c = a;
+ end
+ else begin
+ c = b;
+ end
+ end
+ end
+
+ always @ (posedge a) begin
+ if ( rst ) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ c <= 1'h0;
+ // End of automatics
+ end
+ else if ( a <= b ) begin
+ c <= a;
+ end
+ end
+
+endmodule
diff --git a/tests_ok/autoreset_struct.v b/tests_ok/autoreset_struct.v
new file mode 100644
index 0000000..26f221d
--- /dev/null
+++ b/tests_ok/autoreset_struct.v
@@ -0,0 +1,69 @@
+//bug906
+
+import gmcupkg::*;
+
+module gminstdecode
+ (
+ output instClassType instClass
+ /*blah blah blah*/);
+
+ always_comb begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ instClass.iFunc = '0;
+ instClass.isBool = '0;
+ instClass.sub.bool = '0;
+ instClass.sub2.sub3.bool = '0;
+ // End of automatics
+
+ if (ldBitFromIo | stBitToIo) begin
+ instClass.isBool = 1'b1;
+ instClass.iFunc = IFUNC_BOOL;
+ instClass.sub.bool = 1'b1;
+ instClass.sub2.sub3.bool = 1'b1;
+ end
+ end
+
+ always_comb begin
+ instClass = '{default:0}; // #1 (see below)
+ /*AUTORESET*/
+
+ if (ldBitFromIo | stBitToIo) begin
+ instClass.isBool = 1'b1;
+ instClass.iFunc = IFUNC_BOOL;
+ end
+ end
+
+ always_comb begin
+ instClass.iFunc = IFUNC_ADD; // #2
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ instClass.isBool = '0;
+ // End of automatics
+
+ if (ldBitFromIo | stBitToIo) begin
+ instClass.isBool = 1'b1;
+ instClass.iFunc = IFUNC_BOOL;
+ end
+ end
+
+ always_comb begin
+ instClass.sub = '0;
+ instClass.sub2 = '0;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ instClass.sub3.sub4.bool = '0;
+ // End of automatics
+
+ if (ldBitFromIo | stBitToIo) begin
+ instClass.sub.bool = 1'b1;
+ instClass.sub2.sub3.bool = 1'b1;
+ instClass.sub3.sub4.bool = 1'b1;
+ end
+ end
+endmodule
+
+// Local Variables:
+// verilog-auto-reset-widths: unbased
+// verilog-typedef-regexp: "Type$"
+// End:
diff --git a/tests_ok/autoreset_widths.v b/tests_ok/autoreset_widths.v
new file mode 100644
index 0000000..bf36a32
--- /dev/null
+++ b/tests_ok/autoreset_widths.v
@@ -0,0 +1,72 @@
+// $Revision: #70 $$Date: 2002/10/19 $$Author: wsnyder $ -*- Verilog -*-
+//====================================================================
+
+module CmpEng (/*AUTOARG*/
+ // Inputs
+ clk, reset_l
+ );
+
+ input clk;
+ input reset_l;
+
+ // ****************************************************************
+
+ /*AUTOREG*/
+ /*AUTOWIRE*/
+
+ // ********* Prefetch FSM definitions ****************************
+
+ reg [3:0] m_cac_state_r;
+
+ reg [2:0] m_cac_sel_r, m_dat_sel_r, m_cac_rw_sel_r;
+
+ reg m_wid1_r;
+ reg [2:0] m_wid3_r;
+ reg [5:2] m_wid4_r_l;
+
+ logic [4:1] logic_four;
+
+ logic [PARAM-1:0] paramed;
+
+`define M 2
+`define L 1
+ parameter MS = 2;
+ parameter LS = 1;
+
+ reg [MS:LS] m_param_r;
+ reg [`M:`L] m_def2_r;
+
+ always @ (posedge clk) begin
+ if (~reset_l) begin
+ m_cac_state_r <= CAC_IDLE;
+ m_cac_sel_r <= CSEL_PF;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ logic_four <= 4'h0;
+ m_def2_r <= {(1+(`M)-(`L)){1'b0}};
+ m_param_r <= {(1+(MS)-(LS)){1'b0}};
+ m_wid1_r <= 1'h0;
+ m_wid3_r <= 3'h0;
+ m_wid4_r_l <= ~4'h0;
+ paramed <= {PARAM{1'b0}};
+ // End of automatics
+ end
+ else begin
+ m_wid1_r <= 0;
+ m_wid3_r <= 0;
+ m_wid4_r_l <= 0;
+ m_param_r <= 0;
+ m_def2_r <= 0;
+ logic_four <= 4;
+ paramed <= 1;
+ end
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// verilog-auto-sense-defines-constant: t
+// verilog-auto-reset-widths: t
+// verilog-active-low-regexp: "_l$"
+// End:
diff --git a/tests_ok/autoreset_widths_unbased.v b/tests_ok/autoreset_widths_unbased.v
new file mode 100644
index 0000000..6a9beb8
--- /dev/null
+++ b/tests_ok/autoreset_widths_unbased.v
@@ -0,0 +1,72 @@
+// $Revision: #70 $$Date: 2002/10/19 $$Author: wsnyder $ -*- Verilog -*-
+//====================================================================
+
+module CmpEng (/*AUTOARG*/
+ // Inputs
+ clk, reset_l
+ );
+
+ input clk;
+ input reset_l;
+
+ // ****************************************************************
+
+ /*AUTOREG*/
+ /*AUTOWIRE*/
+
+ // ********* Prefetch FSM definitions ****************************
+
+ reg [3:0] m_cac_state_r;
+
+ reg [2:0] m_cac_sel_r, m_dat_sel_r, m_cac_rw_sel_r;
+
+ reg m_wid1_r;
+ reg [2:0] m_wid3_r;
+ reg [5:2] m_wid4_r_l;
+
+ logic [4:1] logic_four;
+
+ logic [PARAM-1:0] paramed;
+
+`define M 2
+`define L 1
+ parameter MS = 2;
+ parameter LS = 1;
+
+ reg [MS:LS] m_param_r;
+ reg [`M:`L] m_def2_r;
+
+ always @ (posedge clk) begin
+ if (~reset_l) begin
+ m_cac_state_r <= CAC_IDLE;
+ m_cac_sel_r <= CSEL_PF;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ logic_four <= '0;
+ m_def2_r <= '0;
+ m_param_r <= '0;
+ m_wid1_r <= '0;
+ m_wid3_r <= '0;
+ m_wid4_r_l <= ~'0;
+ paramed <= '0;
+ // End of automatics
+ end
+ else begin
+ m_wid1_r <= 0;
+ m_wid3_r <= 0;
+ m_wid4_r_l <= 0;
+ m_param_r <= 0;
+ m_def2_r <= 0;
+ logic_four <= 4;
+ paramed <= 1;
+ end
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// verilog-auto-sense-defines-constant: t
+// verilog-auto-reset-widths: unbased
+// verilog-active-low-regexp: "_l$"
+// End:
diff --git a/tests_ok/autosense.v b/tests_ok/autosense.v
new file mode 100644
index 0000000..a9213ab
--- /dev/null
+++ b/tests_ok/autosense.v
@@ -0,0 +1,48 @@
+module autosense (/*AUTOARG*/
+ // Outputs
+ out, out2,
+ // Inputs
+ ina, inb, inc
+ );
+
+ input ina;
+ input inb;
+ input inc;
+ output [1:0] out;
+ output out2;
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg [1:0] out;
+ reg out2;
+ // End of automatics
+
+`include "autosense_inc_param.v"
+`include "autosense_one.v"
+`define Input ina
+
+ always @(/*AUTOSENSE*/ina or inb or inc) begin
+ case (inc)
+ 1'b1: out = {`Input ? `one : 1'b0, `Input};
+ default: out = {2{inb}};
+ endcase
+ end
+
+
+ always @(/*AUTOSENSE*/ina) begin
+ out2 = `Input | PARAM_TWO | PARAM_THREE | PARAM_FOUR;
+ end
+
+ always @(*) begin
+ // @ (/*AS*/)
+ out3 = ina;
+ end
+
+ always @* begin
+ out3 = ina;
+ end
+
+endmodule
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests_ok/autosense_aas_ifdef.v b/tests_ok/autosense_aas_ifdef.v
new file mode 100644
index 0000000..dd2089f
--- /dev/null
+++ b/tests_ok/autosense_aas_ifdef.v
@@ -0,0 +1,54 @@
+module dummy;
+
+ parameter [TSTBITS-1:0] // synopsys enum tstate_info
+ TIDLE = 3'b000,
+ TCN1 = 3'b001,
+ TCN2 = TCN1+1, // must be numbered consecutively
+ TCN3 = TCN2+1,
+ TCN4 = TCN3+1,
+ TCN5 = TCN4+1,
+ IOCLR = TCN5+1,
+ TUNU1 = 3'b111;
+
+ // state and output logic
+ always @ (`ifdef SIMFSM
+ ireset or
+`endif
+ /*AUTOSENSE*/fooc2_qual or foocr_we or ioclrinst or tstate) begin
+ ioclrtmout = 1'b0;
+ case (tstate)
+ TIDLE: begin
+ if (foocr_we)
+ ntstate = TCN1;
+ else
+ ntstate = TIDLE;
+ end
+ TCN1,TCN2,TCN3,TCN4,TCN5: begin
+ if (ioclrinst | fooc2_qual)
+ ntstate = TIDLE;
+ else
+ ntstate = tstate + 1;
+ end
+ IOCLR: begin
+ ntstate = TIDLE;
+ ioclrtmout = 1'b1;
+ end
+ TUNU1: begin
+ ntstate = TIDLE;
+`ifdef SIMFSM
+ if (~ireset)
+ $display("ERROR: entered unused state at %t",$time);
+`endif
+ end
+ default: begin
+ ntstate = 'bx;
+ ioclrtmout = 1'bx;
+`ifdef SIMFSM
+ if (~ireset)
+ $display("ERROR: entered unknown state at %t",$time);
+`endif
+ end
+ endcase // case(tstate)
+ end // always @ (...
+
+endmodule // dummy
diff --git a/tests_ok/autosense_add_or.v b/tests_ok/autosense_add_or.v
new file mode 100644
index 0000000..fe0d2fa
--- /dev/null
+++ b/tests_ok/autosense_add_or.v
@@ -0,0 +1,24 @@
+module autosense_or(/*AUTOARG*/
+ // Outputs
+ x, y,
+ // Inputs
+ a, c
+ );
+
+ input a;
+ input c;
+ output x;
+ output y;
+
+ always @(a/*AUTOSENSE*/) begin
+ x = a;
+ end
+ always @(a/*AUTOSENSE*/ or c) begin
+ x = a | c;
+ end
+ // always @(a or/*AUTOSENSE*/c) begin
+ // x = a | c;
+ // end
+
+endmodule
+
diff --git a/tests_ok/autosense_chadha.v b/tests_ok/autosense_chadha.v
new file mode 100644
index 0000000..8fc00bb
--- /dev/null
+++ b/tests_ok/autosense_chadha.v
@@ -0,0 +1,37 @@
+module test (/*AUTOARG*/
+ // Outputs
+ out1, out2,
+ // Inputs
+ sel, in0, in1, in2
+ );
+
+ input [1:0] sel;
+ input in0, in1, in2;
+
+ output out1;
+ output out2;
+
+ reg out1;
+ reg out2;
+
+ // Missing in2
+ always @ (/*AS*/in0 or in1 or in2 or sel)
+ if (sel == 2'b00)
+ begin
+ out1 = in1;
+ out2 = in0;
+ end
+ else
+ begin
+ out1 = in2;
+ out2 = in1;
+ end
+
+ // OK
+ always @ (/*AS*/in1 or in2 or sel)
+ if (sel == 2'b00)
+ out1 = in1;
+ else
+ out1 = in2;
+
+endmodule // test
diff --git a/tests_ok/autosense_define_hang.v b/tests_ok/autosense_define_hang.v
new file mode 100644
index 0000000..eec7cbf
--- /dev/null
+++ b/tests_ok/autosense_define_hang.v
@@ -0,0 +1,8 @@
+//From: Anup Sharma <asharma@Eng.Sun.COM>
+
+module x;
+
+ always @ (/*AS*/`EC_EXCLU or `EC_SHARE or jpack_share) begin
+ jb_mc_xact_state_a1[2:0] <= #1 jpack_share[7] ? `EC_SHARE : `EC_EXCLU;
+ end
+endmodule
diff --git a/tests_ok/autosense_dittrich.v b/tests_ok/autosense_dittrich.v
new file mode 100644
index 0000000..6981706
--- /dev/null
+++ b/tests_ok/autosense_dittrich.v
@@ -0,0 +1,29 @@
+module testcase
+ (/*AUTOARG*/
+ // Outputs
+ Z,
+ // Inputs
+ A, B, C, D, SEL
+ );
+
+ input A, B, C, D;
+ input [1:0] SEL;
+ output Z;
+
+`include autosense_dittrich_inc.v
+
+ always @(/*AS*/A or B or C or D or SEL) begin
+ case (SEL)
+ sel_a: Z = A;
+ sel_b: Z = B;
+ sel_c: Z = C;
+ sel_d: Z = D;
+ default: Z = D;
+ endcase // case(SEL)
+ end // always @ (...
+
+endmodule // testcase
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests_ok/autosense_dittrich_inc.v b/tests_ok/autosense_dittrich_inc.v
new file mode 100644
index 0000000..d772144
--- /dev/null
+++ b/tests_ok/autosense_dittrich_inc.v
@@ -0,0 +1,9 @@
+parameter sel_a = {1'b 0, 1'b 0}; // 2'd 0 works fine
+parameter sel_b = {1'b 0, 1'b 1}; // 2'd 1 works fine
+parameter sel_c = 2'd 2,
+ sel_d = 2'd 3;
+
+//parameter sel_a = {1'b 0, 1'b 0}, // 2'd 0 works fine
+// sel_b = {1'b 0, 1'b 1}, // 2'd 1 works fine
+// sel_c = 2'd 2,
+// sel_d = 2'd 3;
diff --git a/tests_ok/autosense_gifford.v b/tests_ok/autosense_gifford.v
new file mode 100644
index 0000000..37ccbf8
--- /dev/null
+++ b/tests_ok/autosense_gifford.v
@@ -0,0 +1,32 @@
+module x (/*AUTOARG*/);
+
+ // Which Internal Bank
+`define DMC_AG_HADDR_BADDR_BST2_RNG 1:0 // Bank Address Range within Hexabyte Address for 2-Burst
+`define DMC_AG_HADDR_BADDR_BST4_RNG 2:1 // Bank Address Range within Hexabyte Address for 4-Burst
+`define DMC_AG_HADDR_BADDR_BST8_RNG 3:2 // Bank Address Range within Hexabyte Address for 8-Burst
+
+ reg [NumBnks-1:0] ibnk_sel_s; // Muxed internal bank address subfield of
+ command address
+ always @(/*AUTOSENSE*/lio_buscfg_brstlen2_sr or lio_buscfg_brstlen4_sr or m_cdq_haddr_sr)
+ begin : PeelIntBnkAddr
+ case ({lio_buscfg_brstlen4_sr,lio_buscfg_brstlen2_sr})
+ 2'b01: // 2-burst
+ begin
+ ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST2_RNG];
+ end
+ 2'b10: // 4-burst
+ begin
+ ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST4_RNG];
+ end
+ default: // 8-burst
+ begin
+ ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST8_RNG];
+ end
+ endcase
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests_ok/autosense_if_else.v b/tests_ok/autosense_if_else.v
new file mode 100644
index 0000000..8b52e18
--- /dev/null
+++ b/tests_ok/autosense_if_else.v
@@ -0,0 +1,13 @@
+module x;
+
+ always @ (/*AS*/a or b or c)
+ if (a) q = b;
+ else r = c;
+
+ always @ (/*AS*/a or b or c or d or e)
+ if (a) q = b;
+ else if (c) r = d;
+ /* skip comments as usual */
+ else r = e;
+
+endmodule
diff --git a/tests_ok/autosense_inandout.v b/tests_ok/autosense_inandout.v
new file mode 100644
index 0000000..acf7bc2
--- /dev/null
+++ b/tests_ok/autosense_inandout.v
@@ -0,0 +1,14 @@
+module autosense_inandout(a,b);
+
+ input a;
+ output b;
+ reg b;
+ reg c;
+
+ always @(/*AUTOSENSE*/a) begin
+ c=a;
+ b=c;
+ end
+
+endmodule
+
diff --git a/tests_ok/autosense_inc_param.v b/tests_ok/autosense_inc_param.v
new file mode 100644
index 0000000..c3483e7
--- /dev/null
+++ b/tests_ok/autosense_inc_param.v
@@ -0,0 +1,6 @@
+
+parameter [2:0] PARAM_TWO = 2,
+ PARAM_THREE = 3;
+parameter PARAM_FOUR = 4;
+
+
diff --git a/tests_ok/autosense_jbrown.v b/tests_ok/autosense_jbrown.v
new file mode 100644
index 0000000..9941ab6
--- /dev/null
+++ b/tests_ok/autosense_jbrown.v
@@ -0,0 +1,29 @@
+`define LCH_GSWDATWID 3
+`define COM_CLDATWID 2
+
+module autosense_jbrown(/*AUTOARG*/
+ // Outputs
+ lch_gswdata,
+ // Inputs
+ com_cldata
+ );
+
+ output [`LCH_GSWDATWID-1:0] lch_gswdata; // data to switch
+ input [`COM_CLDATWID-1:0] com_cldata; // data bus to clusters
+
+ /*autowire*/
+
+ reg tmp;
+`define TEST_DEFINE 1'b0
+ always @ (/*AUTOSENSE*/)
+ begin
+ /* AUTO_CONSTANT (`TEST_DEFINE) */
+ tmp <= `TEST_DEFINE; // test defines
+ end
+
+ // Local Variables:
+ // verilog-library-directories:("." "../cdp/")
+ // verilog-library-extensions:(".v" ".vh")
+ // End:
+
+endmodule
diff --git a/tests_ok/autosense_lavinge.v b/tests_ok/autosense_lavinge.v
new file mode 100644
index 0000000..6b8b572
--- /dev/null
+++ b/tests_ok/autosense_lavinge.v
@@ -0,0 +1,15 @@
+module test
+ #(parameter FOO=1)
+ ( a, b );
+ input a;
+ input b;
+
+ reg c;
+ wire d;
+
+ always @(/*AUTOSENSE*/b or d)
+ begin
+ c=0;
+ if (d) c = b;
+ end
+endmodule
diff --git a/tests_ok/autosense_mcardle_onehot.v b/tests_ok/autosense_mcardle_onehot.v
new file mode 100644
index 0000000..117ca11
--- /dev/null
+++ b/tests_ok/autosense_mcardle_onehot.v
@@ -0,0 +1,28 @@
+module x;
+
+ input [5:0] state;
+ output [5:0] next;
+
+ parameter CYCLEA = 1;
+ parameter CYCLEC = 2;
+ parameter MSTRA = 3;
+ parameter MSTRB = 4;
+ parameter MSTRC = 5;
+
+ // make sure 'state' is listed
+ always @ (/*AUTOSENSE*/done or nREQA or nREQB or nREQC or state) begin
+ next = 6'b0;
+ case (1'b1)
+ state[CYCLEC] : begin
+ if (!nREQA && done) next[MSTRA] = 1'b1;
+ else if (!nREQB && nREQA && done)next[MSTRB] = 1'b1;
+ else if (!nREQC && nREQA && nREQB && done) next[MSTRC] = 1'b1;
+ else next[CYCLEC] = 1'b1;
+ end
+ state[MSTRA] : begin
+ if (!nREQB || !nREQC) next[CYCLEA] = 1'b1;
+ else next[MSTRA] = 1'b1;
+ end
+ endcase
+ end
+endmodule
diff --git a/tests_ok/autosense_metzger_space.v b/tests_ok/autosense_metzger_space.v
new file mode 100644
index 0000000..b21037d
--- /dev/null
+++ b/tests_ok/autosense_metzger_space.v
@@ -0,0 +1,21 @@
+module x (/*AUTOARG*/
+ // Outputs
+ rmsk0, rmsk1, rmsk2,
+ // Inputs
+ endbyte0, endbyte1, endbyte2, strtbyte0, strtbyte1, strtbyte2
+ );
+ input endbyte0;
+ input endbyte1;
+ input endbyte2;
+ input strtbyte0;
+ input strtbyte1;
+ input strtbyte2;
+ output rmsk0;
+ output rmsk1;
+ output rmsk2;
+
+ always @ (/*AS*/endbyte0 or strtbyte0) rmsk0 = maskcalc(strtbyte0,endbyte0);
+ always @ (/*AS*/endbyte1 or strtbyte1) rmsk1 = maskcalc(strtbyte1,endbyte1);
+ always @ (/*AS*/endbyte2 or strtbyte2) rmsk2 = maskcalc(strtbyte2,endbyte2);
+
+endmodule
diff --git a/tests_ok/autosense_one.v b/tests_ok/autosense_one.v
new file mode 100644
index 0000000..b6cfcb0
--- /dev/null
+++ b/tests_ok/autosense_one.v
@@ -0,0 +1,2 @@
+`define one 1'b1
+
diff --git a/tests_ok/autosense_peers_func.v b/tests_ok/autosense_peers_func.v
new file mode 100644
index 0000000..9e3139a
--- /dev/null
+++ b/tests_ok/autosense_peers_func.v
@@ -0,0 +1,39 @@
+module x;
+
+ always @(/*AUTOSENSE*/arb_select_f or octet_idx) begin
+ octet_flag[0] = |arb_select_f[ 7: 0];
+ octet_flag[1] = |arb_select_f[15: 8];
+ octet_flag[2] = |arb_select_f[23:16];
+ octet_flag[3] = |arb_select_f[31:24];
+ octet_flag[4] = |arb_select_f[39:32];
+ octet_flag[5] = |arb_select_f[47:40];
+ octet_flag[6] = |arb_select_f[55:48];
+ octet_flag[7] = |arb_select_f[63:56];
+
+ octet_available = |octet_flag;
+
+ shifted8_64 = barrel_shifter(octet_flag, octet_idx[5:3]);
+ end // always @ (arb_select_f)
+
+endmodule
+
+function [7:0] barrel_shifter;
+
+ input [7:0] source;
+ input [2:0] shift_amt;
+
+ begin
+ case (shift_amt) //synopsys parallel_case full_case
+ 3'b0: barrel_shifter = source;
+ 3'b1: barrel_shifter = {source[0], source[7:1]};
+ 3'b2: barrel_shifter = {source[1:0], source[7:2]};
+ 3'b3: barrel_shifter = {source[2:0], source[7:3]};
+ 3'b4: barrel_shifter = {source[3:0], source[7:4]};
+ 3'b5: barrel_shifter = {source[4:0], source[7:5]};
+ 3'b6: barrel_shifter = {source[5:0], source[7:6]};
+ 3'b7: barrel_shifter = {source[6:0], source[7]};
+ endcase // case(shift_amt)
+ end
+
+endfunction // barrel_shifter
+
diff --git a/tests_ok/autosense_rogoff.v b/tests_ok/autosense_rogoff.v
new file mode 100644
index 0000000..e2647d8
--- /dev/null
+++ b/tests_ok/autosense_rogoff.v
@@ -0,0 +1,10 @@
+
+module x;
+ always @ (/*as*/a or ff)
+ case (a)
+ 1: if (ff[3:0] == 4'd3)
+ sadfsdff;
+ endcase
+
+
+endmodule
diff --git a/tests_ok/autosense_smith.v b/tests_ok/autosense_smith.v
new file mode 100644
index 0000000..d516a65
--- /dev/null
+++ b/tests_ok/autosense_smith.v
@@ -0,0 +1,56 @@
+module x;
+
+ reg [31:0] mb_reg_output;
+
+ // 16 registers max, register 15 is always the version number, so 15 are useable
+ // NOTE: number_interface_regs must be the maximum (or 16 in this case) to get the version register
+ parameter NUMBER_INTERFACE_REGS = 16;
+ parameter MB_REG_START = 3; // start at 4th register location 'h0010
+ parameter CMD_REG_0_ADDR = MB_REG_START;
+ parameter CMD_REG_1_ADDR = MB_REG_START+1;
+ parameter CMD_REG_2_ADDR = MB_REG_START+2;
+ parameter CMD_REG_3_ADDR = MB_REG_START+3;
+ parameter CMD_REG_4_ADDR = MB_REG_START+4;
+ parameter CMD_REG_5_ADDR = MB_REG_START+5;
+ parameter CMD_REG_6_ADDR = MB_REG_START+6;
+ parameter CMD_REG_7_ADDR = MB_REG_START+7;
+ parameter CMD_REG_8_ADDR = MB_REG_START+8;
+ parameter CMD_REG_9_ADDR = MB_REG_START+9;
+ parameter CMD_REG_10_ADDR = MB_REG_START+10;
+ // mode regs
+ parameter MODE_REG_0_ADDR = CMD_REG_8_ADDR;
+
+ // Absolute register 14 is Error counter
+ parameter CMD_REG_14_ADDR = 14;
+ parameter CRC_ERROR_REG_ADDR = CMD_REG_14_ADDR;
+ // ------------ VERSION register is 15
+ parameter VERSION_REG_ADDR = 15;
+
+ reg [NUMBER_INTERFACE_REGS-1:MB_REG_START] mb_reg_wr;
+ reg [NUMBER_INTERFACE_REGS-1:MB_REG_START] mb_reg_rd;
+ wire [31:0] mb_reg_out_w [NUMBER_INTERFACE_REGS-1:MB_REG_START];
+ wire [31:0] interface_from_core_fp;
+
+ assign
+ mb_reg_out_w[VERSION_REG_ADDR] = BUILD_VERSION;
+
+ integer mb_loop;
+ always @(/*AUTOSENSE*/ /*memory or*/ interface_from_core_fp or mb_reg_rwn or mb_reg_select)
+
+ begin: MB_READ_WRITE_SEL_P
+
+ mb_reg_wr = 'h0;
+ mb_reg_rd = 'h0;
+ mb_reg_output = interface_from_core_fp;
+
+ for(mb_loop = MB_REG_START; mb_loop < NUMBER_INTERFACE_REGS; mb_loop=mb_loop+1)
+ begin
+ if(mb_reg_select[mb_loop] == 1'b1)
+ begin
+ mb_reg_rd[mb_loop] = mb_reg_select[mb_loop] & mb_reg_rwn;
+ mb_reg_wr[mb_loop] = mb_reg_select[mb_loop] & !mb_reg_rwn;
+ mb_reg_output = mb_reg_out_w[mb_loop];
+ end
+ end
+ end
+endmodule // x
diff --git a/tests_ok/autosense_venkataramanan_begin.v b/tests_ok/autosense_venkataramanan_begin.v
new file mode 100644
index 0000000..572455d
--- /dev/null
+++ b/tests_ok/autosense_venkataramanan_begin.v
@@ -0,0 +1,18 @@
+
+module autosense_venkataramanan_begin(/*AUTOARG*/);
+
+ reg a,b;
+
+ always @(/*AUTOSENSE*/b) // I didn't expect to get "i" in AUTOSENSE
+ begin : label
+ integer i, j;
+ for (i=0; i< = 3; i = i + 1)
+ vec[i] = b;
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-sense-defines-constant: t
+// verilog-auto-sense-include-inputs: t
+// End:
diff --git a/tests_ok/autotieoff_assign.v b/tests_ok/autotieoff_assign.v
new file mode 100644
index 0000000..09fbea4
--- /dev/null
+++ b/tests_ok/autotieoff_assign.v
@@ -0,0 +1,28 @@
+module autotieoff_signed (/*AUTOARG*/
+ // Outputs
+ ExtraOut, SubOut, active_low_l, ignored_by_regexp
+ );
+
+ output [2:0] ExtraOut;
+ output [2:0] SubOut;
+ output [3:0] active_low_l;
+ output [3:0] ignored_by_regexp;
+
+ /*AUTOTIEOFF*/
+ // Beginning of automatic tieoffs (for this module's unterminated outputs)
+ assign ExtraOut = 3'h0;
+ assign SubOut = 3'h0;
+ assign active_low_l = 4'h0;
+ assign ignored_by_regexp = 4'h0;
+ // End of automatics
+
+endmodule
+
+module sub;
+ input SubIn;
+ output SubOut;
+endmodule
+
+// Local Variables:
+// verilog-auto-tieoff-declaration: "assign"
+// End:
diff --git a/tests_ok/autotieoff_signed.v b/tests_ok/autotieoff_signed.v
new file mode 100644
index 0000000..d76f619
--- /dev/null
+++ b/tests_ok/autotieoff_signed.v
@@ -0,0 +1,79 @@
+module autotieoff_signed (/*AUTOARG*/
+ // Outputs
+ an_output2, an_outputpre, another_output, another_output2, ExtraOut, SubOut, active_low_l,
+ ignored_by_regexp,
+ // Inputs
+ ExtraIn, SubIn
+ );
+
+ input [2:0] ExtraIn;
+ input [2:0] SubIn;
+ output [2:0] ExtraOut;
+ output [2:0] SubOut;
+ output [3:0] active_low_l;
+ output [3:0] ignored_by_regexp;
+
+ /*AUTOINOUTMODULE("autoinst_signed")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output [1:0] an_output2;
+ output signed [1:0] an_outputpre;
+ output signed [1:0] another_output;
+ output [1:0] another_output2;
+ // End of automatics
+
+ // =============================
+ // Auto Wires/Regs
+ // =============================
+
+ /*AUTOWIRE*/
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg [3:0] ignored_by_regexp;
+ // End of automatics
+
+ // =============================
+ // Tieoffs
+ // =============================
+
+ /*AUTOTIEOFF*/
+ // Beginning of automatic tieoffs (for this module's unterminated outputs)
+ wire [2:0] ExtraOut = 3'h0;
+ wire [3:0] active_low_l = ~4'h0;
+ wire [1:0] an_output2 = 2'h0;
+ wire signed [1:0] an_outputpre = 2'sh0;
+ wire signed [1:0] another_output = 2'sh0;
+ wire [1:0] another_output2 = 2'h0;
+ // End of automatics
+
+ // =============================
+
+ sub sub (/*AUTOINST*/
+ // Outputs
+ .SubOut (SubOut),
+ // Inputs
+ .SubIn (SubIn));
+
+ // =============================
+ // Unused signals
+ // =============================
+
+ // lint_checking SCX_UNUSED OFF
+ wire _unused_ok = &{1'b0,
+ /*AUTOUNUSED*/
+ // Beginning of automatic unused inputs
+ ExtraIn,
+ // End of automatics
+ 1'b0 } ;
+ // lint_checking SCX_UNUSED OFF
+
+endmodule
+
+module sub;
+ input SubIn;
+ output SubOut;
+endmodule
+
+// Local Variables:
+// verilog-active-low-regexp: "_l$"
+// verilog-auto-tieoff-ignore-regexp: "ignored"
+// End:
diff --git a/tests_ok/autoundef.v b/tests_ok/autoundef.v
new file mode 100644
index 0000000..c5f5dcd
--- /dev/null
+++ b/tests_ok/autoundef.v
@@ -0,0 +1,36 @@
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+module temp;
+
+`define FOO(a)
+`define BAR
+`define BAZ
+
+ .....
+
+`undef BAR
+`define BAR
+`define BAZ // AGAIN
+
+ /*AUTOUNDEF*/
+ // Beginning of automatic undefs
+`undef BAR
+`undef BAZ
+`undef FOO
+ // End of automatics
+
+ // Make sure this list is empty
+ /*AUTOUNDEF*/
+
+ //======================================================================
+
+`define M_A
+`define X_B
+
+ /*AUTOUNDEF("^M_")*/
+ // Beginning of automatic undefs
+`undef M_A
+ // End of automatics
+
+ endmodule
diff --git a/tests_ok/autounused.v b/tests_ok/autounused.v
new file mode 100644
index 0000000..04e9d45
--- /dev/null
+++ b/tests_ok/autounused.v
@@ -0,0 +1,41 @@
+module wbuf
+ #(parameter width=1)
+ (output [width-1:0] q,
+ input [width-1:0] d);
+endmodule
+
+module autounused
+ #(parameter width=3)
+ (/*AUTOARG*/
+ // Outputs
+ q,
+ // Inputs
+ da, db, dc, dd
+ ) ;
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [width-1:0] q; // From wbuf of wbuf.v
+ // End of automatics
+ input da, db, dc, dd;
+ /*AUTOINPUT*/
+
+ wire _unused_ok = &{/*AUTOUNUSED*/
+ // Beginning of automatic unused inputs
+ dd,
+ // End of automatics
+ 1'b0};
+
+ defparam partbuf.width = width;
+ wbuf wbuf
+ (// Inputs
+ .d ({da,db,dc}),
+ /*AUTOINST*/
+ // Outputs
+ .q (q[width-1:0]));
+
+endmodule // abuf
+
+// Local Variables:
+// verilog-auto-unused-ignore-regexp: "^db$"
+// End:
diff --git a/tests_ok/autowire_godiwala.v b/tests_ok/autowire_godiwala.v
new file mode 100644
index 0000000..2daed7b
--- /dev/null
+++ b/tests_ok/autowire_godiwala.v
@@ -0,0 +1,580 @@
+module FswArbiter (/*AUTOARG*/
+ // Outputs
+ xb_ecc_error_dbit, xb_ecc_error_1bit, insert_idle_ack, bp_performance_count, obx_xb0_GntPst_s3a,
+ obx_xb0_GntByp_s3a, obx_xb1_GntPst_s3a, obx_xb1_GntByp_s3a, obx_xb2_GntPst_s3a,
+ obx_xb2_GntByp_s3a, obx_xb3_GntPst_s3a, obx_xb3_GntByp_s3a, xbx_grant_cycle, bp1_grant_cycle,
+ set_arbitration_enable_d1, reset_ackbuf, wait_for_ack, ice9_databus,
+ // Inputs
+ sclk, lreset_l, csr_insert_idle, csr_arb_enable, csr_bypass3_enable, csr_bypass2_enable,
+ csr_bypass1_enable, csr_xb_ecc_enable, xb0_obx_ReqPst_s2a, xb0_obx_NextVc_s2a,
+ xb0_obx_NextPort_s2a, xb0_obx_NextXbe_s2a, xb0_obx_NextXbe_s3a, xb0_obx_OutDat_s4a,
+ xb0_obx_ReqBypS3_s2a, xb0_obx_ReqBypS2_s2a, xb1_obx_ReqPst_s2a, xb1_obx_NextVc_s2a,
+ xb1_obx_NextPort_s2a, xb1_obx_NextXbe_s2a, xb1_obx_NextXbe_s3a, xb1_obx_OutDat_s4a,
+ xb1_obx_ReqBypS3_s2a, xb1_obx_ReqBypS2_s2a, xb2_obx_ReqPst_s2a, xb2_obx_NextVc_s2a,
+ xb2_obx_NextPort_s2a, xb2_obx_NextXbe_s2a, xb2_obx_NextXbe_s3a, xb2_obx_OutDat_s4a,
+ xb2_obx_ReqBypS3_s2a, xb2_obx_ReqBypS2_s2a, xb3_obx_ReqPst_s2a, xb3_obx_NextVc_s2a,
+ xb3_obx_NextPort_s2a, xb3_obx_NextXbe_s2a, xb3_obx_NextXbe_s3a, xb3_obx_OutDat_s4a,
+ xb3_obx_ReqBypS3_s2a, xb3_obx_ReqBypS2_s2a, ib0_obx_PortSel_s1a, ib0_obx_InDat_s1a,
+ ib0_obx_NextPort_s1a, ib0_obx_NextVc_s1a, ib1_obx_PortSel_s1a, ib1_obx_InDat_s1a,
+ ib1_obx_NextPort_s1a, ib1_obx_NextVc_s1a, ib2_obx_PortSel_s1a, ib2_obx_InDat_s1a,
+ ib2_obx_NextPort_s1a, ib2_obx_NextVc_s1a, ib3_obx_PortSel_s1a, ib3_obx_InDat_s1a,
+ ib3_obx_NextPort_s1a, ib3_obx_NextVc_s1a, rp_is_full, rp_in_progress, rp_arb_poolmask,
+ rp_arb_bufbusy_mask
+ ) ;
+
+
+ // ========================
+ // Include parameter File
+ // ========================
+ parameter DMAO = 0;
+
+`include "chip_fsw_spec_param.v"
+
+ // ===============
+ // Physical Pins
+ // ===============
+
+ input sclk; // Fabric switch clock
+ input lreset_l;
+
+ input csr_insert_idle;
+ input csr_arb_enable;
+
+ input [3:0] csr_bypass3_enable;
+ input [3:0] csr_bypass2_enable;
+ input [3:0] csr_bypass1_enable;
+
+ input csr_xb_ecc_enable;
+
+ output [3:0] xb_ecc_error_dbit;
+ output [3:0] xb_ecc_error_1bit;
+
+ output insert_idle_ack;
+
+ output [2:0] bp_performance_count;
+
+ input xb0_obx_ReqPst_s2a;
+ input [3:0] xb0_obx_NextVc_s2a;
+ input [1:0] xb0_obx_NextPort_s2a;
+ input [3:0] xb0_obx_NextXbe_s2a;
+ input [3:0] xb0_obx_NextXbe_s3a;
+ input [71:0] xb0_obx_OutDat_s4a;
+
+ output obx_xb0_GntPst_s3a;
+ output obx_xb0_GntByp_s3a;
+
+ input xb0_obx_ReqBypS3_s2a;
+ input xb0_obx_ReqBypS2_s2a;
+
+ input xb1_obx_ReqPst_s2a;
+ input [3:0] xb1_obx_NextVc_s2a;
+ input [1:0] xb1_obx_NextPort_s2a;
+ input [3:0] xb1_obx_NextXbe_s2a;
+ input [3:0] xb1_obx_NextXbe_s3a;
+ input [71:0] xb1_obx_OutDat_s4a;
+
+ output obx_xb1_GntPst_s3a;
+ output obx_xb1_GntByp_s3a;
+
+ input xb1_obx_ReqBypS3_s2a;
+ input xb1_obx_ReqBypS2_s2a;
+
+ input xb2_obx_ReqPst_s2a;
+ input [3:0] xb2_obx_NextVc_s2a;
+ input [1:0] xb2_obx_NextPort_s2a;
+ input [3:0] xb2_obx_NextXbe_s2a;
+ input [3:0] xb2_obx_NextXbe_s3a;
+ input [71:0] xb2_obx_OutDat_s4a;
+
+ output obx_xb2_GntPst_s3a;
+ output obx_xb2_GntByp_s3a;
+
+ input xb2_obx_ReqBypS3_s2a;
+ input xb2_obx_ReqBypS2_s2a;
+
+ input xb3_obx_ReqPst_s2a;
+ input [3:0] xb3_obx_NextVc_s2a;
+ input [1:0] xb3_obx_NextPort_s2a;
+ input [3:0] xb3_obx_NextXbe_s2a;
+ input [3:0] xb3_obx_NextXbe_s3a;
+ input [71:0] xb3_obx_OutDat_s4a;
+
+ output obx_xb3_GntPst_s3a;
+ output obx_xb3_GntByp_s3a;
+
+ input xb3_obx_ReqBypS3_s2a;
+ input xb3_obx_ReqBypS2_s2a;
+
+ input ib0_obx_PortSel_s1a;
+ input [63:0] ib0_obx_InDat_s1a;
+ input [1:0] ib0_obx_NextPort_s1a;
+ input [3:0] ib0_obx_NextVc_s1a;
+
+ input ib1_obx_PortSel_s1a;
+ input [63:0] ib1_obx_InDat_s1a;
+ input [1:0] ib1_obx_NextPort_s1a;
+ input [3:0] ib1_obx_NextVc_s1a;
+
+ input ib2_obx_PortSel_s1a;
+ input [63:0] ib2_obx_InDat_s1a;
+ input [1:0] ib2_obx_NextPort_s1a;
+ input [3:0] ib2_obx_NextVc_s1a;
+
+ input ib3_obx_PortSel_s1a;
+ input [63:0] ib3_obx_InDat_s1a;
+ input [1:0] ib3_obx_NextPort_s1a;
+ input [3:0] ib3_obx_NextVc_s1a;
+
+ input rp_is_full;
+ input rp_in_progress;
+
+ input [15:0] rp_arb_poolmask;
+ input [63:0] rp_arb_bufbusy_mask;
+
+ output xbx_grant_cycle;
+ output bp1_grant_cycle;
+ output set_arbitration_enable_d1;
+
+ output [63:0] reset_ackbuf;
+ output [63:0] wait_for_ack;
+
+ output [63:0] ice9_databus;
+
+ // =============================
+ // Auto Wires/Regs
+ // =============================
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire bp1_grant0; // From bp1 of FswBypassArbiter.v
+ wire bp1_grant1; // From bp1 of FswBypassArbiter.v
+ wire bp1_grant2; // From bp1 of FswBypassArbiter.v
+ wire bp1_grant3; // From bp1 of FswBypassArbiter.v
+ wire bp1_grant_cycle_d1; // From bp1 of FswBypassArbiter.v
+ wire bp1_grant_cycle_d2; // From bp1 of FswBypassArbiter.v
+ wire bp1_header; // From bp1 of FswBypassArbiter.v
+ wire bp1_header_d1; // From bp1 of FswBypassArbiter.v
+ wire bp1_header_d2; // From bp1 of FswBypassArbiter.v
+ wire [5:0] bp1_hold_wait_vector; // From bp1 of FswBypassArbiter.v
+ wire [5:0] bp1_hold_wait_vector_d1;// From bp1 of FswBypassArbiter.v
+ wire [1:0] bp1_next_winner; // From bp1 of FswBypassArbiter.v
+ wire [1:0] bp1_next_winner_d1; // From bp1 of FswBypassArbiter.v
+ wire [1:0] bp1_next_winner_d2; // From bp1 of FswBypassArbiter.v
+ wire [3:0] bp1_nextxbe; // From bp1 of FswBypassArbiter.v
+ wire [3:0] bp1_nextxbe_d1; // From bp1 of FswBypassArbiter.v
+ wire [3:0] bp1_nextxbe_d2; // From bp1 of FswBypassArbiter.v
+ wire bp1_select; // From bp1 of FswBypassArbiter.v
+ wire bp1_select_d1; // From bp1 of FswBypassArbiter.v
+ wire bp1_select_d2; // From bp1 of FswBypassArbiter.v
+ wire bp2_grant0; // From bp2 of FswBypassArbiter.v
+ wire bp2_grant1; // From bp2 of FswBypassArbiter.v
+ wire bp2_grant2; // From bp2 of FswBypassArbiter.v
+ wire bp2_grant3; // From bp2 of FswBypassArbiter.v
+ wire bp2_grant_cycle; // From bp2 of FswBypassArbiter.v
+ wire bp2_grant_cycle_d1; // From bp2 of FswBypassArbiter.v
+ wire bp2_grant_cycle_d2; // From bp2 of FswBypassArbiter.v
+ wire bp2_header; // From bp2 of FswBypassArbiter.v
+ wire bp2_header_d1; // From bp2 of FswBypassArbiter.v
+ wire bp2_header_d2; // From bp2 of FswBypassArbiter.v
+ wire [5:0] bp2_hold_wait_vector; // From bp2 of FswBypassArbiter.v
+ wire [5:0] bp2_hold_wait_vector_d1;// From bp2 of FswBypassArbiter.v
+ wire [1:0] bp2_next_winner; // From bp2 of FswBypassArbiter.v
+ wire [1:0] bp2_next_winner_d1; // From bp2 of FswBypassArbiter.v
+ wire [1:0] bp2_next_winner_d2; // From bp2 of FswBypassArbiter.v
+ wire [3:0] bp2_nextxbe; // From bp2 of FswBypassArbiter.v
+ wire [3:0] bp2_nextxbe_d1; // From bp2 of FswBypassArbiter.v
+ wire [3:0] bp2_nextxbe_d2; // From bp2 of FswBypassArbiter.v
+ wire bp2_select; // From bp2 of FswBypassArbiter.v
+ wire bp2_select_d1; // From bp2 of FswBypassArbiter.v
+ wire bp2_select_d2; // From bp2 of FswBypassArbiter.v
+ wire bp3_grant0; // From bp3 of FswBypassArbiter.v
+ wire bp3_grant1; // From bp3 of FswBypassArbiter.v
+ wire bp3_grant2; // From bp3 of FswBypassArbiter.v
+ wire bp3_grant3; // From bp3 of FswBypassArbiter.v
+ wire bp3_grant_cycle; // From bp3 of FswBypassArbiter.v
+ wire bp3_grant_cycle_d1; // From bp3 of FswBypassArbiter.v
+ wire bp3_grant_cycle_d2; // From bp3 of FswBypassArbiter.v
+ wire bp3_header; // From bp3 of FswBypassArbiter.v
+ wire bp3_header_d1; // From bp3 of FswBypassArbiter.v
+ wire bp3_header_d2; // From bp3 of FswBypassArbiter.v
+ wire [5:0] bp3_hold_wait_vector; // From bp3 of FswBypassArbiter.v
+ wire [5:0] bp3_hold_wait_vector_d1;// From bp3 of FswBypassArbiter.v
+ wire [1:0] bp3_next_winner; // From bp3 of FswBypassArbiter.v
+ wire [1:0] bp3_next_winner_d1; // From bp3 of FswBypassArbiter.v
+ wire [1:0] bp3_next_winner_d2; // From bp3 of FswBypassArbiter.v
+ wire [3:0] bp3_nextxbe; // From bp3 of FswBypassArbiter.v
+ wire [3:0] bp3_nextxbe_d1; // From bp3 of FswBypassArbiter.v
+ wire [3:0] bp3_nextxbe_d2; // From bp3 of FswBypassArbiter.v
+ wire bp3_select; // From bp3 of FswBypassArbiter.v
+ wire bp3_select_d1; // From bp3 of FswBypassArbiter.v
+ wire bp3_select_d2; // From bp3 of FswBypassArbiter.v
+ // End of automatics
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg [2:0] bp_performance_count;
+ reg [63:0] ice9_databus;
+ reg insert_idle_ack;
+ reg obx_xb0_GntByp_s3a;
+ reg obx_xb0_GntPst_s3a;
+ reg obx_xb1_GntByp_s3a;
+ reg obx_xb1_GntPst_s3a;
+ reg obx_xb2_GntByp_s3a;
+ reg obx_xb2_GntPst_s3a;
+ reg obx_xb3_GntByp_s3a;
+ reg obx_xb3_GntPst_s3a;
+ reg [63:0] reset_ackbuf;
+ reg set_arbitration_enable_d1;
+ reg [63:0] wait_for_ack;
+ reg [3:0] xb_ecc_error_1bit;
+ reg [3:0] xb_ecc_error_dbit;
+ reg xbx_grant_cycle;
+ // End of automatics
+
+ /* FswBypassArbiter AUTO_TEMPLATE (
+ // Outputs
+ .bp_grant3 (bp@_grant3),
+ .bp_grant2 (bp@_grant2),
+ .bp_grant1 (bp@_grant1),
+ .bp_grant0 (bp@_grant0),
+ .bp_grant_cycle (bp@_grant_cycle),
+ .bp_grant_cycle_d1 (bp@_grant_cycle_d1),
+ .bp_grant_cycle_d2 (bp@_grant_cycle_d2),
+ .bp_next_winner (bp@_next_winner[1:0]),
+ .bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
+ .bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
+ .bp_nextxbe (bp@_nextxbe[3:0]),
+ .bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
+ .bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
+ .bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
+ .bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
+ .bp_select (bp@_select),
+ .bp_select_d1 (bp@_select_d1),
+ .bp_select_d2 (bp@_select_d2),
+ .bp_header (bp@_header),
+ .bp_header_d1 (bp@_header_d1),
+ .bp_header_d2 (bp@_header_d2),
+ // Inputs
+ .lreset_l (bp@_lreset_l),
+ .bp_arb_enable (bp@_arb_enable),
+ .sop3 (sop3 & xbx_bp3_enable_3),
+ .sop2 (sop2 & xbx_bp3_enable_2),
+ .sop1 (sop1 & xbx_bp3_enable_1),
+ .sop0 (sop0 & xbx_bp3_enable_0),
+ ); */
+
+
+ FswBypassArbiter bp3 (/*AUTOINST*/
+ // Outputs
+ .bp_grant3 (bp3_grant3), // Templated
+ .bp_grant2 (bp3_grant2), // Templated
+ .bp_grant1 (bp3_grant1), // Templated
+ .bp_grant0 (bp3_grant0), // Templated
+ .bp_grant_cycle (bp3_grant_cycle), // Templated
+ .bp_grant_cycle_d1 (bp3_grant_cycle_d1), // Templated
+ .bp_grant_cycle_d2 (bp3_grant_cycle_d2), // Templated
+ .bp_next_winner (bp3_next_winner[1:0]), // Templated
+ .bp_next_winner_d1 (bp3_next_winner_d1[1:0]), // Templated
+ .bp_next_winner_d2 (bp3_next_winner_d2[1:0]), // Templated
+ .bp_nextxbe (bp3_nextxbe[3:0]), // Templated
+ .bp_nextxbe_d1 (bp3_nextxbe_d1[3:0]), // Templated
+ .bp_nextxbe_d2 (bp3_nextxbe_d2[3:0]), // Templated
+ .bp_hold_wait_vector (bp3_hold_wait_vector[5:0]), // Templated
+ .bp_hold_wait_vector_d1(bp3_hold_wait_vector_d1[5:0]), // Templated
+ .bp_header (bp3_header), // Templated
+ .bp_header_d1 (bp3_header_d1), // Templated
+ .bp_header_d2 (bp3_header_d2), // Templated
+ .bp_select (bp3_select), // Templated
+ .bp_select_d1 (bp3_select_d1), // Templated
+ .bp_select_d2 (bp3_select_d2), // Templated
+ // Inputs
+ .lreset_l (bp3_lreset_l), // Templated
+ .sclk (sclk),
+ .bp_arb_enable (bp3_arb_enable), // Templated
+ .sop3 (sop3 & xbx_bp3_enable_3), // Templated
+ .sop3_data (sop3_data[63:0]),
+ .sop3_bpcontext (sop3_bpcontext[5:0]),
+ .sop2 (sop2 & xbx_bp3_enable_2), // Templated
+ .sop2_data (sop2_data[63:0]),
+ .sop2_bpcontext (sop2_bpcontext[5:0]),
+ .sop1 (sop1 & xbx_bp3_enable_1), // Templated
+ .sop1_data (sop1_data[63:0]),
+ .sop1_bpcontext (sop1_bpcontext[5:0]),
+ .sop0 (sop0 & xbx_bp3_enable_0), // Templated
+ .sop0_data (sop0_data[63:0]),
+ .sop0_bpcontext (sop0_bpcontext[5:0]),
+ .poolmask (poolmask[15:0]),
+ .bufbusy_mask (bufbusy_mask[63:0]));
+
+
+ /* FswBypassArbiter AUTO_TEMPLATE (
+ // Outputs
+ .bp_grant3 (bp@_grant3),
+ .bp_grant2 (bp@_grant2),
+ .bp_grant1 (bp@_grant1),
+ .bp_grant0 (bp@_grant0),
+ .bp_grant_cycle (bp@_grant_cycle),
+ .bp_grant_cycle_d1 (bp@_grant_cycle_d1),
+ .bp_grant_cycle_d2 (bp@_grant_cycle_d2),
+ .bp_next_winner (bp@_next_winner[1:0]),
+ .bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
+ .bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
+ .bp_nextxbe (bp@_nextxbe[3:0]),
+ .bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
+ .bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
+ .bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
+ .bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
+ .bp_select (bp@_select),
+ .bp_select_d1 (bp@_select_d1),
+ .bp_select_d2 (bp@_select_d2),
+ .bp_header (bp@_header),
+ .bp_header_d1 (bp@_header_d1),
+ .bp_header_d2 (bp@_header_d2),
+ // Inputs
+ .lreset_l (bp@_lreset_l),
+ .bp_arb_enable (bp@_arb_enable),
+ .sop3 (sop3 & xbx_bp2_enable_3),
+ .sop2 (sop2 & xbx_bp2_enable_2),
+ .sop1 (sop1 & xbx_bp2_enable_1),
+ .sop0 (sop0 & xbx_bp2_enable_0),
+ ); */
+
+
+ FswBypassArbiter bp2 (/*AUTOINST*/
+ // Outputs
+ .bp_grant3 (bp2_grant3), // Templated
+ .bp_grant2 (bp2_grant2), // Templated
+ .bp_grant1 (bp2_grant1), // Templated
+ .bp_grant0 (bp2_grant0), // Templated
+ .bp_grant_cycle (bp2_grant_cycle), // Templated
+ .bp_grant_cycle_d1 (bp2_grant_cycle_d1), // Templated
+ .bp_grant_cycle_d2 (bp2_grant_cycle_d2), // Templated
+ .bp_next_winner (bp2_next_winner[1:0]), // Templated
+ .bp_next_winner_d1 (bp2_next_winner_d1[1:0]), // Templated
+ .bp_next_winner_d2 (bp2_next_winner_d2[1:0]), // Templated
+ .bp_nextxbe (bp2_nextxbe[3:0]), // Templated
+ .bp_nextxbe_d1 (bp2_nextxbe_d1[3:0]), // Templated
+ .bp_nextxbe_d2 (bp2_nextxbe_d2[3:0]), // Templated
+ .bp_hold_wait_vector (bp2_hold_wait_vector[5:0]), // Templated
+ .bp_hold_wait_vector_d1(bp2_hold_wait_vector_d1[5:0]), // Templated
+ .bp_header (bp2_header), // Templated
+ .bp_header_d1 (bp2_header_d1), // Templated
+ .bp_header_d2 (bp2_header_d2), // Templated
+ .bp_select (bp2_select), // Templated
+ .bp_select_d1 (bp2_select_d1), // Templated
+ .bp_select_d2 (bp2_select_d2), // Templated
+ // Inputs
+ .lreset_l (bp2_lreset_l), // Templated
+ .sclk (sclk),
+ .bp_arb_enable (bp2_arb_enable), // Templated
+ .sop3 (sop3 & xbx_bp2_enable_3), // Templated
+ .sop3_data (sop3_data[63:0]),
+ .sop3_bpcontext (sop3_bpcontext[5:0]),
+ .sop2 (sop2 & xbx_bp2_enable_2), // Templated
+ .sop2_data (sop2_data[63:0]),
+ .sop2_bpcontext (sop2_bpcontext[5:0]),
+ .sop1 (sop1 & xbx_bp2_enable_1), // Templated
+ .sop1_data (sop1_data[63:0]),
+ .sop1_bpcontext (sop1_bpcontext[5:0]),
+ .sop0 (sop0 & xbx_bp2_enable_0), // Templated
+ .sop0_data (sop0_data[63:0]),
+ .sop0_bpcontext (sop0_bpcontext[5:0]),
+ .poolmask (poolmask[15:0]),
+ .bufbusy_mask (bufbusy_mask[63:0]));
+
+
+ /* FswBypassArbiter AUTO_TEMPLATE (
+ // Outputs
+ .bp_grant3 (bp@_grant3),
+ .bp_grant2 (bp@_grant2),
+ .bp_grant1 (bp@_grant1),
+ .bp_grant0 (bp@_grant0),
+ .bp_grant_cycle (bp@_grant_cycle),
+ .bp_grant_cycle_d1 (bp@_grant_cycle_d1),
+ .bp_grant_cycle_d2 (bp@_grant_cycle_d2),
+ .bp_next_winner (bp@_next_winner[1:0]),
+ .bp_next_winner_d1 (bp@_next_winner_d1[1:0]),
+ .bp_next_winner_d2 (bp@_next_winner_d2[1:0]),
+ .bp_nextxbe (bp@_nextxbe[3:0]),
+ .bp_nextxbe_d1 (bp@_nextxbe_d1[3:0]),
+ .bp_nextxbe_d2 (bp@_nextxbe_d2[3:0]),
+ .bp_hold_wait_vector (bp@_hold_wait_vector[5:0]),
+ .bp_hold_wait_vector_d1 (bp@_hold_wait_vector_d1[5:0]),
+ .bp_select (bp@_select),
+ .bp_select_d1 (bp@_select_d1),
+ .bp_select_d2 (bp@_select_d2),
+ .bp_header (bp@_header),
+ .bp_header_d1 (bp@_header_d1),
+ .bp_header_d2 (bp@_header_d2),
+ // Inputs
+ .lreset_l (bp@_lreset_l),
+ .bp_arb_enable (bp@_arb_enable),
+ .sop3 (sop3 & csr_bp1_enable_3),
+ .sop2 (sop2 & csr_bp1_enable_2),
+ .sop1 (sop1 & csr_bp1_enable_1),
+ .sop0 (sop0 & csr_bp1_enable_0),
+ ); */
+
+
+ FswBypassArbiter bp1 (/*AUTOINST*/
+ // Outputs
+ .bp_grant3 (bp1_grant3), // Templated
+ .bp_grant2 (bp1_grant2), // Templated
+ .bp_grant1 (bp1_grant1), // Templated
+ .bp_grant0 (bp1_grant0), // Templated
+ .bp_grant_cycle (bp1_grant_cycle), // Templated
+ .bp_grant_cycle_d1 (bp1_grant_cycle_d1), // Templated
+ .bp_grant_cycle_d2 (bp1_grant_cycle_d2), // Templated
+ .bp_next_winner (bp1_next_winner[1:0]), // Templated
+ .bp_next_winner_d1 (bp1_next_winner_d1[1:0]), // Templated
+ .bp_next_winner_d2 (bp1_next_winner_d2[1:0]), // Templated
+ .bp_nextxbe (bp1_nextxbe[3:0]), // Templated
+ .bp_nextxbe_d1 (bp1_nextxbe_d1[3:0]), // Templated
+ .bp_nextxbe_d2 (bp1_nextxbe_d2[3:0]), // Templated
+ .bp_hold_wait_vector (bp1_hold_wait_vector[5:0]), // Templated
+ .bp_hold_wait_vector_d1(bp1_hold_wait_vector_d1[5:0]), // Templated
+ .bp_header (bp1_header), // Templated
+ .bp_header_d1 (bp1_header_d1), // Templated
+ .bp_header_d2 (bp1_header_d2), // Templated
+ .bp_select (bp1_select), // Templated
+ .bp_select_d1 (bp1_select_d1), // Templated
+ .bp_select_d2 (bp1_select_d2), // Templated
+ // Inputs
+ .lreset_l (bp1_lreset_l), // Templated
+ .sclk (sclk),
+ .bp_arb_enable (bp1_arb_enable), // Templated
+ .sop3 (sop3 & csr_bp1_enable_3), // Templated
+ .sop3_data (sop3_data[63:0]),
+ .sop3_bpcontext (sop3_bpcontext[5:0]),
+ .sop2 (sop2 & csr_bp1_enable_2), // Templated
+ .sop2_data (sop2_data[63:0]),
+ .sop2_bpcontext (sop2_bpcontext[5:0]),
+ .sop1 (sop1 & csr_bp1_enable_1), // Templated
+ .sop1_data (sop1_data[63:0]),
+ .sop1_bpcontext (sop1_bpcontext[5:0]),
+ .sop0 (sop0 & csr_bp1_enable_0), // Templated
+ .sop0_data (sop0_data[63:0]),
+ .sop0_bpcontext (sop0_bpcontext[5:0]),
+ .poolmask (poolmask[15:0]),
+ .bufbusy_mask (bufbusy_mask[63:0]));
+
+
+ // =======================================
+ // Coverage
+ // =======================================
+
+ // psl default clock = negedge sclk;
+ generate if (DMAO == 0)
+ begin
+ // psl cover {lreset_l & (bp1_grant0 |bp1_grant1 |bp1_grant2 |bp1_grant3 )} report "FswPerfRtl::byp1Taken";
+ // psl cover {lreset_l & (bp2_grant0 |bp2_grant1 |bp2_grant2 |bp2_grant3)} report "FswPerfRtl::byp2Taken";
+ // psl cover {lreset_l & (bp3_grant0 |bp3_grant1 |bp3_grant2 |bp3_grant3)} report "FswPerfRtl::byp3Taken";
+ end
+ endgenerate
+
+ // ================
+ // Unused signals
+ // ================
+
+ // lint_checking SCX_UNUSED off
+ wire _unused_ok = &{1'b0,
+
+ bp_select,
+
+ bp3_hold_wait_vector,
+ bp2_hold_wait_vector_d1,
+ bp1_hold_wait_vector_d1,
+
+ bp3_header,
+ bp3_header_d1,
+ bp3_select,
+ bp3_select_d1,
+ bp3_next_winner[1:0],
+ bp3_next_winner_d1[1:0],
+ bp3_nextxbe[3:0],
+ bp3_nextxbe_d1[3:0],
+
+
+ bp2_grant_cycle_d2,
+ bp2_header,
+ bp2_header_d2,
+ bp2_select,
+ bp2_select_d2,
+ bp2_next_winner[1:0],
+ bp2_next_winner_d2[1:0],
+ bp2_nextxbe[3:0],
+ bp2_nextxbe_d2[3:0],
+
+ bp1_header_d1,
+ bp1_header_d2,
+ bp1_select_d1,
+ bp1_select_d2,
+ bp1_next_winner_d1[1:0],
+ bp1_next_winner_d2[1:0],
+ bp1_nextxbe_d1[3:0],
+ bp1_nextxbe_d2[3:0],
+
+ xb0_obx_NextXbe_s3a, // This is unused signal now.
+ xb1_obx_NextXbe_s3a,
+ xb2_obx_NextXbe_s3a,
+ xb3_obx_NextXbe_s3a,
+
+ syn64,
+ dataout64,
+
+ 1'b0
+ };
+ // lint_checking SCX_UNUSED on
+
+
+endmodule
+
+module FswBypassArbiter (/*AUTOARG*/
+ // Outputs
+ bp_grant3, bp_grant2, bp_grant1, bp_grant0, bp_grant_cycle, bp_grant_cycle_d1, bp_grant_cycle_d2,
+ bp_next_winner, bp_next_winner_d1, bp_next_winner_d2, bp_nextxbe, bp_nextxbe_d1, bp_nextxbe_d2,
+ bp_hold_wait_vector, bp_hold_wait_vector_d1, bp_header, bp_header_d1, bp_header_d2, bp_select,
+ bp_select_d1, bp_select_d2,
+ // Inputs
+ lreset_l, sclk, bp_arb_enable, sop3, sop3_data, sop3_bpcontext, sop2, sop2_data, sop2_bpcontext,
+ sop1, sop1_data, sop1_bpcontext, sop0, sop0_data, sop0_bpcontext, poolmask, bufbusy_mask
+ ) ;
+
+ input lreset_l;
+ input sclk;
+ input bp_arb_enable;
+ output bp_grant3;
+ output bp_grant2;
+ output bp_grant1;
+ output bp_grant0;
+ output bp_grant_cycle;
+ output bp_grant_cycle_d1;
+ output bp_grant_cycle_d2;
+ output [1:0] bp_next_winner;
+ output [1:0] bp_next_winner_d1;
+ output [1:0] bp_next_winner_d2;
+ output [3:0] bp_nextxbe;
+ output [3:0] bp_nextxbe_d1;
+ output [3:0] bp_nextxbe_d2;
+ output [5:0] bp_hold_wait_vector;
+ output [5:0] bp_hold_wait_vector_d1;
+ output bp_header;
+ output bp_header_d1;
+ output bp_header_d2;
+ output bp_select;
+ output bp_select_d1;
+ output bp_select_d2;
+ input sop3;
+ input [63:0] sop3_data;
+ input [5:0] sop3_bpcontext;
+ input sop2;
+ input [63:0] sop2_data;
+ input [5:0] sop2_bpcontext;
+ input sop1;
+ input [63:0] sop1_data;
+ input [5:0] sop1_bpcontext;
+ input sop0;
+ input [63:0] sop0_data;
+ input [5:0] sop0_bpcontext;
+ input [15:0] poolmask;
+ input [63:0] bufbusy_mask;
+endmodule
diff --git a/tests_ok/autowire_import_bug317.v b/tests_ok/autowire_import_bug317.v
new file mode 100644
index 0000000..28eac7d
--- /dev/null
+++ b/tests_ok/autowire_import_bug317.v
@@ -0,0 +1,42 @@
+package pkg;
+ typedef logic [1:0] my_type;
+endpackage
+
+module top;
+ import pkg::*;
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ pkg::my_type_t a; // From sub_2 of sub_2.v
+ pkg::my_type_t z; // From sub_1 of sub_1.v
+ // End of automatics
+ sub_1 sub_1 (.*,
+ // Outputs
+ .z (z), // Implicit .*
+ // Inputs
+ .a (a)); // Implicit .*
+ sub_2 sub_2 (.*,
+ // Outputs
+ .a (a), // Implicit .*
+ // Inputs
+ .z (z)); // Implicit .*
+endmodule
+
+module sub_1
+ import pkg::*; // bug317
+ (
+ input pkg::my_type_t a,
+ output pkg::my_type_t z
+ );
+endmodule
+
+module sub_2
+ (
+ input pkg::my_type_t z,
+ output pkg::my_type_t a
+ );
+endmodule
+
+// Local Variables:
+// verilog-typedef-regexp: "_t$"
+// verilog-auto-star-save: t
+// End:
diff --git a/tests_ok/autowire_isaacson.v b/tests_ok/autowire_isaacson.v
new file mode 100644
index 0000000..628d443
--- /dev/null
+++ b/tests_ok/autowire_isaacson.v
@@ -0,0 +1,44 @@
+module t;
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire w11; // From bp3 of FswBypassArbiter.v
+ wire w12; // From bp3 of FswBypassArbiter.v
+ // End of automatics
+ /*AUTOREG*/
+
+ wand w0;
+ wor w1;
+ tri0 w2;
+ tri1 w3;
+ triand w4;
+ trior w5;
+ trireg w6;
+ tri w7;
+ wire w8;
+ supply0 w9;
+ supply1 w10;
+
+ FswBypassArbiter bp3 (/*AUTOINST*/
+ // Outputs
+ .w0 (w0),
+ .w1 (w1),
+ .w2 (w2),
+ .w3 (w3),
+ .w4 (w4),
+ .w5 (w5),
+ .w6 (w6),
+ .w7 (w7),
+ .w8 (w8),
+ .w9 (w9),
+ .w10 (w10),
+ .w11 (w11),
+ .w12 (w12));
+
+endmodule
+
+module FswBypassArbiter (/*AUTOARG*/
+ // Outputs
+ w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12
+ ) ;
+ output w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12;
+endmodule
diff --git a/tests_ok/autowire_long_yaohung.v b/tests_ok/autowire_long_yaohung.v
new file mode 100644
index 0000000..900533c
--- /dev/null
+++ b/tests_ok/autowire_long_yaohung.v
@@ -0,0 +1,27 @@
+module autowire_long_yaohung(/*AUTOARG*/
+ // Outputs
+ data_out
+ );
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [`LONGNAMELONGNAMELONGNAMELONGNAMELONGNAMELONGNAME] data_out;// From top of top.v
+ // End of automatics
+ /*AUTOWIRE*/
+ /*AUTOREG*/
+
+ top top
+ (/*AUTOINST*/
+ // Outputs
+ .data_out (data_out[`LONGNAMELONGNAMELONGNAMELONGNAMELONGNAMELONGNAME]));
+
+endmodule
+
+module top(/*AUTOARG*/
+ // Outputs
+ data_out
+ );
+
+ output [`LONGNAMELONGNAMELONGNAMELONGNAMELONGNAMELONGNAME] data_out;
+
+endmodule
diff --git a/tests_ok/autowire_lovell_hiear.v b/tests_ok/autowire_lovell_hiear.v
new file mode 100644
index 0000000..76652f0
--- /dev/null
+++ b/tests_ok/autowire_lovell_hiear.v
@@ -0,0 +1,32 @@
+module foo
+ (/*AUTOARG*/
+ // Outputs
+ another_output2
+ );
+
+ /*AUTOOUTPUTEVERY*/
+ // Beginning of automatic outputs (every signal)
+ output [1:0] another_output2; // From inst of autoinst_signed_fubar2.v
+ // End of automatics
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [1:0] another_output2; // From inst of autoinst_signed_fubar2.v
+ // End of automatics
+
+
+ /* autoinst_signed_fubar2 AUTO_TEMPLATE (
+ .an_output2 (hi.ear.ial),
+ );
+ */
+
+ autoinst_signed_fubar2 inst
+ (
+ /*AUTOINST*/
+ // Outputs
+ .an_output2 (hi.ear.ial), // Templated
+ .another_output2 (another_output2[1:0]),
+ // Inputs
+ .an_input2 (an_input2[1:0]));
+
+endmodule
diff --git a/tests_ok/autowire_merge_bug303.v b/tests_ok/autowire_merge_bug303.v
new file mode 100644
index 0000000..cd12790
--- /dev/null
+++ b/tests_ok/autowire_merge_bug303.v
@@ -0,0 +1,48 @@
+module TOP (/*AUTOARG*/
+ // Outputs
+ SIG_NAMEB, SIG_NAMEA
+ )
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [223:0] SIG_NAMEA; // From A of A.v, ...
+ output [FOO*4-2:0] SIG_NAMEB; // From C of C.v
+ // End of automatics
+ /*AUTOINPUT*/
+ /*AUTOWIRE*/
+
+ A A(/*AUTOINST*/
+ // Outputs
+ .SIG_NAMEA (SIG_NAMEA[224*1-1:128*1]));
+ B B(/*AUTOINST*/
+ // Outputs
+ .SIG_NAMEA (SIG_NAMEA[127:0]));
+ C C(/*AUTOINST*/
+ // Outputs
+ .SIG_NAMEB (SIG_NAMEB[FOO*4-2*1:0]));
+endmodule
+
+module A(/*AUTOARG*/
+ // Outputs
+ SIG_NAMEA
+ );
+ output [224*1-1:128*1] SIG_NAMEA;
+ //output [223:128] SIG_NAMEA;
+endmodule
+
+
+module B(/*AUTOARG*/
+ // Outputs
+ SIG_NAMEA
+ );
+ output [127:0] SIG_NAMEA;
+endmodule
+
+
+module C(/*AUTOARG*/
+ // Outputs
+ SIG_NAMEB
+ );
+ output [FOO*4-2*1:0] SIG_NAMEB;
+endmodule
+
+
diff --git a/tests_ok/autowire_misalias_bug295.v b/tests_ok/autowire_misalias_bug295.v
new file mode 100644
index 0000000..bd92690
--- /dev/null
+++ b/tests_ok/autowire_misalias_bug295.v
@@ -0,0 +1,35 @@
+interface my_interface ();
+ logic [2:0] out2;
+ logic [2:0] out3;
+endinterface: my_interface
+
+module foobar (input [2:0] in2, output [2:0] out2);
+endmodule
+
+module foo_autowire_fails (my_interface itf);
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [2:0] out2; // From foobar0 of foobar.v
+ // End of automatics
+ assign itf.out2 = out2; // perhaps a namespace collision?
+ foobar foobar0
+ (/*AUTOINST*/
+ // Outputs
+ .out2 (out2[2:0]),
+ // Inputs
+ .in2 (in2[2:0]));
+endmodule
+
+module foo_autowire_works (my_interface itf);
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [2:0] out2; // From foobar0 of foobar.v
+ // End of automatics
+ assign itf.out3 = out2;
+ foobar foobar0
+ (/*AUTOINST*/
+ // Outputs
+ .out2 (out2[2:0]),
+ // Inputs
+ .in2 (in2[2:0]));
+endmodule
diff --git a/tests_ok/autowire_myers.v b/tests_ok/autowire_myers.v
new file mode 100644
index 0000000..8515fce
--- /dev/null
+++ b/tests_ok/autowire_myers.v
@@ -0,0 +1,25 @@
+module test1 ( wireA, wireB );
+ output [3:0] wireA;
+ output [16:0] wireB;
+endmodule
+
+module test_top;
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [3:0] wireA; // From t1 of test1.v
+ wire [16:0] wireB; // From t1 of test1.v
+ // End of automatics
+
+ generate
+ if (1) begin
+ test1 t1 (/*AUTOINST*/
+ // Outputs
+ .wireA (wireA[3:0]),
+ .wireB (wireB[16:0]));
+ end
+ else begin
+ assign wireA = 0;
+ end
+ endgenerate
+endmodule
diff --git a/tests_ok/autowire_nocomment.v b/tests_ok/autowire_nocomment.v
new file mode 100644
index 0000000..ce9b7a5
--- /dev/null
+++ b/tests_ok/autowire_nocomment.v
@@ -0,0 +1,37 @@
+module top;
+
+ /*AUTOOUTPUTEVERY*/
+ // Beginning of automatic outputs (every signal)
+ output logic out1a;
+ output logic [1:0] out1b;
+ // End of automatics
+ /*AUTOREG*/
+
+ /*AUTOLOGIC*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic out1a;
+ logic [1:0] out1b;
+ // End of automatics
+
+
+ sub2 isub2 (/*AUTOINST*/
+ // Outputs
+ .out1a (out1a),
+ .out1b (out1b[1:0]),
+ // Inputs
+ .in1a (in1a),
+ .in1b (in1b));
+
+endmodule
+
+module sub2
+ ( input logic in1a,
+ input logic in1b,
+ output logic out1a,
+ output logic [1:0] out1b
+ );
+endmodule
+
+// Local Variables:
+// verilog-auto-wire-comment: nil
+// End:
diff --git a/tests_ok/autowire_paramvec_bug302.v b/tests_ok/autowire_paramvec_bug302.v
new file mode 100644
index 0000000..d1f217c
--- /dev/null
+++ b/tests_ok/autowire_paramvec_bug302.v
@@ -0,0 +1,60 @@
+module Abc_TEST ();
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ logic [5:0] [31:0] abc; // From u_Def of Def.v
+ // End of automatics
+
+ Abc #(
+ .No1 (6),
+ /*AUTOINSTPARAM*/
+ // Parameters
+ .No2 (No2),
+ .No3 (No3/*.[No1:0][No2-1:0]*/)) u_Abc
+ (
+ /*AUTOINST*/
+ // Inputs
+ .ck (ck),
+ .abc (abc/*[5:0][31:0]*/));
+
+ Def #(
+ .No1 (6)) u_Def
+ (
+ // Outputs
+ .ck (ck),
+ /*AUTOINST*/
+ // Outputs
+ .abc (abc/*[5:0][31:0]*/));
+
+endmodule
+
+
+module Abc
+ #(
+ parameter No1 = 6,
+ parameter int unsigned No2 // Parameter no. 2
+ = pa_Abc::No2,
+ parameter bit No3 [No1:0][No2-1:0] // Parameter no. 3
+ = pa_Abc::No3
+ )
+ (
+ input logic ck,
+ input logic [No1-1:0][31:0] abc
+ input logic [No1-1:0][31:0] abc
+ );
+endmodule
+
+module Def
+ #(
+ parameter No1 = 6
+ )
+ (
+ input logic ck,
+ output logic [No1-1:0][31:0] abc
+ );
+endmodule
+
+// Local Variables:
+// verilog-library-extensions:(".v" ".sv")
+// verilog-auto-inst-param-value:t
+// End:
diff --git a/tests_ok/autowire_pkg_bug195.v b/tests_ok/autowire_pkg_bug195.v
new file mode 100644
index 0000000..c62c395
--- /dev/null
+++ b/tests_ok/autowire_pkg_bug195.v
@@ -0,0 +1,66 @@
+`default_nettype none
+
+package testcase_pkg;
+
+ typedef int unsigned uint;
+
+ localparam uint SIZE = 8;
+
+ typedef enum {ENUM1, ENUM2} enum_t;
+
+endpackage
+
+module testcase_top
+ (
+ input testcase_pkg::enum_t top_enum,
+ input logic [testcase_pkg::SIZE-1:0] top_in,
+ output logic [testcase_pkg::SIZE-1:0] top_out
+ );
+ import testcase_pkg::*;
+ //enum_t sub_enum; // is not declared by AUTOWIRE
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ testcase_pkg::enum_t sub_enum; // From testcase_sub1 of testcase_sub1.v
+ logic [testcase_pkg::SIZE-1:0] sub_in; // From testcase_sub1 of testcase_sub1.v
+ logic [testcase_pkg::SIZE-1:0] sub_out; // From testcase_sub2 of testcase_sub2.v
+ // End of automatics
+ assign top_out = sub_out;
+ testcase_sub1 testcase_sub1 (.*,
+ // Outputs
+ .sub_enum (sub_enum), // Implicit .*
+ .sub_in (sub_in[testcase_pkg::SIZE-1:0]), // Implicit .*
+ // Inputs
+ .top_enum (top_enum)); // Implicit .*
+ testcase_sub2 testcase_sub2 (.*,
+ // Outputs
+ .sub_out (sub_out[testcase_pkg::SIZE-1:0]), // Implicit .*
+ // Inputs
+ .sub_enum (sub_enum), // Implicit .*
+ .sub_in (sub_in[testcase_pkg::SIZE-1:0])); // Implicit .*
+endmodule
+
+module testcase_sub1
+ (
+ input testcase_pkg::enum_t top_enum,
+ output testcase_pkg::enum_t sub_enum,
+ output logic [testcase_pkg::SIZE-1:0] sub_in
+ );
+ import testcase_pkg::*;
+ assign sub_enum = top_enum;
+ assign sub_in = '1;
+endmodule
+
+module testcase_sub2
+ (
+ input testcase_pkg::enum_t sub_enum,
+ input logic [testcase_pkg::SIZE-1:0] sub_in,
+ output logic [testcase_pkg::SIZE-1:0] sub_out
+ );
+ import testcase_pkg::*;
+ assign sub_out = (sub_enum==ENUM1) ? ~sub_in : sub_in;
+endmodule
+
+// Local Variables:
+// verilog-typedef-regexp: "_t$"
+// verilog-auto-star-save: t
+// End:
diff --git a/tests_ok/autowire_real.v b/tests_ok/autowire_real.v
new file mode 100644
index 0000000..5b6c68e
--- /dev/null
+++ b/tests_ok/autowire_real.v
@@ -0,0 +1,50 @@
+module sc_top (
+ input var real Tx_vcm,
+ input var real i_DAC_in,
+ input i_Tx_SC_en,
+ output var real Tx_vsc
+ );
+
+endmodule
+
+
+module cm_top (
+ input i_Tx_CM_en,
+ output var real Tx_vcm
+ );
+
+endmodule
+
+module top (
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output real Tx_vsc, // From sc_buf of sc_top.v
+ // End of automatics
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input real i_DAC_in, // To sc_buf of sc_top.v
+ input i_Tx_CM_en, // To cm_buf of cm_top.v
+ input i_Tx_SC_en // To sc_buf of sc_top.v
+ // End of automatics
+ );
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ real Tx_vcm; // From cm_buf of cm_top.v
+ // End of automatics
+
+ cm_top cm_buf (/*AUTOINST*/
+ // Outputs
+ .Tx_vcm (Tx_vcm),
+ // Inputs
+ .i_Tx_CM_en (i_Tx_CM_en));
+
+ sc_top sc_buf (/*AUTOINST*/
+ // Outputs
+ .Tx_vsc (Tx_vsc),
+ // Inputs
+ .Tx_vcm (Tx_vcm),
+ .i_DAC_in (i_DAC_in),
+ .i_Tx_SC_en (i_Tx_SC_en));
+
+endmodule
diff --git a/tests_ok/autowire_req.v b/tests_ok/autowire_req.v
new file mode 100644
index 0000000..b0cb6c7
--- /dev/null
+++ b/tests_ok/autowire_req.v
@@ -0,0 +1,20 @@
+
+module autowire_req ();
+
+ reqcmd_t AReq;
+ reqcmd_t BReq;
+
+ /*AUTOWIRE*/
+
+ autowire_req_sw autowire_req_sw (/*AUTOINST*/
+ // Outputs
+ .BReq (BReq),
+ // Inputs
+ .AReq (AReq));
+
+endmodule
+
+// Local Variables:
+// verilog-library-directories:(".")
+// verilog-typedef-regexp:"_t$"
+// End:
diff --git a/tests_ok/autowire_req_sw.v b/tests_ok/autowire_req_sw.v
new file mode 100644
index 0000000..a62ceed
--- /dev/null
+++ b/tests_ok/autowire_req_sw.v
@@ -0,0 +1,19 @@
+`include "pf_sc.vh"
+
+module autowire_req_sw
+ (
+ input reqcmd_t AReq,
+ output reqcmd_t BReq
+ /*AUTOINPUT*/
+ );
+
+ assign Bnk0Req = Cpu0Req;
+
+
+endmodule
+
+
+// Local Variables:
+// verilog-library-directories:(".")
+// verilog-typedef-regexp:"_t$"
+// End:
diff --git a/tests_ok/autowire_thon_selects.v b/tests_ok/autowire_thon_selects.v
new file mode 100644
index 0000000..0c9306f
--- /dev/null
+++ b/tests_ok/autowire_thon_selects.v
@@ -0,0 +1,38 @@
+module foo
+ (/*AUTOARG*/
+ // Outputs
+ aa
+ );
+
+ /*AUTOOUTPUTEVERY*/
+ // Beginning of automatic outputs (every signal)
+ output [Y:X] aa; // From inst of autoinst_signed_fubar2.v, ..., Couldn't Merge
+ // End of automatics
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [Y:X] aa; // From inst of autoinst_signed_fubar2.v, ..., Couldn't Merge
+ // End of automatics
+
+
+ // Check that if aa is connected differently in a input, it doesn't make conflicts.
+
+ autoinst_signed_fubar2 inst
+ (
+ // Outputs
+ .an_output2 (hi.ear.ial),
+ .another_output2 (aa[FOO:0]),
+ // Inputs
+ .an_input2 (an_input2[1:0])
+ /*AUTOINST*/);
+
+ autoinst_signed_fubar2 instx
+ (
+ // Outputs
+ .an_output2 (hi.ear.ial),
+ // Inputs
+ .an_input2 (an_input2[1:0]),
+ .another_output2 (aa[Y:X]),
+ /*AUTOINST*/);
+
+endmodule
diff --git a/tests_ok/autowire_totte.v b/tests_ok/autowire_totte.v
new file mode 100644
index 0000000..2c5c9d2
--- /dev/null
+++ b/tests_ok/autowire_totte.v
@@ -0,0 +1,59 @@
+module test1 ( wire2, wire4 );
+ output [3:0] wire2;
+ output [16:0] wire4;
+endmodule
+
+module test2 ( wire6, wire12 );
+ input [3:0] wire6;
+ input [16:0] wire12;
+endmodule
+
+module test3 ( wireA, wireB );
+ input [3:0] wireA;
+ input [16:0] wireB;
+endmodule
+
+module test4 ( wireA, wireB );
+ output [3:0] wireA;
+ output [16:0] wireB;
+endmodule
+
+module test_top;
+
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire [3:0] wireA; // From t4 of test4.v
+ wire [16:0] wireB; // From t4 of test4.v
+ wire [3:0] wire_2_to_6; // From t1 of test1.v
+ wire [16:0] wire_4_to_12; // From t1 of test1.v
+ // End of automatics
+
+ /* test1 AUTO_TEMPLATE (
+ .wire@(wire_\1_to_@"(* \1 3)"[]),
+ ); */
+
+ test1 t1 (/*AUTOINST*/
+ // Outputs
+ .wire2 (wire_2_to_6[3:0]), // Templated
+ .wire4 (wire_4_to_12[16:0])); // Templated
+
+ /* test2 AUTO_TEMPLATE (
+ .wire@(wire@"(/ \1 3)"_to_\1[]),
+ ); */
+
+ test2 t2 (/*AUTOINST*/
+ // Inputs
+ .wire6 (wire2_to_6[3:0]), // Templated
+ .wire12 (wire4_to_12[16:0])); // Templated
+
+ test3 t3 (/*AUTOINST*/
+ // Inputs
+ .wireA (wireA[3:0]),
+ .wireB (wireB[16:0]));
+
+ test4 t4 (/*AUTOINST*/
+ // Outputs
+ .wireA (wireA[3:0]),
+ .wireB (wireB[16:0]));
+
+endmodule
diff --git a/tests_ok/batch_li_child.v b/tests_ok/batch_li_child.v
new file mode 100644
index 0000000..1b3a1cc
--- /dev/null
+++ b/tests_ok/batch_li_child.v
@@ -0,0 +1,27 @@
+module batch_li_child
+ #(parameter
+
+ WIDTH_0= 'h8,
+ WIDTH_1 = 'h4
+ )
+ (
+ input rst,
+ input clk
+ );
+
+ reg [WIDTH_0-1:0] counter_0;
+ reg [WIDTH_1-1:0] counter_1;
+
+ always @(posedge clk) begin
+ if (rst) begin
+ counter_0 <= #1 0;
+ counter_1 <= #1 0;
+ end
+ else begin
+ counter_0 <= #1 counter_0 + 1'b1;
+ counter_1 <= #1 counter_1 + 1'b1;
+ end
+ end
+
+endmodule
+
diff --git a/tests_ok/batch_li_parent.v b/tests_ok/batch_li_parent.v
new file mode 100644
index 0000000..1687fd8
--- /dev/null
+++ b/tests_ok/batch_li_parent.v
@@ -0,0 +1,25 @@
+module batch_li_parent (/*AUTOARG*/
+ // Inputs
+ clk, rst
+ );
+
+ input rst;
+ input clk;
+
+ parameter WIDTH_0 = 8;
+ parameter WIDTH_1 = 16;
+
+ batch_li_child
+ #(.WIDTH_1 (WIDTH_0),
+ .WIDTH_0 (WIDTH_1))
+ child
+ (/*AUTOINST*/
+ // Inputs
+ .rst (rst),
+ .clk (clk));
+
+endmodule
+
+// Local Variables:
+// verilog-auto-arg-sort: t
+// End:
diff --git a/tests_ok/batch_prof_cell.v b/tests_ok/batch_prof_cell.v
new file mode 100644
index 0000000..288354a
--- /dev/null
+++ b/tests_ok/batch_prof_cell.v
@@ -0,0 +1,4 @@
+module batch_prof_cell(Z,A,B);
+ output Z;
+ input A, B;
+endmodule
diff --git a/tests_ok/carlson.v b/tests_ok/carlson.v
new file mode 100644
index 0000000..4cf898d
--- /dev/null
+++ b/tests_ok/carlson.v
@@ -0,0 +1,19 @@
+module x ();
+ always @ (/*AUTOSENSE*/bus or in1 or in2 or reset) begin
+ out4 = | bus;
+
+ out7 = 1'b0; // pre-initialize output of case so default not needed
+ case (bus[1:0])
+ 2'b00: out7 = in1;
+ 2'b01: out7 = in2;
+ 2'b10: out7 = reset;
+`ifdef BEH
+ default: begin
+ out7 = 1'bX; // force VCS simulation to propagate X's from the bus signal
+ $display ("\n Error, in module temp, bus[1:0] illegal value of 11\n");
+ end
+`endif
+
+ endcase // case(bus[1:0])
+ end
+endmodule
diff --git a/tests_ok/case_question.v b/tests_ok/case_question.v
new file mode 100644
index 0000000..f08f33f
--- /dev/null
+++ b/tests_ok/case_question.v
@@ -0,0 +1,16 @@
+module test ();
+
+ always @(/*AUTOSENSE*/xyz)
+ begin
+ casex (xyz)
+ 4'b???0: r = 1;
+ 4'b??01: r = 2;
+ 4'b?001: r = 3;
+ default: r = 4;
+ endcase
+ end
+
+ assign x = y;
+
+endmodule
+
diff --git a/tests_ok/comment_strip.v b/tests_ok/comment_strip.v
new file mode 100644
index 0000000..0c3c8c6
--- /dev/null
+++ b/tests_ok/comment_strip.v
@@ -0,0 +1,25 @@
+module foo;
+ initial begin
+ /* The function verilog-strip-comments should not change this line:*/
+ $display("INFO :[PIPE LINK %d]: ///////////////////////////////////////////",PIPE_LINK);
+
+ // to this:
+ $display("INFO :[PIPE LINK %d]: ");
+
+ /* The function verilog-strip-comments should not change this line:*/
+ $display("INFO :[PIPE LINK %d]: /* ",PIPE_LINK); /* This comment should go away */
+ // to this:
+ $display("INFO :[PIPE LINK %d]: ");
+
+ /* also this comment should not get eaten
+ because of use of slashes // and such like
+ */
+ /*
+ ugly hidded end comment // */
+ $display("don't forget me agentina");
+ // another hidden comment /*
+ /**/
+
+ end
+
+endmodule // foo
diff --git a/tests_ok/debug.v b/tests_ok/debug.v
new file mode 100644
index 0000000..bb5740d
--- /dev/null
+++ b/tests_ok/debug.v
@@ -0,0 +1,15 @@
+`include "some_macros.v"
+
+module z();
+
+ $display("%t:", $time);
+ a = b;
+ casfasdf = d;
+ g = r;
+ fgasdfasdfasdfasfdasfd <= p;
+ gh := h;
+ gf <=g;
+ ssdf = 5;
+ f = zsfdsdf >= f;
+
+endmodule
diff --git a/tests_ok/disable.v b/tests_ok/disable.v
new file mode 100644
index 0000000..df0f9f6
--- /dev/null
+++ b/tests_ok/disable.v
@@ -0,0 +1,27 @@
+module foo;
+ task my_task;
+ begin :body_my_task
+ fork
+ join
+ case (a)
+ endcase // case endcase
+ if (a) begin
+ end
+ begin
+ end
+ fork : main_fork
+ begin : body_main_fork
+ fork : sub_fork
+ begin
+ // st1
+ end
+ begin
+ // st2
+ end
+ join_any // first wins
+ a = b;
+ disable fork; // kill others
+ end // block: body_main_fork
+ end // block: body_main_fork
+ endtask // my_task
+endmodule // foo
diff --git a/tests_ok/escape_a.v b/tests_ok/escape_a.v
new file mode 100644
index 0000000..a1d03f0
--- /dev/null
+++ b/tests_ok/escape_a.v
@@ -0,0 +1,14 @@
+module escape_a (/*AUTOARG*/
+ // Outputs
+ \o[10] , \o[2] ,
+ // Inputs
+ \i&e;
+ );
+ output \o[10] ;
+ output \o[2] ;
+ input \i&e; ;
+
+ wire \o[10] = \i&e; ;
+ wire \o[2] = \i&e; ;
+
+endmodule
diff --git a/tests_ok/escape_top.v b/tests_ok/escape_top.v
new file mode 100644
index 0000000..b5976bd
--- /dev/null
+++ b/tests_ok/escape_top.v
@@ -0,0 +1,29 @@
+module escape_top (/*AUTOARG*/
+ // Outputs
+ \oren10 , \o[2] ,
+ // Inputs
+ \i&e;
+ );
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input \i&e; ; // To a of escape_a.v
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output \o[2] ; // From a of escape_a.v
+ output \oren10 ; // From a of escape_a.v
+ // End of automatics
+
+ /* escape_a AUTO_TEMPLATE(
+ .\(.*o.*10.*\) (\\oren10 ),
+ ); */
+
+ escape_a a (/*AUTOINST*/
+ // Outputs
+ .\o[10] (\oren10 ), // Templated
+ .\o[2] (\o[2] ),
+ // Inputs
+ .\i&e; (\i&e; ));
+
+endmodule
diff --git a/tests_ok/example.v b/tests_ok/example.v
new file mode 100644
index 0000000..209afb0
--- /dev/null
+++ b/tests_ok/example.v
@@ -0,0 +1,33 @@
+module example (/*AUTOARG*/
+ // Outputs
+ lower_out, o,
+ // Inputs
+ lower_inb, lower_ina, i
+ );
+ input i;
+ output o;
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input lower_ina; // To inst of inst.v
+ input lower_inb; // To inst of inst.v
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output lower_out; // From inst of inst.v
+ // End of automatics
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg o;
+ // End of automatics
+ inst inst (/*AUTOINST*/
+ // Outputs
+ .lower_out (lower_out),
+ // Inputs
+ .lower_inb (lower_inb),
+ .lower_ina (lower_ina));
+ always @ (/*AUTOSENSE*/i) begin
+ o = i;
+ end
+endmodule
+
+
diff --git a/tests_ok/flag_f_reeves.v b/tests_ok/flag_f_reeves.v
new file mode 100644
index 0000000..239a072
--- /dev/null
+++ b/tests_ok/flag_f_reeves.v
@@ -0,0 +1,30 @@
+
+module flag_f_reeves
+ (/*AUTOARG*/
+ // Outputs
+ q,
+ // Inputs
+ a
+ ) ;
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output q; // From ibuf of flag_f_reeves_IBUF.v
+ // End of automatics
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input a; // To ibuf of flag_f_reeves_IBUF.v
+ // End of automatics
+
+ flag_f_reeves_IBUF ibuf
+ (/*AUTOINST*/
+ // Outputs
+ .q (q),
+ // Inputs
+ .a (a));
+
+endmodule
+// Local Variables:
+// verilog-library-flags: ("-f flag_f_reeves.vc")
+// End:
diff --git a/tests_ok/flag_f_reeves.vc b/tests_ok/flag_f_reeves.vc
new file mode 100644
index 0000000..b62fcce
--- /dev/null
+++ b/tests_ok/flag_f_reeves.vc
@@ -0,0 +1 @@
+-y subdir
diff --git a/tests_ok/for.v b/tests_ok/for.v
new file mode 100644
index 0000000..cba503d
--- /dev/null
+++ b/tests_ok/for.v
@@ -0,0 +1,28 @@
+module lbm
+ (/*AUTOARG*/
+ // Outputs
+ outgo,
+ // Inputs
+ income
+ );
+
+ input [1:0] income;
+ output [1:0] outgo;
+ reg [1:0] outgo;
+
+ integer i;
+ always @ (/*AUTOSENSE*/income) begin
+ for (i=0; i<32; i=i+1) begin
+ outgo[i] = income[i];
+ end
+ end
+
+ always @ (/*AUTOSENSE*/income) begin
+ if (|income) begin
+ $display("[0%10t] %I-for.v: found %s \"quote\" ",
+ $time, ((|income)?"in":"out"));
+
+ end
+ end
+
+endmodule
diff --git a/tests_ok/gorfajn.v b/tests_ok/gorfajn.v
new file mode 100644
index 0000000..32dc99e
--- /dev/null
+++ b/tests_ok/gorfajn.v
@@ -0,0 +1,12 @@
+module x;
+ always @(/*autosense*/d32S_CurCcbH or ramS_CcbBaseH or ramS_ccbsizeH)
+ begin
+ case (ramS_ccbsizeH)
+ 2'b00 : ramS_CcbAddH = {2'b00, d32S_CurCcbH };
+ 2'b01 : ramS_CcbAddH = {1'b0, d32S_CurCcbH, 1'b0};
+ 2'b10 : ramS_CcbAddH = {d32S_CurCcbH, 2'b00};
+ 2'b11 : ramS_CcbAddH = {d32S_CurCcbH, 2'b00}; // unused
+ endcase
+ ramS_CcbAddresH = {10'h000, ramS_CcbAddH} + ramS_CcbBaseH;
+ end
+endmodule
diff --git a/tests_ok/grisamore_twoinone.v b/tests_ok/grisamore_twoinone.v
new file mode 100644
index 0000000..d18446a
--- /dev/null
+++ b/tests_ok/grisamore_twoinone.v
@@ -0,0 +1,44 @@
+module foo (/*AUTOARG*/
+ // Outputs
+ d,
+ // Inputs
+ b, a
+ );
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input a; // To foo2 of foo2.v
+ input b; // To foo2 of foo2.v
+ // End of automatics
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output d; // From foo2 of foo2.v
+ // End of automatics
+ /*AUTOWIRE*/
+ /*AUTOREGINPUT*/
+ foo2 foo2 (/*AUTOINST*/
+ // Outputs
+ .d (d),
+ // Inputs
+ .a (a),
+ .b (b));
+
+endmodule
+
+
+module foo2 (/*AUTOARG*/
+ // Outputs
+ d,
+ // Inputs
+ a, b
+ );
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ /*AUTOWIRE*/
+ /*AUTOREGINPUT*/
+ input a;
+ input b;
+ output d;
+
+ //{ Behavioral verilog code here}
+endmodule
+
diff --git a/tests_ok/hangcase.v b/tests_ok/hangcase.v
new file mode 100644
index 0000000..4c50252
--- /dev/null
+++ b/tests_ok/hangcase.v
@@ -0,0 +1,59 @@
+// See Line 54
+
+module hangcase (/*AUTOARG*/);
+
+ //
+ assign w_rdat_ena = ({16{foo[ 0]}} & bar ) |
+ ({16{foo[ 1]}} & bar ) |
+ ({16{foo[ 2]}} & bar ) |
+ ({16{foo[ 3]}} & bar ) |
+ ({16{foo[ 4]}} & bar ) |
+ ({16{foo[ 5]}} & bar ) |
+ ({16{foo[ 6]}} & bar ) |
+ ({16{foo[ 7]}} & bar ) |
+ ({16{foo[ 8]}} & bar ) |
+ ({16{foo[ 9]}} & bar ) |
+ ({16{foo[10]}} & bar ) |
+ ({16{foo[11]}} & bar ) |
+ ({16{foo[12]}} & bar ) |
+ ({16{foo[13]}} & bar ) |
+ ({16{foo[14]}} & bar ) |
+ ({16{foo[15]}} & bar ) ;
+
+ //
+ assign w_rdat_mrk = ({16{foo[ 0]}} & bar & baz ) |
+ ({16{foo[ 1]}} & bar & baz ) |
+ ({16{foo[ 2]}} & bar & baz ) |
+ ({16{foo[ 3]}} & bar & baz ) |
+ ({16{foo[ 4]}} & bar & baz ) |
+ ({16{foo[ 5]}} & bar & baz ) |
+ ({16{foo[ 6]}} & bar & baz ) |
+ ({16{foo[ 7]}} & bar & baz ) |
+ ({16{foo[ 8]}} & bar & baz ) |
+ ({16{foo[ 9]}} & bar & baz ) |
+ ({16{foo[10]}} & bar & baz ) |
+ ({16{foo[11]}} & bar & baz ) |
+ ({16{foo[12]}} & bar & baz ) |
+ ({16{foo[13]}} & bar & baz ) |
+ ({16{foo[14]}} & bar & baz ) |
+ ({16{foo[15]}} & bar & baz ) ;
+
+ //
+ assign w_wdat_ena_set = ({16{ena_set}} & col_dec );
+ assign w_wdat_ena_clr = ({16{ena_clr}} & col_dec );
+ assign w_wdat_mrk_set = ({16{mrk_set}} & w_rdat_ena );
+ assign w_wdat_mrk_clr = ({16{mrk_clr}} & col_dec );
+ assign w_wdat_ena = (w_rdat_ena & ~w_wdat_ena_clr) | w_wdat_ena_set;
+ assign w_wdat_mrk = (w_rdat_mrk & ~w_wdat_mrk_clr) | w_wdat_mrk_set;
+
+ //
+ assign w_dat15_ena = foo[15] ? w_wdat_ena : bar;
+
+ //
+ assign w_dat15_mrk = foo[15] ? w_wdat_mrk : baz;
+
+ //^^^^ FIX NEWLINE ABOVE HERE
+ //
+ assign w_timeout_mrk = row_check ? w_wdat_mrk : r_timeout_mrk;
+
+endmodule
diff --git a/tests_ok/indent_1.v b/tests_ok/indent_1.v
new file mode 100644
index 0000000..e76978d
--- /dev/null
+++ b/tests_ok/indent_1.v
@@ -0,0 +1,6 @@
+module foo(reg_input_signal_name);
+ input a;
+ input reg_input_signal_name;
+
+endmodule // foo
+
diff --git a/tests_ok/indent_2.v b/tests_ok/indent_2.v
new file mode 100644
index 0000000..b1e68f7
--- /dev/null
+++ b/tests_ok/indent_2.v
@@ -0,0 +1,18 @@
+module foo(reg_input_signal_name,a,b,c,d,e);
+ // foo bar
+ output c;//this is a comment
+
+
+ reg foo;
+ //a
+
+ /* jj
+ KK */
+ reg foo;
+ output reg /* */ signed d;
+ output reg signed e; /* so is this */
+
+ reg [31:0] blather;
+
+endmodule // foo
+
diff --git a/tests_ok/indent_3.v b/tests_ok/indent_3.v
new file mode 100644
index 0000000..8c3114a
--- /dev/null
+++ b/tests_ok/indent_3.v
@@ -0,0 +1,12 @@
+module junk (/*AUTOARG*/
+ // Outputs
+ c_junk, d_junk,
+ // Inputs
+ a_junk, b_junk
+ ) ;
+ input a_junk;
+ input wire signed [15:0] b_junk;
+ output c_junk;
+ output [15:0][31:0][1024:(`REALLY_BIG_NAME-1)] d_junk;
+endmodule // junk
+
diff --git a/tests_ok/indent_4.v b/tests_ok/indent_4.v
new file mode 100644
index 0000000..4d026fe
--- /dev/null
+++ b/tests_ok/indent_4.v
@@ -0,0 +1,22 @@
+module foo;
+ initial
+ begin
+ s1;
+ end
+
+ always @(a)
+ begin
+ s1;
+ end // always @ (a)
+ always
+ begin
+ s1;
+ end // always begin
+ always_ff
+ begin
+ end // always_ff begin
+ task
+ t;
+ endtask // t
+
+endmodule // foo
diff --git a/tests_ok/indent_always_decl.v b/tests_ok/indent_always_decl.v
new file mode 100644
index 0000000..3cbdb91
--- /dev/null
+++ b/tests_ok/indent_always_decl.v
@@ -0,0 +1,34 @@
+module foo ();
+ // Before the always block,
+ // indents to here: (which I like)
+ // V
+ wire [10:0] mux_output0 =
+ select0[0] ? mux_input0 :
+ select0[1] ? mux_input1 :
+ select0[2] ? mux_input2 :
+ select0[3] ? mux_input3 :
+ select0[4] ? mux_input4 :
+ select0[5] ? mux_input5 :
+ select0[6] ? mux_input6 :
+ mux_input7;
+
+ reg foobar;
+ always @(posedge clk)
+ if (reset_n) begin
+ foobar <= 1'b0;
+ end
+
+ // After the always block,
+ // indents to here:
+ // V
+ wire [10:0] mux_output1 =
+ select1[0] ? mux_input8 :
+ select1[1] ? mux_input9 :
+ select1[2] ? mux_input10 :
+ select1[3] ? mux_input11 :
+ select1[4] ? mux_input12 :
+ select1[5] ? mux_input13 :
+ select1[6] ? mux_input14 :
+ mux_input15;
+endmodule
+
diff --git a/tests_ok/indent_assert.v b/tests_ok/indent_assert.v
new file mode 100644
index 0000000..30a933c
--- /dev/null
+++ b/tests_ok/indent_assert.v
@@ -0,0 +1,7 @@
+module assert_test;
+ reg [31:0] whatever2;
+ initial begin
+ a = b;
+ assert(std::randomize(whatever2) with { whatever2 inside {[10:100]};});
+ end
+endmodule // assert_test
diff --git a/tests_ok/indent_assert_else.v b/tests_ok/indent_assert_else.v
new file mode 100644
index 0000000..04552aa
--- /dev/null
+++ b/tests_ok/indent_assert_else.v
@@ -0,0 +1,50 @@
+module myassert(input clk,
+ input reset,
+ input [15:0] data);
+
+ property myproperty;
+ @(posedge clk)
+ $rose(reset) |-> data == 16'h0;
+ endproperty
+
+ //Assert, cover, and assume property statements
+ //support begin/end keywords. The else begin/end
+ //clause below is getting indented improperly.
+ myassert0: assert property(myproperty) begin
+ $display("myassert0 was successful");
+ a;
+ b;
+ c;
+ d;
+ end // myassert0: assert property (myproperty)
+ else begin
+ $fatal("myassert0 was unsuccessful");
+ end // else: !assert property(myproperty)
+ if (a) begin
+ b;
+ c;
+ end // if (a)
+ else begin
+ o;
+ end // else: !if(a)
+ assert (a) begin
+ o;
+ end // assert (a)
+ else begin
+ o;
+ end // else: !assert (a)
+
+ assert (statement) begin
+ $display("assertion passed"); //this code is correctly indented
+ end // assert (statement)
+ else begin // this whole section should be moved to the left
+ $error("assertion failed");
+ end // else: !assert (statement)
+
+ //Also, any statements following the assert,
+ //cover, and assume property statements get
+ // indented too far to the right.
+ always @(posedge clk) begin
+ a;
+ end // always @ (posedge clk)
+endmodule
diff --git a/tests_ok/indent_assert_property.v b/tests_ok/indent_assert_property.v
new file mode 100644
index 0000000..02359e8
--- /dev/null
+++ b/tests_ok/indent_assert_property.v
@@ -0,0 +1,25 @@
+module myassert(input clk,
+ input reset,
+ input [15:0] data);
+
+ property myproperty;
+ @(posedge clk)
+ $rose(reset) |-> data == 16'h0;
+ endproperty
+
+ //Assert, cover, and assume property statements
+ //support begin/end keywords. The else begin/end
+ //clause below is getting indented improperly.
+ myassert0: assert property(myproperty) begin
+ $display("myassert0 was successful");
+ end
+ else begin
+ $fatal("myassert0 was unsuccessful");
+ end
+
+ //Also, any statements following the assert,
+ //cover, and assume property statements get
+ // indented too far to the right.
+ always @(posedge clk) begin
+ end
+endmodule
diff --git a/tests_ok/indent_assignment.v b/tests_ok/indent_assignment.v
new file mode 100644
index 0000000..837bf68
--- /dev/null
+++ b/tests_ok/indent_assignment.v
@@ -0,0 +1,28 @@
+// Issue 941 : The following operators should not be broken by auto-indents
+module m;
+ initial begin
+ a = b;
+ a <= b;
+ a <<= b;
+ a <<<= b;
+ a >= b;
+ a >>= b;
+ a >>>= b;
+ a == b;
+ a != b;
+ a === b;
+ a !== b;
+ a ==? b;
+ a !=? b;
+ a <-> b;
+ a -> b;
+ a ->> b;
+ a |-> b;
+ a |=> b;
+ a #-# b;
+ a #=# b;
+ a := b;
+ a :/ b;
+ end
+
+endmodule
diff --git a/tests_ok/indent_attributes.v b/tests_ok/indent_attributes.v
new file mode 100644
index 0000000..e390887
--- /dev/null
+++ b/tests_ok/indent_attributes.v
@@ -0,0 +1,10 @@
+module example(out1, out2, out3);
+ (* LOC = "D14" *)
+ output out1;
+ /* foobar */ (* LOC = "C15" *) /* jar */ output out2;
+ (* LOC = "C16" *)
+ output out3;
+ out1 = 1'b1;
+ out2 = 1'b1;
+ out3 = 1'b1;
+endmodule
diff --git a/tests_ok/indent_begin_clapp.v b/tests_ok/indent_begin_clapp.v
new file mode 100644
index 0000000..a543055
--- /dev/null
+++ b/tests_ok/indent_begin_clapp.v
@@ -0,0 +1,44 @@
+// bug 825
+module x;
+
+ always @*
+ begin
+ end
+
+ initial
+ begin
+ end
+
+ final
+ begin
+ end
+
+ initial forever
+ begin
+ end
+
+ foreach(1)
+ begin
+ end
+
+ do
+ begin
+ end while (i);
+
+ initial @a.b
+ begin
+ end
+
+ always @E
+ begin
+ end
+
+ forever @E
+ begin
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-indent-begin-after-if: nil
+// End:
diff --git a/tests_ok/indent_bracket.v b/tests_ok/indent_bracket.v
new file mode 100644
index 0000000..f4aabdc
--- /dev/null
+++ b/tests_ok/indent_bracket.v
@@ -0,0 +1,12 @@
+// bug437: Indentation of continued assignment incorrect if first line ends with ']'
+module foo
+ (input [63:0] data_in,
+ input ctl_in,
+
+ output [63:0] data_out,
+ output ctl_out);
+
+ assign data_out = data_in[1] ? data_in[63:0]
+ : 64'h0;
+
+endmodule
diff --git a/tests_ok/indent_case.v b/tests_ok/indent_case.v
new file mode 100644
index 0000000..2228c0d
--- /dev/null
+++ b/tests_ok/indent_case.v
@@ -0,0 +1,48 @@
+module testcaseindent();
+ case (a)
+ 1: begin
+ asdf;
+ end // case: 1
+
+ 2: begin
+ asdfasdf;
+ end // case: 2
+
+ 3: begin
+ asdfasd;
+ end // case: 3
+
+ endcase // case (a)
+
+
+ unique case (a)
+ 1: begin
+ asdf;
+ end // case: 1
+
+ 2: begin
+ case (d)
+ 2: a;
+ 3: c;
+ 4: begin
+ priority casex (f)
+ 4: g;
+ 5: h;
+ endcase // priority casex
+ end
+ endcase // case (d)
+ asdfasdf;
+ end // case: 2
+
+ 3: begin
+ asdfasd;
+ end // case: 3
+
+ endcase // case (a)
+ unique case (a)
+ 1: asdf;
+ 2: asdfasdf;
+ 3: asdfasd;
+ endcase // case (a)
+
+endmodule // test_case_indent
diff --git a/tests_ok/indent_class.v b/tests_ok/indent_class.v
new file mode 100644
index 0000000..1a186f1
--- /dev/null
+++ b/tests_ok/indent_class.v
@@ -0,0 +1,53 @@
+class foo();
+ int my_field;
+endclass // foo
+
+class temp;
+ extern function test();
+ extern function test2();
+ function foo();
+ foo = 1;
+ endfunction // foo
+ extern function test3();
+ reg [31:0] b;
+endclass // temp
+
+class short extends temp;
+ logic a;
+endclass
+
+`define vmm_channel(A) A+A
+
+
+module foo;
+ reg a;
+ reg [1:0] b;
+
+ initial begin
+ b = `vmm_channel(a);
+ end // initial begin
+endmodule // foo
+
+
+class A;
+ extern function int e1();
+ extern function int e2(int src,int dst);
+ extern static function int f1();
+ extern static function int f2(int src,int dst);
+ extern static function int f3(int src,int dst);
+ extern static function chandle f10(int src);
+ extern static function automatic int f11(int mcid);
+ extern function automatic int f13(int mcid);
+ static function int s1();
+ int i = 0;
+ endfunction
+ static function int s2();
+ int i = 0;
+ endfunction
+ function int f1();
+ int i = 0;
+ endfunction
+ function int f2();
+ int i = 0;
+ endfunction
+endclass
diff --git a/tests_ok/indent_clocking.v b/tests_ok/indent_clocking.v
new file mode 100644
index 0000000..f183818
--- /dev/null
+++ b/tests_ok/indent_clocking.v
@@ -0,0 +1,17 @@
+module t;
+ default clocking @(posedge clk);
+ begin
+ a = 8;
+ end
+ property foo (a)
+ a = b;
+ endproperty
+ cover property (prop) $display("**COVERAGE**");
+ assert property (foo) a;
+ assume property (bar) b;
+ b1: assume property (bar) b;
+ B2: assert property (foo) a;
+ B2: cover property (foo) a;
+ assume property (bar) b;
+ a;
+endmodule
diff --git a/tests_ok/indent_clockingblock.v b/tests_ok/indent_clockingblock.v
new file mode 100644
index 0000000..bc20e2c
--- /dev/null
+++ b/tests_ok/indent_clockingblock.v
@@ -0,0 +1,38 @@
+class mipsbfm_trans extends vmm_data;
+ static vmm_log log = new ("mipsbfm_trans", "class") ;
+ logic [31:0] addr, data, mask, op;
+ function new();
+ super.new(this.log);
+ endfunction: new
+endclass // mipsbfm_trans
+
+interface mipsbfm_if(input clk);
+ logic [31:0] data;
+ logic [31:0] addr;
+ logic [31:0] mask;
+ logic [31:0] op;
+ logic valid;
+
+ clocking cb @(posedge clk);
+ output data;
+ output addr;
+ output mask;
+ output op;
+ output valid;
+ endclocking // cb
+
+endinterface // mipsbfm_if
+
+
+`vmm_channel(mipsbfm_trans);
+
+//--------------------------------------------------------------
+// MIPS BFM Master Xactor Class
+//--------------------------------------------------------------
+
+class mipsbfm_master extends vmm_xactor;
+ // Transaction channels
+ mipsbfm_trans_channel in_chan ;
+
+endclass // mipsbfm_master
+
diff --git a/tests_ok/indent_comments.v b/tests_ok/indent_comments.v
new file mode 100644
index 0000000..8de36df
--- /dev/null
+++ b/tests_ok/indent_comments.v
@@ -0,0 +1,7 @@
+module dummy (
+ input wire xx,
+ output wire yy, // comment with paren ) adsfasdf
+ ouput wire zz); // oops - matched paren in comment!!
+endmodule // dummy
+
+
diff --git a/tests_ok/indent_constraint.v b/tests_ok/indent_constraint.v
new file mode 100644
index 0000000..4d5ece1
--- /dev/null
+++ b/tests_ok/indent_constraint.v
@@ -0,0 +1,146 @@
+// my simple if else example, indented by verilog-mode
+if (x == 1)
+ begin
+ test1 <= 1;
+ test2 <= 2;
+ end
+else
+ begin
+ test1 <= 2;
+ test2 <= 1;
+ end
+
+// code from IEEE spec, pg. 164
+class MyBus extends Bus;
+ rand AddrType atype;
+ constraint addr_range
+ {
+ (atype == low ) -> addr inside { [0 : 15] };
+ (atype == mid ) -> addr inside { [16 : 127]};
+ (atype == high) -> addr inside {[128 : 255]};
+ }
+ //
+endclass // MyBus
+
+// same example, with verilog mode indenting, Cexp indent = 3
+class MyBus extends Bus;
+ rand AddrType atype;
+ constraint addr_range
+ {
+ (atype == low ) -> addr inside { [0 : 15] };
+ (atype == mid ) -> addr inside { [16 : 127]};
+ (atype == high) -> addr inside {[128 : 255]};
+ }
+ //
+endclass // MyBus
+
+// same example, with verilog mode indenting, Cexp indent = 0
+class MyBus extends Bus;
+ rand AddrType atype;
+ constraint addr_range
+ {
+ (atype == low ) -> addr inside { [0 : 15] };
+ (atype == mid ) -> addr inside { [16 : 127]};
+ (atype == high) -> addr inside {[128 : 255]};
+ }
+endclass // MyBus
+
+// covergroup example from IEEE pg. 317
+covergroup cg @(posedge clk );
+ a : coverpoint v_a {
+ bins a1 = { [0:63] };
+ bins a2 = { [64:127] };
+ bins a3 = { [128:191] };
+ bins a4 = { [192:255] };
+ }
+ b : coverpoint v_b {
+ bins b1 = {0};
+ bins b2 = { [1:84] };
+ bins b3 = { [85:169] };
+ bins b4 = { [170:255] };
+ }
+ //
+ c : cross a, b
+ {
+ bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
+ bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
+ bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
+ }
+endgroup
+
+// here is the same code with verilog-mode indenting
+// covergroup example from IEEE pg. 317
+covergroup cg @(posedge clk );
+ a : coverpoint v_a
+ {
+ bins a1 = { [0:63] };
+ bins a2 = { [64:127] };
+ bins a3 = { [128:191] };
+ bins a4 = { [192:255] };
+ }
+ // foo
+ b : coverpoint v_b
+ {
+ bins b1 = {0};
+ bins b2 = { [1:84] };
+ bins b3 = { [85:169] };
+ bins b4 = { [170:255] };
+ }
+ c : cross a, b
+ {
+ bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
+ bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
+ bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
+ }
+endgroup
+
+module fool;
+
+ always @(posedge clk) begin
+ if(!M_select)
+ xferCount < = 8'd0;
+ else
+ case (condition[1 :0])
+ 2'b00 : xferCount <= xferCount;
+ 2'b01 : xferCount <= xferCount - 8'd1;
+ 2'b10 : xferCount <= xferCount + 8'd1;
+ 2'b11 : xferCount <= xferCount;
+ endcase // case (condition[1:0])
+ end
+ // But not this :
+ always @(posedge clk) begin
+ if(!M_select)
+ xferCount < = 8'd0;
+ else
+ case ({M_seqAddr,OPB_xferAck})
+ 2'b00 : xferCount <= xferCount;
+ 2'b01 : xferCount <= xferCount - 8'd1;
+ 2'b10 : xferCount <= xferCount + 8'd1;
+ 2'b11 : xferCount <= xferCount;
+ endcase // case ({M_seqAddr,OPB_xferAck})
+ end // always @ (posedge clk)
+
+endmodule // fool
+
+module foo;
+ initial begin
+ k = 10;
+ std::randomize(delay) with { (delay>=1000 && delay<=3000); };
+ j = 9;
+ end
+endmodule // foo
+
+
+// Issue 324 - constraint indentation is not correct
+// This checks for indentation around { and } inside constraint contents
+class myclass;
+ constraint c {
+ foreach(items[i]) {
+ if(write) {
+ items[i].op_code == WRITE;
+ } else if(read) {
+ items[i].op_code == READ;
+ }
+ }
+ }
+endclass // myclass
diff --git a/tests_ok/indent_constraint2.v b/tests_ok/indent_constraint2.v
new file mode 100644
index 0000000..60a343c
--- /dev/null
+++ b/tests_ok/indent_constraint2.v
@@ -0,0 +1,25 @@
+
+constraint Cepon_gate_random::grant_relations_c {
+ foreach (grant_relation_m[index]) {
+ if ((index == 0) && (last_start_time_m < time_stamp_m+`MINIMUM_TIME_TO_GATE)) grant_relation_m[index] == EPON_GATE_IN_ORDER;
+
+ else {
+
+ grant_relation_m[index] dist {
+ EPON_GATE_IN_ORDER :/55,
+ EPON_GATE_1ST_CONTAINS_2ND :/5,
+ EPON_GATE_2ND_CONTAINS_1ST :/5,
+ EPON_GATE_1ST_START_2ND_START :/5,
+ EPON_GATE_2ND_START_1ST_START :/5,
+ EPON_GATE_NO_GAP_1ST :/5,
+ EPON_GATE_NO_GAP_2ND :/5,
+ EPON_GATE_1CC_GAP :/5,
+ EPON_GATE_1CC_INTERLEAVE :/5,
+ EQUAL :/5
+ };
+
+ }
+
+ }
+
+}
diff --git a/tests_ok/indent_constraint3.v b/tests_ok/indent_constraint3.v
new file mode 100644
index 0000000..78044b5
--- /dev/null
+++ b/tests_ok/indent_constraint3.v
@@ -0,0 +1,30 @@
+//bug433
+
+class data;
+ rand integer data1;
+ rand integer data2,data3;
+ rand reg [31:0] foo;
+
+ constraint basic_c {
+ //empty constraint
+ }
+
+ constraint complex_c {
+ data1 <= 100;
+ foo inside {[40:999]};
+ if(foo < 87)
+ data2 == 10;
+ if(data2 == 76) {
+ data3 == 8;
+ }
+ }
+
+ constraint implication_c {
+ data1 == 10 -> data3 >= -1;
+ }
+
+ function new();
+ data1 = 0;
+ data2 = 78;
+ endfunction // new
+endclass // data
diff --git a/tests_ok/indent_covergroup.v b/tests_ok/indent_covergroup.v
new file mode 100644
index 0000000..1be3ab4
--- /dev/null
+++ b/tests_ok/indent_covergroup.v
@@ -0,0 +1,46 @@
+module coverage;
+ enum { red, green, blue } color;
+ covergroup foo @(posedge clk);
+ c : coverpoint color;
+ c : coverpoint color;
+ c : coverpoint color;
+ c : coverpoint color;
+ endgroup // foo
+
+ foo = bar;
+
+ sequence bar
+ b = c;
+ endsequence // bar
+ j = taskt;
+ function foo;
+ begin
+ foo = 1;
+ end
+ endfunction // foo
+
+ randsequence bar
+ b = c;
+ endsequence // bar
+
+ case (foo)
+ 1: a;
+ 2:b;
+ endcase // case (foo)
+
+ casex (foo)
+ 1: a;
+ 2:b;
+ endcase // case (foo)
+
+ casez (foo)
+ 1: a;
+ 2:b;
+ endcase // case (foo)
+
+ randcase (foo)
+ 1: a;
+ 2:b;
+ endcase // case (foo)
+
+endmodule // coverage
diff --git a/tests_ok/indent_coverpoint.v b/tests_ok/indent_coverpoint.v
new file mode 100644
index 0000000..872af4e
--- /dev/null
+++ b/tests_ok/indent_coverpoint.v
@@ -0,0 +1,29 @@
+
+// here is the same code with verilog-mode indenting
+// covergroup example from IEEE pg. 317
+covergroup cg @(posedge clk);
+ a: coverpoint v_a {
+ bins a1 = { [0:63] };
+ bins a2 = { [64:127] };
+ bins a3 = { [128:191] };
+ bins a4 = { [192:255] };
+ }
+ b: coverpoint v_b iff ( g )
+ {
+ bins b1 = {0};
+ bins b2 = { [1:84] };
+ bins b3 = { [85:169] };
+ bins b4 = { [170:255] };
+ }
+ c: coverpoint v_c iff ( !g ) {
+ bins c1 = {0};
+ bins c2 = { [1:84] };
+ bins c3 = { [85:169] };
+ bins c4 = { [170:255] };
+ }
+ d: cross a , b, c {
+ bins c1 = ! binsof(a) intersect {[100:200]}; // 4 cross products
+ bins c2 = binsof(a.a2) || binsof(b.b2); // 7 cross products
+ bins c3 = binsof(a.a1) && binsof(b.b4); // 1 cross product
+ }
+endgroup
diff --git a/tests_ok/indent_decl-1.v b/tests_ok/indent_decl-1.v
new file mode 100644
index 0000000..8a5bcc4
--- /dev/null
+++ b/tests_ok/indent_decl-1.v
@@ -0,0 +1,27 @@
+module soft_rst
+ (
+ // System clock and reset
+ input clk,
+ input rst_n,
+
+ // Interface to software land
+ input req_soft_rst, // Soft reset request
+ output soft_rst_dne, // Soft reset done
+
+ // Interface to other modules
+ output dma_halt, // Reset pending, halt activity
+ input tx_quiet, // TX side is dormant
+ input rx_quiet, // RX side is dormant
+ input c,
+ output soft_rst, // Soft (sync) reset to VC3 side
+ output hs_async_rst_n // Async reset to host side
+ );
+
+ reg [1:0] state;
+
+ reg [1:0] IDLE = 2'h0,
+ HALT = 2'h1,
+ RST = 2'h2,
+ DONE = 2'h3;
+
+endmodule // soft_rst
diff --git a/tests_ok/indent_decl.v b/tests_ok/indent_decl.v
new file mode 100644
index 0000000..67793db
--- /dev/null
+++ b/tests_ok/indent_decl.v
@@ -0,0 +1,9 @@
+module foo;
+ input a;
+ input b;
+ input [1:0] cfg_dev_i; // Config Device: 0b00 = Pangu, 0b01 = Switch
+ output switch_idsel_o; // Switch PCI IDSEL
+ output pangu_idsel_o; // Pangu PCI IDSEL
+ output wire g;
+ inout wire h;
+endmodule // foo
diff --git a/tests_ok/indent_directives.v b/tests_ok/indent_directives.v
new file mode 100644
index 0000000..3aa3c36
--- /dev/null
+++ b/tests_ok/indent_directives.v
@@ -0,0 +1,69 @@
+module foo;
+`ifdef LABEL_A
+ CHIP CPU (
+ .clkin(clkin),
+ `ifdef LABEL_B
+ .bclko(bclko),
+ `endif
+ .cmode(cmode),
+ );
+ input sysclk;
+ `ifdef LABEL_B
+ input bclko;
+ `endif
+ input cmode;
+`endif
+
+ // instead of:
+
+`ifdef LABEL_A
+ CHIP CPU (
+ .clkin(clkin),
+ `ifdef LABEL_B
+ .bclko(bclko),
+ `endif
+ .cmode(cmode),
+ );
+ input sysclk;
+ `ifdef LABEL_B
+ input bclko;
+ `endif
+ input cmode;
+`endif // `ifdef LABEL_A
+ reg a,b;
+`ifdef A
+ always @(a) begin
+ b = a; // asfSDfsdfsasa
+ b = a; // asfSDfsdfsasa
+ b = a; // asfSDfsdfsasa //
+ b = a; // asfSDfsdfsasa //
+ b = a; // asfSDfsdfsasa //
+ b = a; // asfSDfsdfsasa //
+ b = a; // asfSDfsdfsasa //
+ b = a; // asfSDfsdfsasa //
+ b = a; // asfSDfsdfsasa //
+ end
+`elsif B
+ always @(b) begin
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa //
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa //
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa //
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa
+ a = b; // asfSDfsdfsasa //
+ end
+`else // !`elsif B
+ always @(a or b) begin
+ a <= b;
+ b <= a;
+ end
+`endif // !`elsif B
+
+
+endmodule // foo
diff --git a/tests_ok/indent_dpi.v b/tests_ok/indent_dpi.v
new file mode 100644
index 0000000..e81f83b
--- /dev/null
+++ b/tests_ok/indent_dpi.v
@@ -0,0 +1,29 @@
+import "DPI-C" function string fna (input string str1);
+export "DPI" c_identifier = task task_identifier;
+import "DPI" context function string fnb (input string str1);
+
+module testbench;
+
+ import "DPI" function string fn1 (input string str1);
+ import "DPI-C" function void dpiWriteArray (input bit[7:0] data[]);
+ import "DPI-C" pure function void dpiReadArray (output bit[7:0] data[]);
+ import "DPI-C" function void dpiAesSetKey ( int key_high_u int key_high_l,
+ int key_low_u, int key_low_l );
+ import "DPI-C" function void dpiAesSetIV (int iv_high_u, int iv_high_l,
+ int iv_low_u, int iv_low_l);
+ import "DPI-C" function void dpiAesSetSkip (int skip);
+ import "DPI-C" function void dpiAesCBCEncrypt ();
+
+ logic a;
+endmodule // testbench
+
+/*
+ package ref_model;
+ import "DPI-C" xx_write_bmp_file =
+ function void write_bmp_file(input string filename);
+
+ import "DPI-C" xx_demosaic =
+ function void demosaic(regs regs,
+ inout pix_buf imgR, imgG, imgB);
+endpackage
+ */
diff --git a/tests_ok/indent_foreach.v b/tests_ok/indent_foreach.v
new file mode 100644
index 0000000..7eb2778
--- /dev/null
+++ b/tests_ok/indent_foreach.v
@@ -0,0 +1,14 @@
+`ifndef FOO
+ `define FOO
+module foo;
+ reg [31:0] payload [255:0];
+ reg [7:0] index;
+
+ always @ (b) begin
+ foreach (1) begin
+ @(router.cb);
+ end // foreach (1)
+ end // always @ (b)
+endmodule // foo
+`else // !`ifndef FOO
+`endif // !`ifndef FOO
diff --git a/tests_ok/indent_fork_join_any.v b/tests_ok/indent_fork_join_any.v
new file mode 100644
index 0000000..c422745
--- /dev/null
+++ b/tests_ok/indent_fork_join_any.v
@@ -0,0 +1,27 @@
+module fork_join_any;
+ initial begin
+ fork
+ begin
+ fork
+ begin
+ end
+ join_any
+ a = b;
+ disable fork;
+ blah;
+ wait fork;
+ blah;
+ end
+ join_any
+ foo = bar;
+ end // initial fork
+endmodule // fork_join_any
+
+class x;
+ task y;
+ a = b;
+ wait fork;
+ $display("I'm indented too far");
+ endtask // y
+endclass // x
+
diff --git a/tests_ok/indent_formfeed.v b/tests_ok/indent_formfeed.v
new file mode 100644
index 0000000..1d06580
--- /dev/null
+++ b/tests_ok/indent_formfeed.v
@@ -0,0 +1,9 @@
+
+module x;
+
+ foo;
+endmodule
+
+bar;
+module z;
+endmodule
diff --git a/tests_ok/indent_function.v b/tests_ok/indent_function.v
new file mode 100644
index 0000000..2614d06
--- /dev/null
+++ b/tests_ok/indent_function.v
@@ -0,0 +1,50 @@
+module t;
+
+endmodule
+class C;
+ function int f();
+ f = 17;
+ endfunction
+ extern function int g();
+ virtual function int f();
+ a;
+ endfunction // int
+ // pure virtual functions have no endfunction.
+ C a;
+ initial begin
+ $display("hello world");
+ $display("a of f is %d, g is %d", a.f(),a.g());
+ end
+ function int C::g();
+ g = 18;
+ endfunction // g
+ // pure virtual functions have no endfunction.
+endclass // C
+
+class pure_virt_func_class;
+ pure virtual function string pure_virt_func();
+ pure virtual function string pure_virt_func();
+ pure virtual function string pure_virt_func();
+ extern pure virtual task t();
+ pure virtual task t();
+ virtual task t();
+ /* body */
+ endtask // t
+ virtual function f();
+ /* body */
+ endfunction // f
+endclass // pure_virt_func_class
+
+class base_test extends uvm_test;
+ `uvm_component_utils(base_test)
+ typedef virtual my_if my_vif_t;
+ // A function definition starting with the virtual keyword should not be
+ // detected as a declaration. This issue is seen when an attempt to indent
+ // each declaration is done (when the verilog-auto-lineup variable is set
+ // to 'declarations).
+ // In other words, the "function" in "virtual function" below must not be
+ // aligned with "my_if" in the "typedef virtual my_if.." line above.
+ virtual function void start_of_simulation_phase(uvm_phase phase);
+ super.start_of_simulation_phase(phase);
+ endfunction : start_of_simulation_phase
+endclass : base_test
diff --git a/tests_ok/indent_generate.v b/tests_ok/indent_generate.v
new file mode 100644
index 0000000..1880338
--- /dev/null
+++ b/tests_ok/indent_generate.v
@@ -0,0 +1,15 @@
+module test();
+
+ reg [3:0] x;
+
+ genvar i;
+ generate
+ for(i=0; i<4; i=i+1) begin:a
+ always @(*) begin
+ x[i] = 1;
+ end
+ wire y = 0;
+ end
+ endgenerate
+endmodule // test
+
diff --git a/tests_ok/indent_if.v b/tests_ok/indent_if.v
new file mode 100644
index 0000000..add652b
--- /dev/null
+++ b/tests_ok/indent_if.v
@@ -0,0 +1,7 @@
+module foo;
+ initial
+ if (cond1) begin
+ sig1 <= {4'h0, 4'hc};
+ sig2 <= 8'hff;
+ end // if (cond1)
+endmodule // foo
diff --git a/tests_ok/indent_if2.v b/tests_ok/indent_if2.v
new file mode 100644
index 0000000..b60e4eb
--- /dev/null
+++ b/tests_ok/indent_if2.v
@@ -0,0 +1,23 @@
+module foo;
+ always@(*)
+ begin
+ if(state==LBT_STATE)
+ begin
+ if(something)
+ begin
+ end
+ else
+ begin
+ end
+ end
+ else if(state==HS_0_STATE)
+ begin
+ end
+ else if(state==STATE_4)
+ begin
+ end
+ else
+ begin
+ end
+ end // always@ (*)
+endmodule // foo
diff --git a/tests_ok/indent_ifdef.v b/tests_ok/indent_ifdef.v
new file mode 100644
index 0000000..8be7d87
--- /dev/null
+++ b/tests_ok/indent_ifdef.v
@@ -0,0 +1,46 @@
+module test(out);
+ output out;
+`define wow
+`define nest_one
+`define second_nest
+`define nest_two
+`ifdef wow
+ initial $display("wow is defined");
+ `ifdef nest_one
+ initial $display("nest_one is defined");
+ `ifdef nest_two
+ initial $display("nest_two is defined");
+ `else
+ initial $display("nest_two is not defined");
+ `endif
+ `else
+ initial $display("nest_one is not defined");
+ `endif
+`else
+ initial $display("wow is not defined");
+ `ifdef second_nest
+ initial $display("second_nest is defined");
+ `else
+ initial $display("second_nest is not defined");
+ `endif
+`endif
+endmodule
+
+
+// Local Variables:
+// verilog-auto-lineup: all
+// verilog-auto-endcomments: t
+// verilog-auto-indent-on-newline: t
+// verilog-auto-lineup: all
+// verilog-auto-newline: nil
+// verilog-case-indent: 2
+// verilog-highlight-p1800-keywords: nil
+// verilog-indent-begin-after-if: t
+// verilog-indent-level: 2
+// verilog-indent-level-behavioral: 2
+// verilog-indent-level-declaration: 2
+// verilog-indent-level-directive: 2
+// verilog-indent-level-module: 2
+// verilog-minimum-comment-distance: 40
+// verilog-tab-always-indent: t
+// End:
diff --git a/tests_ok/indent_ifdef_generate.v b/tests_ok/indent_ifdef_generate.v
new file mode 100644
index 0000000..84e643d
--- /dev/null
+++ b/tests_ok/indent_ifdef_generate.v
@@ -0,0 +1,32 @@
+// Issue 559 - nested ifdef with generate indentation bug
+module m;
+
+`ifndef DDR_PT_GATE_SIM
+ generate
+ /***************** Assertions for DP HM signals ***************************************************************/
+ for (dp_id=0; dp_id <PDDR_NUM_DP; dp_id++) begin: DPConnectGen
+
+ if (PDDR_DP_HV[dp_id]) begin: VGen
+ `ifdef IO_DDR3
+ // CR?V connectivity for DP HM
+ DP_CRN0V15_Connection: assert property (ConnectProp(1'b1, `PHYTOP.CRN0V[dp_id+PGEN_NUM_ADR], `PHYTOP.DPBundleGen[dp_id].u_DpBundle.`DPV_INST.CRN0V15))
+ else begin
+ $display ($stime, " ERROR: CRN0V[%0d] to DP HM %0d CRN0V15 Connection Failed", dp_id+PGEN_NUM_ADR, dp_id);
+
+ postError();
+
+ end // else: !assert property
+ DP_CRN1V15_Connection: assert property (ConnectProp(1'b1, `PHYTOP.CRN1V[dp_id+PGEN_NUM_ADR], `PHYTOP.DPBundleGen[dp_id].u_DpBundle.`DPV_INST.CRN1V15))
+ else begin
+ $display ($stime, " ERROR: CRN1V[%0d] to DP HM %0d CRN1V15 Connection Failed", dp_id+PGEN_NUM_ADR, dp_id);
+
+ postError();
+
+ end // else: !assert property
+ end // block: VGen
+ `endif // `ifdef IO_DDR3
+ end // block: DPConnectGen
+ endgenerate
+`endif
+
+endmodule // m
diff --git a/tests_ok/indent_immediate_assertion.sv b/tests_ok/indent_immediate_assertion.sv
new file mode 100644
index 0000000..6c10d3f
--- /dev/null
+++ b/tests_ok/indent_immediate_assertion.sv
@@ -0,0 +1,27 @@
+// Issue 949 - Indenting SVA assert final block broken
+module tb;
+ begin
+ a0: assert final (data0 == 1) else
+ $error;
+ end
+endmodule
+
+
+// Now check for other types of immediate assertion
+module tb;
+ always @(abcd) begin
+
+ // simple immediate assert statement
+ assert (xyz) a = b;
+
+ // deferred immediate cover statement w/ #0
+ if(x)
+ cover #0 (efg)
+ $display("covered");
+
+ // deferred immedate assume statement w/ final
+ assume final (abcd) else
+ $display();
+ end
+
+endmodule
diff --git a/tests_ok/indent_importfunction.v b/tests_ok/indent_importfunction.v
new file mode 100644
index 0000000..18e9d35
--- /dev/null
+++ b/tests_ok/indent_importfunction.v
@@ -0,0 +1,8 @@
+module toto (input logic dummy);
+ import "DPI-C" pure function real fabs (input real a);
+ import "DPI-C" context function real fcons (input real a);
+ import "DPI-C" string_sv2c = task string();
+ import "DPI-C" int_sv2c = task intsv2c();
+ import "DPI-C" context int_sv2c = task intsv2cont();
+ logic a; // wrong indentation
+endmodule // wrong indentation
diff --git a/tests_ok/indent_interface.v b/tests_ok/indent_interface.v
new file mode 100644
index 0000000..4413bc4
--- /dev/null
+++ b/tests_ok/indent_interface.v
@@ -0,0 +1,27 @@
+interface simple_bus; // Define the interface
+ logic req, gnt;
+ logic [7:0] addr, data;
+ logic [1:0] mode;
+ logic start, rdy;
+endinterface: simple_bus
+module memMod(
+ simple_bus a, // Access the simple_bus interface
+ input bit clk);
+
+ logic avail;
+ // When memMod is instantiated in module top, a.req is the req
+ // signal in the sb_intf instance of the simple_bus interface
+ always @(posedge clk)
+ a.gnt <= a.req & avail;
+endmodule
+module cpuMod(simple_bus b, input bit clk);
+ always @(b) begin
+ end
+endmodule
+module top;
+ logic clk = 0;
+ simple_bus sb_intf(); // Instantiate the interface
+ memMod mem(sb_intf, clk); // Connect the interface to the module instance
+ cpuMod cpu(.b(sb_intf), .clk(clk)); // Either by position or by name
+endmodule
+
diff --git a/tests_ok/indent_linefeed.v b/tests_ok/indent_linefeed.v
new file mode 100644
index 0000000..1e373d2
--- /dev/null
+++ b/tests_ok/indent_linefeed.v
@@ -0,0 +1,18 @@
+module foo;
+ input a,b;
+
+ always @(a) begin
+ b <= #10 ~ a;
+ end
+endmodule // foo
+
+module bar;
+ //
+ input a,b;
+
+ always @(a) begin //
+ b <= #10 ~ a;
+
+ a;
+ end
+endmodule // foo
diff --git a/tests_ok/indent_lineup_inlists.v b/tests_ok/indent_lineup_inlists.v
new file mode 100644
index 0000000..d7bf442
--- /dev/null
+++ b/tests_ok/indent_lineup_inlists.v
@@ -0,0 +1,25 @@
+module soft_rst (
+ // System clock and reset
+ input clk,
+ input rst_n,
+
+ // Interface to software land
+ input req_soft_rst, // Soft reset request
+ output soft_rst_dne, // Soft reset done
+
+ // Interface to other modules
+ output dma_halt, // Reset pending, halt activity
+ input tx_quiet, // TX side is dormant
+ input rx_quiet, // RX side is dormant
+ output soft_rst, // Soft (sync) reset to VC3 side
+ output hs_async_rst_n // Async reset to host side
+ );
+
+ reg [1:0] state;
+
+ localparam [1:0] IDLE = 2'h0,
+ HALT = 2'h1,
+ RST = 2'h2,
+ DONE = 2'h3;
+
+endmodule // soft_rst
diff --git a/tests_ok/indent_lineup_mode_all.v b/tests_ok/indent_lineup_mode_all.v
new file mode 100644
index 0000000..b7ad06a
--- /dev/null
+++ b/tests_ok/indent_lineup_mode_all.v
@@ -0,0 +1,19 @@
+module test (pci_ack, reg_wr, reg_sel, clk, rst);
+ input [3:0] pci_ack;
+ input reg_wr;
+ input reg_sel;
+ input clk;
+ input rst;
+ initial begin
+ foo;
+ bar;
+ x <= y;
+ longish <= alsolongish;
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-lineup: all
+// End:
+
diff --git a/tests_ok/indent_lineup_mode_assignments.v b/tests_ok/indent_lineup_mode_assignments.v
new file mode 100644
index 0000000..28d8e10
--- /dev/null
+++ b/tests_ok/indent_lineup_mode_assignments.v
@@ -0,0 +1,18 @@
+module test (pci_ack, reg_wr, reg_sel, clk, rst);
+ input [3:0] pci_ack;
+ input reg_wr;
+ input reg_sel;
+ input clk;
+ input rst;
+ initial begin
+ foo;
+ bar;
+ x <= y;
+ longish <= alsolongish;
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-lineup: assignments
+// End:
diff --git a/tests_ok/indent_lineup_mode_declarations.v b/tests_ok/indent_lineup_mode_declarations.v
new file mode 100644
index 0000000..42bbc42
--- /dev/null
+++ b/tests_ok/indent_lineup_mode_declarations.v
@@ -0,0 +1,19 @@
+module test (pci_ack, reg_wr, reg_sel, clk, rst);
+ input [3:0] pci_ack;
+ input reg_wr;
+ input reg_sel;
+ input clk;
+ input rst;
+ initial begin
+ foo;
+ bar;
+ x <= y;
+ longish <= alsolongish;
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-lineup: declarations
+// End:
+
diff --git a/tests_ok/indent_lineup_mode_none.v b/tests_ok/indent_lineup_mode_none.v
new file mode 100644
index 0000000..4d8ca93
--- /dev/null
+++ b/tests_ok/indent_lineup_mode_none.v
@@ -0,0 +1,19 @@
+module test (pci_ack, reg_wr, reg_sel, clk, rst);
+ input [3:0] pci_ack;
+ input reg_wr;
+ input reg_sel;
+ input clk;
+ input rst;
+ initial begin
+ foo;
+ bar;
+ x <= y;
+ longish <= alsolongish;
+ end
+
+endmodule
+
+// Local Variables:
+// verilog-auto-lineup: nil
+// End:
+
diff --git a/tests_ok/indent_macro_braces.v b/tests_ok/indent_macro_braces.v
new file mode 100644
index 0000000..a8064bb
--- /dev/null
+++ b/tests_ok/indent_macro_braces.v
@@ -0,0 +1,9 @@
+// bug 433 - Check indentation around macro (uvm/ovm/vmm) with curly-brace
+// internals (these look like a constraint)
+
+module m;
+ if(x)
+ `ovm_do_with(my,
+ { y == 1;
+ z == 2; });
+endmodule
diff --git a/tests_ok/indent_macro_comment.v b/tests_ok/indent_macro_comment.v
new file mode 100644
index 0000000..0c3db94
--- /dev/null
+++ b/tests_ok/indent_macro_comment.v
@@ -0,0 +1,41 @@
+// issue 935 - Incorrect indentation after multi-line `define macro
+`ifndef _ABC
+ `define _ABC
+
+ `define TEMPA 1
+
+// CORRECT INDENTATION
+
+ `define DEF1 { "a" \
+ , "b" \
+ }
+
+// Incorrect indentation (v1) after multi-line macro definition above
+
+ `define TEMPB (`TEMPA >= 0 ? 0 : 1)
+
+// Incorrect indentation (v1) *strangely, not yet affected by the >= chars above*
+
+ `define DEF2 { "a" \
+ , "b" \
+ }
+
+// Incorrect indentation (v2) *NOW aligns to the
+// >= sign in `define TEMPB above (which it should not)
+// Looks like the multi-line macro definition DEF2
+// above caused this second version of incorrect
+// indentation*
+
+ `define TEMPC ((`TEMPA + 1_000_000) >= 0 ? 0 : 1)
+
+// BACK TO Incorrect indentation (v1)!
+
+ `define DEF3 { "a" \
+ , "b" \
+ }
+
+// BACK TO Incorrect indentation (v2)! Surprisingly
+// the >= sign in `define TEMPC macro did not affect
+// the indentation this time; but the indentation
+// returned to (v2) as set by that sign in `define TEMPB
+`endif
diff --git a/tests_ok/indent_mailbox.v b/tests_ok/indent_mailbox.v
new file mode 100644
index 0000000..377d862
--- /dev/null
+++ b/tests_ok/indent_mailbox.v
@@ -0,0 +1,13 @@
+class Driver;
+ mailbox mbox; // <= not highlighted.
+ semaphore smtx;
+ int id;
+ virtual Rx_if Rx;
+
+ function new(mailbox mbox, int id, virtual Rx_if.TB Rx);
+ this.mbox = mbox;
+ this.id = i;
+ this.Rx = Rx;
+ endfunction // new
+endclass // Driver
+
diff --git a/tests_ok/indent_modansi.v b/tests_ok/indent_modansi.v
new file mode 100644
index 0000000..4bb407c
--- /dev/null
+++ b/tests_ok/indent_modansi.v
@@ -0,0 +1,16 @@
+module testmodule(
+ input wire [1:0] pin1,
+ input wire pin2,
+ input wire [1:0] pin3,
+ input wire pin4,
+ output wire pin5,
+ output wire [10:0] pin6,
+ output reg pin7,
+ output reg [1:0] pin8
+ );
+ initial begin
+ $display("alls well that ends well");
+ end
+endmodule // testmodule
+
+
diff --git a/tests_ok/indent_modport.v b/tests_ok/indent_modport.v
new file mode 100644
index 0000000..20c71b0
--- /dev/null
+++ b/tests_ok/indent_modport.v
@@ -0,0 +1,6 @@
+module foo;
+ modport foo_mp;
+ modport foo_mp1(a);
+ modport foo_mp2(clocking bar_cb);
+ a;
+endmodule // foo
diff --git a/tests_ok/indent_named_assert.v b/tests_ok/indent_named_assert.v
new file mode 100644
index 0000000..9b96999
--- /dev/null
+++ b/tests_ok/indent_named_assert.v
@@ -0,0 +1,9 @@
+module test;
+ property p_test;
+ a |-> b;
+ endproperty : p_test
+ assert property (p_test);
+ a_test : assert property (p_test);
+ a = b; // this and following lines are not properly indented
+ foo;
+endmodule // test
diff --git a/tests_ok/indent_ovm.v b/tests_ok/indent_ovm.v
new file mode 100644
index 0000000..919bec3
--- /dev/null
+++ b/tests_ok/indent_ovm.v
@@ -0,0 +1,70 @@
+module ovm;
+class simple_item extends ovm_sequence_item;
+ rand int unsigned addr;
+ rand int unsigned data;
+ rand int unsigned delay;
+ constraint c1 { addr < 16'h2000; }
+ constraint c2 { data < 16'h1000; }
+ // OVM automation macros for general objects
+ `ovm_object_utils_begin(simple_item)
+ a = b;
+ c = d;
+ `ovm_field_int(addr, OVM_ALL_ON)
+ `ovm_field_int(data, OVM_ALL_ON)
+ `ovm_field_int(delay, OVM_ALL_ON)
+ `ovm_object_utils_end
+ // Constructor
+ function new (string name = "simple_item");
+ super.new(name);
+ endfunction : new
+endclass : simple_item
+class mydata extends ovm_object;
+
+ string str;
+ mydata subdata;
+ int field;
+ myenum e1;
+ int queue[$];
+ `ovm_object_utils(mydata)
+ `ovm_object_utils_begin(mydata) //requires ctor with default args
+ `ovm_field_string(str, OVM_DEFAULT)
+ `ovm_field_object(subdata, OVM_DEFAULT)
+ `ovm_field_int(field, OVM_DEC) //use decimal radix
+ `ovm_field_enum(myenum, e1, OVM_DEFAULT)
+ `ovm_field_queue_int(queue, OVM_DEFAULT)
+ `ovm_object_utils_end
+ `ovm_object_param_utils_begin(mydata) //requires ctor with default args
+ `ovm_field_string(str, OVM_DEFAULT)
+ `ovm_field_object(subdata, OVM_DEFAULT)
+ `ovm_field_int(field, OVM_DEC) //use decimal radix
+ `ovm_field_enum(myenum, e1, OVM_DEFAULT)
+ `ovm_field_queue_int(queue, OVM_DEFAULT)
+ `ovm_object_utils_end
+endclass
+class my_trans extends ovm_sequence_item;
+
+ rand bit [127:0] data [];
+
+ //---> Configuration
+ `ovm_object_utils_begin(my_trans)
+ `ovm_field_array_int ( data, OVM_ALL_ON)
+ `ovm_object_utils_end
+
+ function new (string name = "my_trans", ovm_sequencer_base sequencer = null, ovm_sequence parent_seq = null);
+ super.new(name, sequencer, parent_seq);
+ endfunction : new
+endclass : my_trans
+endmodule // ovm
+
+module tt;
+
+ initial begin
+ while (1) begin
+ `ovm_do_with(aa, {bb == 0;})
+ `ovm_do(cc)
+ `ovm_do(cc)
+ end // while (1)
+ end // initial begin
+
+endmodule // tt
+
diff --git a/tests_ok/indent_param.v b/tests_ok/indent_param.v
new file mode 100644
index 0000000..b7b82d1
--- /dev/null
+++ b/tests_ok/indent_param.v
@@ -0,0 +1,15 @@
+module example_block
+ #(
+ parameter PARAM = 1,
+ FOO = 2,
+ BARFLUG = 4,
+ G = 5,
+ )
+ (// I/O
+ input reset_n,
+ input clk
+ input a, b,
+ output reg c
+ );
+endmodule
+
diff --git a/tests_ok/indent_preproc.v b/tests_ok/indent_preproc.v
new file mode 100644
index 0000000..6dffdfd
--- /dev/null
+++ b/tests_ok/indent_preproc.v
@@ -0,0 +1,27 @@
+
+
+aa;
+`__FILE__
+`__LINE__
+`celldefine
+`end_keywords
+`resetall
+`unconnected_drive
+`undefineall
+
+`ifdef AA
+`else
+`endif
+`ifndef AA
+`elsif FOO
+`endif
+
+`begin_keywords "FOO"
+`undef FOO
+
+`line 2 "xx" 2
+`include "YY"
+`include <YY>
+`pragma endofline
+`timescale 10ns/10ps
+`define foo bar
diff --git a/tests_ok/indent_preproc_label.v b/tests_ok/indent_preproc_label.v
new file mode 100644
index 0000000..8bcea94
--- /dev/null
+++ b/tests_ok/indent_preproc_label.v
@@ -0,0 +1,16 @@
+// bug861/862 - named coverpoint inside/near pre-processor macro confuses indentation
+module m;
+
+`ifdef ASSERT_ON
+ asrt_001: assert property(p_001);
+ asrt_002: assert property(p_002);
+ asrt_003: assert property(p_003);
+`endif
+
+`ifdef COVER_ON
+ chk_001: cover property(p_001);
+ chk_002: cover property(p_002);
+ chk_003: cover property(p_003);
+`endif
+
+endmodule
diff --git a/tests_ok/indent_property.v b/tests_ok/indent_property.v
new file mode 100644
index 0000000..3ed464c
--- /dev/null
+++ b/tests_ok/indent_property.v
@@ -0,0 +1,65 @@
+module foo();
+ initial begin
+ a;
+ end
+
+ always @(a) begin
+ b;
+ end
+ task a (a);
+ begin
+ a = f;
+ a = f;
+ d <= 89;
+ sdf = sdf;
+ adada = > asda;
+ d ->> g;
+ aasd <<<= 3;
+ ccc %= 6;
+ d *= b;
+ g -= c;
+ end
+ endtask // a
+
+
+ property p_3;
+ a = > ##3 !a;
+ a |=> ##1 !a;
+ a |-> ##2 !a;
+ endproperty
+ property p_2;
+ @(posedge clk) b |-> ##1 c;
+ endproperty
+ property p_1;
+ @(posedge clk) a |-> b;
+ endproperty
+
+ initial d;
+
+ // ap_1 assert property (p_1); FIXME
+ // ap_2 assert property (p_2);
+
+ property p_lane_output_change_on_input_change;
+ @(negedge test_clk)
+ disable iff (ana_byp == 0)
+ !$stable(lane_inputs) |-> !$stable(lane_outputs);
+ endproperty
+
+ // Issue #940 - '=' in |=> , #=#, and [=n] operators should not mis-indent next line of continued expression
+ property p_nonSequential;
+ a |-> b[=n] ##0
+ c;
+ endproperty
+
+ property p_nonOverlapFollowedBy;
+ a #=#
+ c;
+ endproperty
+
+ property p_nonBlockingImplication;
+ a |=> b[*n] ##0
+ c;
+ endproperty
+
+
+endmodule
diff --git a/tests_ok/indent_randcase.v b/tests_ok/indent_randcase.v
new file mode 100644
index 0000000..3d7ed68
--- /dev/null
+++ b/tests_ok/indent_randcase.v
@@ -0,0 +1,18 @@
+module aa;
+
+ int a,b,c;
+
+ initial begin
+ randcase
+ 10 : begin
+ a = 1;
+ end
+ 15 : begin
+ b = 0;
+ c = 5;
+ end
+ endcase // randcase
+
+ end // initial begin
+
+endmodule // a
diff --git a/tests_ok/indent_random.v b/tests_ok/indent_random.v
new file mode 100644
index 0000000..c52e7c7
--- /dev/null
+++ b/tests_ok/indent_random.v
@@ -0,0 +1,38 @@
+module top;
+ initial begin
+ // Test
+ $display("Hello world");
+ void'(std::randomize(foo) with {foo < 10;}; );
+ end
+endmodule // top
+/*
+ --------------------------
+
+ It also appears to have indentation problems with the following variation:
+
+ == The code: ==
+ */
+module top;
+
+ initial begin
+ // Test
+ $display("Hello world");
+ assert(std::randomize(foo) with {foo < 10;}; )
+ else $error("ERROR randomizing foo");
+ end
+endmodule // top
+/*
+
+ ------------------------------
+
+ Also tried the following (removed semicolon after closing-curly-brace), and got same result:
+ */
+
+module top;
+
+ initial begin
+ // Test
+ $display("Hello world");
+ void'(std::randomize(foo) with {foo < 10;} );
+ end
+endmodule // top
diff --git a/tests_ok/indent_struct.v b/tests_ok/indent_struct.v
new file mode 100644
index 0000000..addcb57
--- /dev/null
+++ b/tests_ok/indent_struct.v
@@ -0,0 +1,45 @@
+module foo;
+
+ a = { g + c; };
+ a = c;
+
+ typedef struct {
+ reg r;
+ ahb_op_t op; // Read, write, etc.
+ ahb_cycle_type_t cti; // Cycle type for bursts
+ ahb_incr_type_t incr; // Increment type (for bursts)
+ bit b;
+ reg r;
+ ahb_thingy a;
+ bit [31:2] addr; // Starting address
+ bit [3:0] byte_sel; // Byte lane select
+ int len; // Length of transfer
+ bit [31:0] data[0:7]; // Write data
+ } ahb_req_t;
+
+ struct {
+ reg f;
+ xyzzy b;
+ };
+ struct packed {
+ int a; // ok
+ };
+ struct packed signed {
+ int a; // woops
+ };
+ struct packed unsigned {
+ int a; // woops
+ };
+
+endmodule // foo
+
+module foo (
+ input a;
+ input c;
+ output d;
+ );
+ always @(a) g;
+
+
+
+endmodule // foo
diff --git a/tests_ok/indent_task.v b/tests_ok/indent_task.v
new file mode 100644
index 0000000..59cb44c
--- /dev/null
+++ b/tests_ok/indent_task.v
@@ -0,0 +1,92 @@
+module foo;
+
+ // for each additional in-air txmacphy byte
+ task nextTxByte();
+ TxByteCnt++;
+ TxLastByteTime = $time;
+ endtask // nextTxByte
+ task automatic blah();
+ t;
+ endtask // blah
+ function static foo();
+ foo = 1;
+ endfunction // foo
+ // start counting when txmacphy sees first in-air byte
+ task firstTxByte();
+ TxByteCnt = 1;
+ TxFirstByteTime = $time;
+ TxLastByteTime = $time;
+ endtask // firstTxByte
+
+ // outputs the overall performance of the RX path in Mbps (MBits per second)
+ task printRxPerformance();
+ integer ibps;
+ real Mbps;
+ if( RxByteCnt && systemTop.intMonitor.frgRxedCnt >= 2 ) begin
+ ibps =
+ (RxByteCnt*8*1000000000)/(RxLastByteTime-RxFirstByteTime);
+ Mbps = ibps/1000000;
+ $display("%t: %s - RX average performance: %fMbps (Mbits/sec)",
+ $time, myName, Mbps );
+ end
+ else
+ $display("%t: %s - Requires >= 2 RX frames in order to measure performance", $time, myName);
+
+ endtask // printRxPerformance
+
+endmodule // foo
+
+class a;
+ virtual function void foo();
+ foo = 2;
+ endfunction // void
+ extern function void bar();
+ function fred();
+ aaa;
+ endfunction // fred
+
+ task foo;
+ endtask // endtask
+
+ virtual task foo;
+ endtask // endtask
+
+ generate g;
+ endgenerate
+
+ covergroup g;
+ endgroup // g
+
+ property p;
+ endproperty
+
+ sequence s;
+ endsequence // s
+
+ clocking c;
+ endclocking // c
+
+ function f;
+ endfunction //
+
+ virtual function f;
+ endfunction //
+
+ protected function f;
+ endfunction //
+
+endclass // a
+
+class base_test extends uvm_test;
+ `uvm_component_utils(base_test)
+ typedef virtual my_if my_vif_t;
+ // A task definition starting with the virtual keyword should not be
+ // detected as a declaration. This issue is seen when an attempt to indent
+ // each declaration is done (when the verilog-auto-lineup variable is set
+ // to 'declarations).
+ // In other words, the "task" in "virtual task" below must not be
+ // aligned with "my_if" in the "typedef virtual my_if.." line above.
+ virtual task run_phase(uvm_phase phase);
+ super.run_phase(phase);
+ endtask // run_phase
+endclass // base_test
diff --git a/tests_ok/indent_task_func_decl.sv b/tests_ok/indent_task_func_decl.sv
new file mode 100644
index 0000000..4f1cebb
--- /dev/null
+++ b/tests_ok/indent_task_func_decl.sv
@@ -0,0 +1,90 @@
+typedef class burst_drv;
+
+class burst_drv extends vmm_xactor;
+
+ int EXECUTING;
+ int OBSERVED;
+ int SUB_OBSERVED;
+
+ protected burst_drv_cfg cfg;
+ local burst_drv_cfg reset_cfg;
+ protected burst_xn rx_factory;
+ local burst_xn reset_rx_factory;
+
+ burst_xn_channel in_chan;
+ burst_xn_channel obs_chan;
+
+ burst_xn tr_main; // Current transaction in main()
+ /* could have [extern] [virtual] [protected|local] task [static|automatic|] name (); */
+ /* If extern -> then it is complete; other wise it is not complete */
+ /* class could have:
+ class c
+ extern virtual static protected task t ();
+ endclass
+ task declaration could have
+ task static t();
+ endtask
+ */
+ class c;
+ endclass // c
+ function f();
+ g;
+ endfunction // f
+ generate g;
+ /* a lot of stuff */
+ endgenerate
+ task t();
+ /**/
+ /**/
+ endtask // t
+ protected virtual task pv_t();
+ /**/
+ endtask // pv_t
+
+ protected task p_t();
+ /* ACK*/
+ endtask // p_t
+ virtual task v_t();
+ /**/
+ endtask // v_t
+ virtual protected task vp_t();
+ /**/
+ endtask // vp_t
+ protected virtual task pv_t();
+ /**/
+ endtask // pv_t
+ extern task e_t();
+ extern virtual task ev_t();
+ extern protected task ep_t();
+ extern protected virtual task epv_t();
+ extern protected virtual task main();
+ generate g;
+ /**/
+ endgenerate
+
+ extern virtual function void reconfigure(burst_drv_cfg cfg);
+ extern virtual function void reset_xactor(reset_e rst_type = SOFT_RST);
+ extern virtual function new (
+ string inst,
+ int stream_id,
+ burst_drv_cfg cfg = null,
+ burst_xn_channel in_chan = null,
+ burst_xn_channel obs_chan = null,
+ burst_xn rx_factory = null);
+ virtual task start();
+ super.start();
+ this.tx_dma.start();
+ this.rx_dma.start();
+ endtask // start
+ task start();
+ super.start();
+ this.tx_dma.start();
+ this.rx_dma.start();
+ endtask // start
+ task static start();
+ super.start();
+ this.tx_dma.start();
+ this.rx_dma.start();
+ endtask // static
+endclass : burst_drv
+
diff --git a/tests_ok/indent_typedef.sv b/tests_ok/indent_typedef.sv
new file mode 100644
index 0000000..93f3daf
--- /dev/null
+++ b/tests_ok/indent_typedef.sv
@@ -0,0 +1,5 @@
+package p;
+ typedef enum {a, b} type_t;
+ typedef enum {TASK, TASK2} type2_t;
+ typedef enum {Package, Class} type3_t;
+endpackage
diff --git a/tests_ok/indent_unique_case-1.v b/tests_ok/indent_unique_case-1.v
new file mode 100644
index 0000000..d16ef66
--- /dev/null
+++ b/tests_ok/indent_unique_case-1.v
@@ -0,0 +1,366 @@
+module xxx_xxxxxx (input wire clk, input wire reset);
+
+ typedef enum reg [4:0] {IDLE, IIII, HHHHH,
+ AA_OP, AA_CMRD, AA_CMRD_WAIT, AA_RMW, AA_RMW_WAIT, AA_CMLLL, AA_CMLLL_WAIT, AA_NEXT,
+ BB_OP, BB_CMLLL, BB_CMLLL_WAIT, BB_NEXT,
+ CC_OP, CC_NEXT_OOOO,
+ DD_OP, DD_CMRD, DD_CMRD_WAIT, DD_ACCUM, DD_CMLLL, DD_CMLLL_WAIT,
+ EE_OP, EE_NEXT_OOOO,
+ FF_OP,
+ zxcvzxcv, cvbncvbn} xxxxxx_state_e;
+
+ xxxxxx_state_e current_state;
+
+ always_ff @ (posedge clk) begin
+ if (reset) begin
+ current_state <= IDLE;
+ end
+ else begin
+ unique case (current_state)
+
+ IDLE : begin
+ qwerty <= '0;
+
+ if (~qqq_empty)
+ current_state <= HHHHH;
+ end
+ AA_CMLLL : begin
+ lll_start <= 1'b1;
+
+ if (jjjj_left < 4)
+ lll_wcnt <= jjjj_left[2:0];
+ else
+ lll_wcnt <= FOUR[2:0];
+
+ current_state <= AA_CMLLL_WAIT;
+ end
+
+ HHHHH : begin
+ qqq_opiuy <= 1'b1;
+
+ if (qqq_opiuy) begin
+ qqq_opiuy <= '0;
+ current_state <= IIII;
+
+ end
+ end
+
+ AA_OP : begin
+ if (aa_pgm_err) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin
+ jjjj_left <= tgbyhn;
+
+ current_state <= AA_CMRD;
+ end
+ end
+
+ AA_CMRD : begin
+ uuuuu <= 1'b1;
+ current_state <= AA_CMRD_WAIT;
+ end
+ IIII : begin
+ qqq_opiuy <= '0;
+ if (err_iiii) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin
+ unique0 case (opm_cur)
+
+ `XXXCP : current_state <= AA_OP;
+ `XXXZR : current_state <= BB_OP;
+
+ default : current_state <= zxcvzxcv;
+ endcase // unique0 case
+
+ end // else: !if(err_iiii)
+ end // case: IIII
+
+ AA_CMRD_WAIT : begin
+ uuuuu <= '0;
+ if (kjkjkjkjk) begin
+ if (err_cmrd_par) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin
+ if (err_cmrd_csel) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin : assign_writecvbn
+ lllcvbn <= asdf ? ghjk : rdcvbn;
+ lll_par <= asdf ? cvbn : rd_par;
+
+ current_state <= AA_CMLLL;
+ end
+ end // else: !if(err_cmrd_par)
+ end // if (kjkjkjkjk)
+ end // case: AA_CMRD_WAIT
+
+ AA_CMLLL_WAIT : begin
+ lll_start <= '0;
+
+ if (lll_done) begin
+ if (alalala) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin
+ current_state <= AA_NEXT;
+ end
+ end
+ end // case: AA_CMLLL_WAIT
+
+
+
+ AA_NEXT : begin
+
+ if (qwerty) begin
+ qwerty <= '0;
+
+
+ unique case (opm_cur)
+
+ `XXXCP : current_state <= cvbncvbn;
+ `XXXSG : current_state <= CC_NEXT_OOOO;
+ default : current_state <= zxcvzxcv;
+ endcase // unique case
+
+ end // if (qwerty)
+ else begin
+ jjjj_left <= jjjj_left - 4;
+
+ current_state <= AA_CMRD;
+ end // else: !if(qwerty)
+ end // case: AA_NEXT
+
+ BB_OP : begin
+ if (bb_pgm_err) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin
+ lllcvbn <= '0;
+ lll_par <= '0;
+ jjjj_left <= tgbyhn;
+
+ current_state <= BB_CMLLL;
+ end
+ end // case: BB_OP
+
+
+
+ BB_CMLLL : begin
+ lll_start <= 1'b1;
+
+ if (jjjj_left <= 4) begin
+ lll_wcnt <= jjjj_left[2:0];
+ qwerty <= 1'b1;
+ end
+ else begin
+ lll_wcnt <= FOUR[2:0];
+ end
+
+ current_state <= BB_CMLLL_WAIT;
+ end // case: BB_CMLLL
+
+
+
+ BB_CMLLL_WAIT : begin
+ lll_start <= '0;
+
+ if (lll_done) begin
+ if (alalala) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin
+ current_state <= BB_NEXT;
+ end
+ end
+ end // case: BB_CMLLL_WAIT
+
+
+
+
+ BB_NEXT : begin
+ if (qwerty) begin
+ qwerty <= '0;
+ current_state <= cvbncvbn;
+ end
+ else begin
+ jjjj_left <= jjjj_left - 4;
+ current_state <= BB_CMLLL;
+ end
+ end
+
+
+
+
+
+
+ CC_OP : begin
+ jjjj_left_oooo <= tgbyhn;
+
+ if (tgbyhn <= oooo_cur) begin
+ last_oooo <= 1'b1;
+ jjjj_left <= tgbyhn;
+ end
+ else begin
+ jjjj_left <= oooo_cur;
+ end
+
+ current_state <= AA_CMRD;
+
+ end // case: CC_OP
+
+
+
+
+ CC_NEXT_OOOO : begin
+ if (last_oooo) begin
+ current_state <= cvbncvbn;
+ end
+ else begin
+
+ rd_rrrr <= rd_rrrr + ttttt_cur;
+ lll_rrrr <= lll_rrrr + oooo_cur;
+
+
+ if (jjjj_left_oooo <= oooo_cur) begin
+ last_oooo <= 1'b1;
+ jjjj_left <= jjjj_left_oooo;
+ end
+ else begin
+ jjjj_left <= oooo_cur;
+ end
+
+ current_state <= AA_CMRD;
+ end // else: !if(last_oooo)
+
+ end // case: CC_NEXT_OOOO
+
+
+
+
+
+ DD_OP : begin
+ accumulate_sum <= '0;
+ jjjj_left <= tgbyhn;
+
+ current_state <= DD_CMRD;
+ end
+
+
+ DD_CMRD : begin
+ uuuuu <= 1'b1;
+
+ if (jjjj_left <= 4) begin
+ qwerty <= 1'b1;
+ end
+
+ current_state <= DD_CMRD_WAIT;
+ end
+
+
+
+ DD_CMRD_WAIT : begin
+ uuuuu <= '0;
+
+ if (kjkjkjkjk) begin
+ if (zazaz) begin
+ current_state <= zxcvzxcv;
+ end
+ else begin
+
+ current_state <= DD_ACCUM;
+ end
+ end
+ end // case: DD_CMRD_WAIT
+
+
+ DD_ACCUM : begin
+ if (qwerty) begin
+ current_state <= DD_CMLLL;
+ end
+ else begin
+ current_state <= DD_CMRD;
+ end
+ end
+
+
+
+ DD_CMLLL : begin
+ lll_start <= 1'b1;
+
+ current_state <= DD_CMLLL_WAIT;
+ end
+
+
+
+ DD_CMLLL_WAIT : begin
+ lll_start <= '0;
+
+ end
+
+
+
+
+ EE_OP : begin
+ jjjj_left_oooo <= tgbyhn;
+
+ current_state <= AA_CMRD;
+ end
+
+
+
+
+ EE_NEXT_OOOO : begin
+ if (last_oooo) begin
+ current_state <= cvbncvbn;
+ end
+ else begin
+
+ end
+ end
+
+
+
+ FF_OP : begin
+ asdf <= 1'b1;
+
+ current_state <= CC_OP;
+ end
+
+ zxcvzxcv : begin
+ current_state <= cvbncvbn;
+ end
+
+ cvbncvbn : begin
+ if (dci_cur) begin
+ current_state <= IDLE;
+ cmd_proc_done <= 1'b1;
+ end
+ else if (crq_ready) begin
+ crq_start <= 1'b1;
+ crqcvbn <= complcvbn;
+ crq_proc_id <= proc_id_cur;
+
+ current_state <= IDLE;
+ cmd_proc_done <= 1'b1;
+ end
+ end // case: cvbncvbn
+
+ default : begin
+ current_state <= IDLE;
+ cmd_proc_done <= 1'b1;
+ end
+ endcase // unique case
+ end // else: !if(reset)
+ end // always _ff
+
+
+
+endmodule // xxx_xxxxxx
+
+
+
+
+
diff --git a/tests_ok/indent_unique_case-2.v b/tests_ok/indent_unique_case-2.v
new file mode 100644
index 0000000..9f758ee
--- /dev/null
+++ b/tests_ok/indent_unique_case-2.v
@@ -0,0 +1,52 @@
+module testmod ();
+ always_comb begin
+ unique case (eeee)
+ ZERO[1:0] : begin
+ a = 1;
+ end // case: ZERO[1:0]
+
+ ONE[1:0] : begin
+ a = 1;
+ end // case: ONE[1:0]
+
+ TWO[1:0] : begin
+ a = 1;
+ end // case: TWO[1:0]
+ THREE[1:0] : begin
+ a = 1;
+ end // case: THREE[1:0]
+ endcase // unique case (eeee)
+ end // always_comb
+
+ always_ff @ (posedge clk) begin
+ if (reset) begin
+ current_state <= `TQ STATE0;
+ end // if (reset)
+ else begin
+ priority case (current_state)
+ STATE0 : begin
+ current_state <= `TQ STATE3;
+ end // case: STATE0
+
+ STATE1 : begin
+ current_state <= `TQ STATE3;
+ end // case: STATE1
+
+ STATE2 : begin
+ current_state <= `TQ STATE3;
+ end // case: STATE2
+
+ STATE3 : begin
+ current_state <= `TQ STATE0;
+ end // case: STATE3
+
+ default : current_state <= `TQ STATE0;
+ endcase // priority case (current_state)
+ end // else: !if(reset)
+ end // always_ff @
+
+endmodule // testmod
+
+
+
+
diff --git a/tests_ok/indent_unique_case.v b/tests_ok/indent_unique_case.v
new file mode 100644
index 0000000..373f239
--- /dev/null
+++ b/tests_ok/indent_unique_case.v
@@ -0,0 +1,36 @@
+module foo;
+ // syntaxify the unique keyword correctly please...
+ always_comb (*) begin
+ case (f)
+ 1 : 2;
+ endcase // case (f)
+
+ unique case(vlcnum)
+ 0 : unique case(in.value1)
+ 0 : out = 1; 1 : out = 3; 2 : out = 3; 3 : out = 4;
+ 4 : out = 4; 5 : out = 5; 6 : out = 5; 7 : out = 6;
+ 8 : out = 6; 9 : out = 7; 10: out = 7; 11: out = 8;
+ 12 : out = 8; 13: out = 9; 14: out = 9; 15: out = 9;
+ endcase
+ 1 :
+ unique
+ case(in.value1)
+ 0 : out = 3;
+ 1 : out = 3;
+ 2 : out = 3;
+ 3 : out = 3;
+ 4 : out = 3;
+ 5 : out = 4;
+ 6 : out = 4;
+ 7 : out = 4;
+ 8 : out = 4;
+ 9 : out = 5;
+ 10 : out = 5;
+ 11 : out = 6;
+ 12 : out = 6;
+ 13 : out = 6;
+ 14 : out = 6;
+ endcase // case (in.value1)
+ endcase // case (in.value1)
+ end
+endmodule
diff --git a/tests_ok/indent_uvm.v b/tests_ok/indent_uvm.v
new file mode 100644
index 0000000..3a3fd00
--- /dev/null
+++ b/tests_ok/indent_uvm.v
@@ -0,0 +1,70 @@
+module uvm;
+class simple_item extends uvm_sequence_item;
+ rand int unsigned addr;
+ rand int unsigned data;
+ rand int unsigned delay;
+ constraint c1 { addr < 16'h2000; }
+ constraint c2 { data < 16'h1000; }
+ // UVM automation macros for general objects
+ `uvm_object_utils_begin(simple_item)
+ a = b;
+ c = d;
+ `uvm_field_int(addr, UVM_ALL_ON)
+ `uvm_field_int(data, UVM_ALL_ON)
+ `uvm_field_int(delay, UVM_ALL_ON)
+ `uvm_object_utils_end
+ // Constructor
+ function new (string name = "simple_item");
+ super.new(name);
+ endfunction : new
+endclass : simple_item
+class mydata extends uvm_object;
+
+ string str;
+ mydata subdata;
+ int field;
+ myenum e1;
+ int queue[$];
+ `uvm_object_utils(mydata)
+ `uvm_object_utils_begin(mydata) //requires ctor with default args
+ `uvm_field_string(str, UVM_DEFAULT)
+ `uvm_field_object(subdata, UVM_DEFAULT)
+ `uvm_field_int(field, UVM_DEC) //use decimal radix
+ `uvm_field_enum(myenum, e1, UVM_DEFAULT)
+ `uvm_field_queue_int(queue, UVM_DEFAULT)
+ `uvm_object_utils_end
+ `uvm_object_param_utils_begin(mydata) //requires ctor with default args
+ `uvm_field_string(str, UVM_DEFAULT)
+ `uvm_field_object(subdata, UVM_DEFAULT)
+ `uvm_field_int(field, UVM_DEC) //use decimal radix
+ `uvm_field_enum(myenum, e1, UVM_DEFAULT)
+ `uvm_field_queue_int(queue, UVM_DEFAULT)
+ `uvm_object_utils_end
+endclass
+class my_trans extends uvm_sequence_item;
+
+ rand bit [127:0] data [];
+
+ //---> Configuration
+ `uvm_object_utils_begin(my_trans)
+ `uvm_field_array_int ( data, UVM_ALL_ON)
+ `uvm_object_utils_end
+
+ function new (string name = "my_trans", uvm_sequencer_base sequencer = null, uvm_sequence parent_seq = null);
+ super.new(name, sequencer, parent_seq);
+ endfunction : new
+endclass : my_trans
+endmodule // uvm
+
+module tt;
+
+ initial begin
+ while (1) begin
+ `uvm_do_with(aa, {bb == 0;})
+ `uvm_do(cc)
+ `uvm_do(cc)
+ end // while (1)
+ end // initial begin
+
+endmodule // tt
+
diff --git a/tests_ok/indent_virtual_class.sv b/tests_ok/indent_virtual_class.sv
new file mode 100644
index 0000000..7e4c739
--- /dev/null
+++ b/tests_ok/indent_virtual_class.sv
@@ -0,0 +1,9 @@
+// issue 928 - 'pure virtual' items in classes break indentation
+package p:
+ virtual class c extends parent;
+ pure virtual protected task t(type_t a, type_t b);
+ function f(string s="");
+ blah;
+ endfunction:f
+ endclass
+endpackage
diff --git a/tests_ok/indent_warren.v b/tests_ok/indent_warren.v
new file mode 100644
index 0000000..ef9b32f
--- /dev/null
+++ b/tests_ok/indent_warren.v
@@ -0,0 +1,6 @@
+`include "x.h"
+//
+module x;
+ ////
+ reg y;
+endmodule // x
diff --git a/tests_ok/inject_first.v b/tests_ok/inject_first.v
new file mode 100644
index 0000000..a05b15c
--- /dev/null
+++ b/tests_ok/inject_first.v
@@ -0,0 +1,29 @@
+module ex_inject (i, o,/*AUTOARG*/
+ // Inputs
+ j
+ );
+ input i;
+ input j;
+ output o;
+
+ // Ok:
+ always @ (/*AS*/i or j)
+ o = i | j;
+ // No change:
+ always @ (j) o = i | j;
+ always @ (j or i or p) o = i | j;
+ // Instant
+
+ autoinst_lopaz_srpad pad
+ (.foo(bar),
+ .clk(newclk),
+ /*AUTOINST*/
+ // Outputs
+ .pin_in (pin_in[2*w-1:0]),
+ // Inouts
+ .pin (pin[w-1:0]),
+ // Inputs
+ .pin_out (pin_out[w-1:0]),
+ .pin_outen (pin_outen));
+
+endmodule
diff --git a/tests_ok/inject_inst_empty_ports.v b/tests_ok/inject_inst_empty_ports.v
new file mode 100644
index 0000000..da94cce
--- /dev/null
+++ b/tests_ok/inject_inst_empty_ports.v
@@ -0,0 +1,27 @@
+module inject_inst_empty_ports;
+ logic [7:0] q;
+ logic [7:0] d;
+ logic clk, rst_n;
+
+ register r1 (.qb(), // unconnect output
+ /*AUTOINST*/
+ // Outputs
+ .q (q[7:0]),
+ // Inputs
+ .d (d[7:0]),
+ .clk (clk),
+ .rst_n (rst_n));
+endmodule
+
+module register (
+ output logic [7:0] q, qb,
+ input logic [7:0] d,
+ input logic clk, rst_n
+ /*AUTOARG*/);
+
+ always_ff @(posedge clk or negedge rst_n)
+ if (!rst_n) q <= '0;
+ else q <= d;
+
+ assign qb = ~q;
+endmodule
diff --git a/tests_ok/inject_inst_endparen.v b/tests_ok/inject_inst_endparen.v
new file mode 100644
index 0000000..a9de17d
--- /dev/null
+++ b/tests_ok/inject_inst_endparen.v
@@ -0,0 +1,35 @@
+module inject_inst_endparen;
+ logic [7:0] q;
+ logic [7:0] d;
+ logic clk, nreset;
+
+ register r1 (.rst_n(nreset),
+ /*AUTOINST*/
+ // Outputs
+ .q (q[7:0]),
+ // Inputs
+ .d (d[7:0]),
+ .clk (clk));
+
+`if NEVER
+ register r1 (.q(qKEEP),
+ .d(dKEEP),
+ .clk(clkKEEP),
+ // This is the
+ // asynchronous reset
+ .rst_n(nreset)
+ /*AUTOINST*/);
+`endif
+
+endmodule
+
+module register (
+ output logic [7:0] q,
+ input logic [7:0] d,
+ input logic clk, rst_n
+ /*AUTOARG*/);
+
+ always_ff @(posedge clk or negedge rst_n)
+ if (!rst_n) q <= '0;
+ else q <= d;
+endmodule
diff --git a/tests_ok/inject_inst_net_case.v b/tests_ok/inject_inst_net_case.v
new file mode 100644
index 0000000..3922bce
--- /dev/null
+++ b/tests_ok/inject_inst_net_case.v
@@ -0,0 +1,42 @@
+module inject_inst_net_case (
+ output logic [7:0] q2,
+ input logic [7:0] d,
+ input logic clk, rst_n
+ /*AUTOARG*/);
+ logic [7:0] Q1;
+
+ register2 r2 (.q1(Q1), .ck(clk),
+ /*AUTOINST*/
+ // Outputs
+ .q2 (q2[7:0]),
+ // Inputs
+ .rst_n (rst_n));
+
+ register1 r1 (.q1(Q1), .ck(clk),
+ /*AUTOINST*/
+ // Inputs
+ .d (d[7:0]),
+ .rst_n (rst_n));
+endmodule
+
+module register2 (
+ output logic [7:0] q2,
+ input logic [7:0] q1,
+ input logic ck, rst_n
+ /*AUTOARG*/);
+
+ always_ff @(posedge ck or negedge rst_n)
+ if (!rst_n) q2 <= '0;
+ else q2 <= q1;
+endmodule
+
+module register1 (
+ output logic [7:0] q1,
+ input logic [7:0] d,
+ input logic ck, rst_n
+ /*AUTOARG*/);
+
+ always_ff @(posedge ck or negedge rst_n)
+ if (!rst_n) q1 <= '0;
+ else q1 <= d;
+endmodule
diff --git a/tests_ok/inject_inst_param.v b/tests_ok/inject_inst_param.v
new file mode 100644
index 0000000..3adfd0c
--- /dev/null
+++ b/tests_ok/inject_inst_param.v
@@ -0,0 +1,26 @@
+module inject_inst_param;
+ parameter WIDTH = 8;
+ logic [WIDTH-1:0] q;
+ logic [WIDTH-1:0] d;
+ logic clk, rst_n;
+
+ register #(.WIDTH(WIDTH)) r1 (
+ /*AUTOINST*/
+ // Outputs
+ .q (q[WIDTH-1:0]),
+ // Inputs
+ .d (d[WIDTH-1:0]),
+ .clk (clk),
+ .rst_n (rst_n));
+endmodule
+
+module register #(parameter WIDTH=4) (
+ output logic [WIDTH-1:0] q,
+ input logic [WIDTH-1:0] d,
+ input logic clk, rst_n
+ /*AUTOARG*/);
+
+ always_ff @(posedge clk or negedge rst_n)
+ if (!rst_n) q <= '0;
+ else q <= d;
+endmodule
diff --git a/tests_ok/inject_path.v b/tests_ok/inject_path.v
new file mode 100644
index 0000000..aa8bc0e
--- /dev/null
+++ b/tests_ok/inject_path.v
@@ -0,0 +1,19 @@
+module inject_path;
+ logic [7:0] q;
+ logic [7:0] d;
+ logic clk, rst_n;
+
+ register r1 (
+ /*AUTOINST*/
+ // Outputs
+ .q (q[7:0]),
+ // Inputs
+ .d (d[7:0]),
+ .clk (clk),
+ .rst_n (rst_n));
+endmodule
+
+// Local Variables:
+// mode: Verilog
+// verilog-library-flags:("-f inject_path.f")
+// End:
diff --git a/tests_ok/inject_path_cmt.v b/tests_ok/inject_path_cmt.v
new file mode 100644
index 0000000..092fcfe
--- /dev/null
+++ b/tests_ok/inject_path_cmt.v
@@ -0,0 +1,19 @@
+module comments_test;
+ logic [7:0] q1;
+ logic [7:0] d;
+ logic clk, rst_n;
+
+ register r1 (.q(q1),
+ .clk100(clk),
+ // Asynchronous reset
+ /*AUTOINST*/
+ // Inputs
+ .d (d[7:0]),
+ .clk (clk),
+ .rst_n (rst_n));
+endmodule
+
+// Local Variables:
+// mode: Verilog
+// verilog-library-flags:("-f inject_path.f")
+// End:
diff --git a/tests_ok/inject_path_sub.v b/tests_ok/inject_path_sub.v
new file mode 100644
index 0000000..028cb91
--- /dev/null
+++ b/tests_ok/inject_path_sub.v
@@ -0,0 +1,28 @@
+// Note module names don't match, this is intentional to check the .f file
+
+module reg_core (
+ output logic [7:0] q,
+ input logic [7:0] d,
+ input logic clk, rst_n
+ /*AUTOARG*/);
+
+ always_ff @(posedge clk or negedge rst_n)
+ if (!rst_n) q <= '0;
+ else q <= d;
+endmodule
+
+module register (
+ output logic [7:0] q,
+ input logic [7:0] d,
+ input logic clk, rst_n
+ /*AUTOARG*/);
+
+ reg_core c1 (
+ /*AUTOINST*/
+ // Outputs
+ .q (q[7:0]),
+ // Inputs
+ .d (d[7:0]),
+ .clk (clk),
+ .rst_n (rst_n));
+endmodule
diff --git a/tests_ok/inst.v b/tests_ok/inst.v
new file mode 100644
index 0000000..6a46e16
--- /dev/null
+++ b/tests_ok/inst.v
@@ -0,0 +1,18 @@
+module inst (/*AUTOARG*/
+ // Outputs
+ lower_out,
+ // Inputs
+ lower_inb, lower_ina
+ );
+
+ parameter param1;
+ parameter param2;
+
+ input lower_inb;
+ input lower_ina;
+ output lower_out;
+
+ wire lower_out = lower_ina | lower_inb;
+
+endmodule
+
diff --git a/tests_ok/label_always.v b/tests_ok/label_always.v
new file mode 100644
index 0000000..fe72f0a
--- /dev/null
+++ b/tests_ok/label_always.v
@@ -0,0 +1,49 @@
+// bug 895 - labeling of always constructs
+module example;
+
+ always
+ begin
+ end // always
+
+ always @(posedge clk)
+ begin
+ end // always @ (posedge clk)
+
+ always @*
+ begin
+ end // always @ *
+
+ always @(*)
+ begin
+ end // always @ (*)
+
+ always_comb
+ begin
+ end // always_comb
+
+ always_latch
+ begin
+ end // always_latch
+
+ always @( *)
+ begin
+ end // always @ ( *)
+
+ always @(* )
+ begin
+ end // always @ (* )
+
+ always_ff @(posedge clk)
+ begin
+ end // always_ff @ (posedge clk)
+
+ always @(*)
+ begin
+ end // always @ (*)
+
+endmodule // example
+
+// Local Variables:
+// verilog-minimum-comment-distance: 1
+// verilog-auto-endcomments: t
+// End:
diff --git a/tests_ok/label_class.sv b/tests_ok/label_class.sv
new file mode 100644
index 0000000..d77cf23
--- /dev/null
+++ b/tests_ok/label_class.sv
@@ -0,0 +1,3 @@
+// Bug 888 -- verilog-label-be should remove existing comment labels before adding new ones
+class c;
+endclass // c
diff --git a/tests_ok/label_do.v b/tests_ok/label_do.v
new file mode 100644
index 0000000..b7b23ac
--- /dev/null
+++ b/tests_ok/label_do.v
@@ -0,0 +1,12 @@
+// bug 842
+module x;
+
+ do begin
+ end while(); // do begin
+
+endmodule // x
+
+// Local Variables:
+// verilog-minimum-comment-distance: 1
+// verilog-auto-endcomments: t
+// End:
diff --git a/tests_ok/label_function.v b/tests_ok/label_function.v
new file mode 100644
index 0000000..cbb351b
--- /dev/null
+++ b/tests_ok/label_function.v
@@ -0,0 +1,66 @@
+module test();
+
+ // function with no lifetime, return-type, or port-list
+ function f0;
+ blah0;
+ endfunction // f0
+
+ // empty port-list
+ function f1();
+ blah1;
+ endfunction // f1
+
+ // non-empty portlist
+ function f2(stuff2);
+ blah2;
+ endfunction // f2
+
+ // test that ": function_identifier" remains unscathed
+ function f3;
+ endfunction : f3
+
+ // return type
+ function void f4;
+ blah4;
+ endfunction // f4
+
+ // return type with empty port-list.
+ function void f5();
+ int i;
+ begin
+ blah4;
+ end
+ endfunction // f5
+
+ // return type, non-empty portlist
+ // also check that a stale auto-comment gets removed
+ function void f6(stuff,
+ that,
+ spans,
+ lines);
+ blah5;
+ endfunction // f6
+
+ // test lifetime keywords 'automatic' and 'static'
+ function automatic f7();
+ endfunction // f7
+
+ // test a crazy-long function declaration
+ function static union packed signed {bit[1:0] a, bit[2:0] b} [5:0] f8(input ports, input ports, output ports);
+ endfunction // f8
+
+ // port-list that doesn't start on the same line as the function declaration
+ function automatic void f9
+ (int a,
+ int b);
+ endfunction // f9
+
+ // mismatched keyword
+ function f10;
+ endtask // unmatched end(function|task|module|primitive|interface|package|class|clocking)
+
+// make sure previous screw-up doesn't affect future functions
+function f11;
+endfunction // f11
+
+endmodule // test
diff --git a/tests_ok/label_macro.v b/tests_ok/label_macro.v
new file mode 100644
index 0000000..46b888f
--- /dev/null
+++ b/tests_ok/label_macro.v
@@ -0,0 +1,23 @@
+// Bug 859 -- 'end' should label after a user/library-defined macro
+// that isn't terminated with a semi-colon
+class c;
+
+ `uvm_info(get_type_name(), "Digital power up.", UVM_MEDIUM)
+
+ fork
+ begin
+ end // fork begin
+ join
+
+ `made_up_macro (a, \
+ b, \
+ c)
+ begin: named_block
+ end // block: named_block
+
+endclass // c
+
+// Local Variables:
+// verilog-minimum-comment-distance: 1
+// verilog-auto-endcomments: t
+// End:
diff --git a/tests_ok/label_no_indent.v b/tests_ok/label_no_indent.v
new file mode 100644
index 0000000..6ab03d2
--- /dev/null
+++ b/tests_ok/label_no_indent.v
@@ -0,0 +1,15 @@
+// bug 841
+module x;
+
+always @*
+begin
+end // always @ *
+
+endmodule // x
+
+// Local Variables:
+// verilog-indent-level-module: 0
+// verilog-indent-begin-after-if: nil
+// verilog-minimum-comment-distance: 1
+// verilog-auto-endcomments: t
+// End:
diff --git a/tests_ok/label_task.v b/tests_ok/label_task.v
new file mode 100644
index 0000000..f87a64f
--- /dev/null
+++ b/tests_ok/label_task.v
@@ -0,0 +1,51 @@
+module test();
+
+ // task with no lifetime, return-type, or port-list
+ task t0;
+ blah0;
+ endtask // t0
+
+ // empty port-list
+ task t1();
+ blah1;
+ endtask // t1
+
+ // non-empty portlist
+ task t2(stuff2);
+ blah2;
+ endtask // t2
+
+ // test that ": task_identifier" remains unscathed
+ task t3;
+ endtask : t3
+
+ // check that stale auto-label is overwritten
+ task t4(input port1, output port2, inout port3);
+ begin
+ blah blah blah;
+ end
+ endtask // t4
+
+ // test lifetime keywords 'automatic' and 'static'
+ task static t7();
+ endtask // t7
+
+ // test a more complete example
+ task automatic t8(input ports, input ports, output ports);
+ endtask // t8
+
+ // port-list that doesn't start on the same line as the task declaration
+ task automatic t9
+ (int a,
+ int b);
+ endtask // t9
+
+ // mismatched keyword
+ task t10;
+ endfunction // unmatched end(function|task|module|primitive|interface|package|class|clocking)
+
+// make sure even the simplest test works after all the insanity
+task t11;
+endtask // t11
+
+endmodule // test
diff --git a/tests_ok/lavigne_instpath.v b/tests_ok/lavigne_instpath.v
new file mode 100644
index 0000000..f7ab4a4
--- /dev/null
+++ b/tests_ok/lavigne_instpath.v
@@ -0,0 +1,28 @@
+module lavigne_instpath ();
+
+ /* lavigne_t1 AUTO_TEMPLATE (
+ .a(a1),
+ );
+ */
+ lavigne_t1 m1 (/*AUTOINST*/
+ // Inputs
+ .a (a1)); // Templated
+
+ /* lavigne_t2 AUTO_TEMPLATE (
+ .b(b2),
+ );
+ */
+
+ lavigne_t2 m2 (/*AUTOINST*/
+ // Inputs
+ .b (b2)); // Templated
+
+endmodule
+
+// verilkkkkkkkog-library-directories:("*/")
+
+//(load-file "/usr/local/common/site-lisp/local/verilog-mode.el")
+
+// Local Variables:
+// verilog-library-flags:("-y lavigne_instpath/")
+// End:
diff --git a/tests_ok/lavigne_instpath/lavigne_t1.v b/tests_ok/lavigne_instpath/lavigne_t1.v
new file mode 100644
index 0000000..6292b54
--- /dev/null
+++ b/tests_ok/lavigne_instpath/lavigne_t1.v
@@ -0,0 +1,3 @@
+module lavigne_t1 (a);
+input a;
+endmodule
diff --git a/tests_ok/lavigne_instpath/lavigne_t2.v b/tests_ok/lavigne_instpath/lavigne_t2.v
new file mode 100644
index 0000000..8867ea7
--- /dev/null
+++ b/tests_ok/lavigne_instpath/lavigne_t2.v
@@ -0,0 +1,3 @@
+module lavigne_t2 (b);
+input b;
+endmodule
diff --git a/tests_ok/lineup.v b/tests_ok/lineup.v
new file mode 100644
index 0000000..4ccf9b1
--- /dev/null
+++ b/tests_ok/lineup.v
@@ -0,0 +1,2 @@
+module ocnSwitchClockGen(output reg ocnSwitchClock);
+ parameter ocnSwitchClockPeriod = 2000;
diff --git a/tests_ok/local_vmode.x b/tests_ok/local_vmode.x
new file mode 100644
index 0000000..fcc536a
--- /dev/null
+++ b/tests_ok/local_vmode.x
@@ -0,0 +1,12 @@
+module local_vmode ();
+
+ local_vmode_sub sub (/*AUTOINST*/
+ // Inputs
+ .in (in));
+
+endmodule
+
+// Local Variables:
+// mode: Verilog
+// verilog-library-flags:("+libext+.x")
+// End:
diff --git a/tests_ok/local_vmode_sub.x b/tests_ok/local_vmode_sub.x
new file mode 100644
index 0000000..ab2d4b4
--- /dev/null
+++ b/tests_ok/local_vmode_sub.x
@@ -0,0 +1,6 @@
+module local_vmode_sub (input in);
+endmodule
+
+// Local Variables:
+// mode: Verilog
+// End:
diff --git a/tests_ok/mac_autosense_dot.v b/tests_ok/mac_autosense_dot.v
new file mode 100644
index 0000000..5d71cc3
--- /dev/null
+++ b/tests_ok/mac_autosense_dot.v
@@ -0,0 +1,9 @@
+//From: Michael McNamara <mac@verilog.com>
+//Date: Tue, 27 Jun 2000 04:38:32 -0700 (PDT)
+module x;
+
+ always @ (/*AS*/top.agc_tool.adc_dta_i or top.agc_tool.adc_preagc_dta_i) begin
+ agctoolerr = top.agc_tool.adc_dta_i / top.agc_tool.adc_preagc_dta_i;
+ end
+
+endmodule
diff --git a/tests_ok/mac_test2.sv b/tests_ok/mac_test2.sv
new file mode 100644
index 0000000..b1a6528
--- /dev/null
+++ b/tests_ok/mac_test2.sv
@@ -0,0 +1,14 @@
+module foobar;
+
+ sequence s_1;
+ {txd, txdk} && (ppd == 3'b000) && !txe;
+ endsequence // s_1
+
+ sequence s_phy_transmitting;
+ {rxd, rxdk} &&
+ ((ppd == 3'b000) || (ppd == 3'b001))
+ && rxv;
+ endsequence // s_phy_transmitting
+
+
+endmodule
diff --git a/tests_ok/mac_test2.v b/tests_ok/mac_test2.v
new file mode 100644
index 0000000..b1a6528
--- /dev/null
+++ b/tests_ok/mac_test2.v
@@ -0,0 +1,14 @@
+module foobar;
+
+ sequence s_1;
+ {txd, txdk} && (ppd == 3'b000) && !txe;
+ endsequence // s_1
+
+ sequence s_phy_transmitting;
+ {rxd, rxdk} &&
+ ((ppd == 3'b000) || (ppd == 3'b001))
+ && rxv;
+ endsequence // s_phy_transmitting
+
+
+endmodule
diff --git a/tests_ok/more_params.v b/tests_ok/more_params.v
new file mode 100644
index 0000000..77ed77d
--- /dev/null
+++ b/tests_ok/more_params.v
@@ -0,0 +1,54 @@
+module InstName (/*AUTOARG*/
+ // Outputs
+ out,
+ // Inputs
+ in
+ );
+ input [7:0] in;
+ output [7:0] out;
+ wire [7:0] out = ~in;
+endmodule // bottm
+
+module top (/*AUTOARG*/
+ // Outputs
+ outgo,
+ // Inputs
+ incom
+ );
+ input [31:0] incom;
+ output [31:0] outgo;
+
+ /* AUTO_LISP(defun getparam2 (strg)
+ (string-match "[^0-9]*[0-9]+[^0-9]*\\([0-9]+\\)" strg)
+ (match-string 1 strg))*/
+ /* InstName AUTO_TEMPLATE (
+ .out (@),
+ .in (@"(getparam2 vl-cell-name)"),
+ );
+ */
+
+ InstName BT0_2 (/*AUTOINST*/
+ // Outputs
+ .out (0), // Templated
+ // Inputs
+ .in (2)); // Templated
+ InstName BT1_3 (/*AUTOINST*/
+ // Outputs
+ .out (1), // Templated
+ // Inputs
+ .in (3)); // Templated
+ InstName BT2_5 (/*AUTOINST*/
+ // Outputs
+ .out (2), // Templated
+ // Inputs
+ .in (5)); // Templated
+ InstName BT3_9 (/*AUTOINST*/
+ // Outputs
+ .out (3), // Templated
+ // Inputs
+ .in (9)); // Templated
+
+endmodule
+
+
+
diff --git a/tests_ok/morrison.v b/tests_ok/morrison.v
new file mode 100644
index 0000000..a619890
--- /dev/null
+++ b/tests_ok/morrison.v
@@ -0,0 +1,16 @@
+`define XYZ 4'ha
+
+module test ();
+
+ always @(/*AUTOSENSE*/r or x)
+ begin
+ casex(x)
+ 5: d = {r, `XYZ };
+ endcase
+ end
+
+endmodule // test
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests_ok/params_multiline_msg618.v b/tests_ok/params_multiline_msg618.v
new file mode 100644
index 0000000..07ec687
--- /dev/null
+++ b/tests_ok/params_multiline_msg618.v
@@ -0,0 +1,15 @@
+module testMultiLineParams (/*AUTOARG*/) ;
+`include "params_multiline_msg618_inc.vh"
+ reg comboIn, comboOut;
+
+ // expect AUTOSENSE to be comboIn only, no params
+ always @ ( /*AUTOSENSE*/comboIn) begin
+ comboOout = param1 & param2 & param3 & comboIn;
+ end
+
+endmodule // foo
+
+// Local Variables:
+// verilog-library-directories:(".")
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests_ok/params_multiline_msg618_inc.vh b/tests_ok/params_multiline_msg618_inc.vh
new file mode 100644
index 0000000..ee0620b
--- /dev/null
+++ b/tests_ok/params_multiline_msg618_inc.vh
@@ -0,0 +1,6 @@
+parameter
+ // full line comment
+ param1 = 1'b1, // trailing comment
+ param2 = 1'b0, /* trailing comment */
+ // full line comment
+ param3 = 1'b1;
diff --git a/tests_ok/property_test.v b/tests_ok/property_test.v
new file mode 100644
index 0000000..97d70a5
--- /dev/null
+++ b/tests_ok/property_test.v
@@ -0,0 +1,62 @@
+
+//////////////////////////////////////////////////////////////////////////////
+//
+// Main
+//
+//////////////////////////////////////////////////////////////////////////////
+
+
+module test();
+
+ integer count;
+ bit test_clk;
+
+
+ // Create a test clock
+ always #01.8 test_clk = ~test_clk;
+
+ //**********************************************************************
+ // Testing.
+ // Shift a moving set of ones up the input vector. At each shift
+ // the outputs should change, which is checked by the assertions
+ // below. This test doesnt care which output changes, as that was
+ // checked to be accurate by formal means.
+ //**********************************************************************
+
+ initial begin
+ count=0;
+ end
+
+ always @(posedge test_clk) begin
+ count++;
+ end
+
+ //**********************************************************************
+ // SV assertions
+ //**********************************************************************
+ property p_lane_output_change_on_input_change;
+ @(negedge test_clk)
+ disable iff (ana_byp == 0)
+ !$stable(lane_inputs) |-> !$stable(lane_outputs);
+ endproperty
+
+ a_lane_output_change_on_input_change: assert property (p_lane_output_change_on_input_change)
+ else begin
+ $error("ERROR! Analog Bypass: Input change not observed on the outputs: %h (lane)",
+ lane_inputs);
+ end // UNMATCHED !!
+endproperty //FIXME
+
+ property p_sup_output_change_on_input_change;
+ @(negedge test_clk)
+ disable iff (ana_byp == 0)
+ !$stable(sup_inputs) |-> !$stable(sup_outputs);
+ endproperty
+
+ a_sup_output_change_on_input_change: assert property (p_sup_output_change_on_input_change)
+ else begin
+ $error("ERROR! Analog Bypass: Input change not observed on the outputs: %h (sup)",
+ sup_inputs);
+ end
+endproperty
+endmodule // test
diff --git a/tests_ok/reversed_bits.v b/tests_ok/reversed_bits.v
new file mode 100644
index 0000000..250e910
--- /dev/null
+++ b/tests_ok/reversed_bits.v
@@ -0,0 +1,39 @@
+module lbnsub
+ (/*AUTOARG*/
+ // Outputs
+ outgo,
+ // Inputs
+ income
+ );
+
+ input [7:4] income;
+ output [7:4] outgo;
+
+ wire [7:4] outgo = income;
+
+endmodule
+
+module lbm
+ (/*AUTOARG*/
+ // Outputs
+ outgo,
+ // Inputs
+ income
+ );
+
+ input [7:4] income;
+ output [7:4] outgo;
+
+ /*
+ lbnsub AUTO_TEMPLATE (
+ // Inputs
+ .income (income[4:7]));
+ */
+
+ lbnsub lbnsub (/*AUTOINST*/
+ // Outputs
+ .outgo (outgo[7:4]),
+ // Inputs
+ .income (income[4:7])); // Templated
+endmodule
+
diff --git a/tests_ok/set_membership.sv b/tests_ok/set_membership.sv
new file mode 100644
index 0000000..3cbb17c
--- /dev/null
+++ b/tests_ok/set_membership.sv
@@ -0,0 +1,40 @@
+import avm_pkg::*;
+import tinyalu_pkg::*;
+
+module top;
+
+ alu_operation req;
+ string msg;
+ integer i;
+
+ initial begin
+ $display ("---- A or B inside {0,8'hFF} ----");
+ for (i = 1; i<=5; i++) begin
+ req = new();
+ assert( a() with {A} );
+ req.randomize()
+ with
+ {
+ A inside {0,8'hFF};
+ B inside {0,8'hFF};
+ };
+ $sformat (msg,"ALU Request: %s", req.convert2string());
+ avm_report_message("TOP",msg);
+ $display;
+ $display ("---- op inside [add_op : mul_op] ----");
+
+ for (i = 1; i<=10; i++) begin
+ req = new();
+ assert(
+ req.randomize() with
+ {
+ op inside {[add_op : mul_op]};
+ }
+ );
+ $sformat (msg,"ALU Request: %s", req.convert2string());
+ avm_report_message("TOP",msg);
+ end // for (i = 1; i<=10; i++)
+ end // initial begin
+ endmodule // req_reader
+
+
diff --git a/tests_ok/singh.v b/tests_ok/singh.v
new file mode 100644
index 0000000..d304b57
--- /dev/null
+++ b/tests_ok/singh.v
@@ -0,0 +1,52 @@
+// HERE IS THE TEST CASE
+module bt (/*AUTOARG*/
+ // Outputs
+ out,
+ // Inputs
+ in
+ );
+ input [7:0] in;
+ output [7:0] out;
+
+ wire [7:0] out = ~in;
+endmodule // bottm
+
+module top (/*AUTOARG*/
+ // Outputs
+ outgo,
+ // Inputs
+ incom
+ );
+ input [31:0] incom;
+ output [31:0] outgo;
+
+ /* bt AUTO_TEMPLATE (
+ .in (incom[@"(+ (* 8 @) 7)":@"(* 8 @)"]),
+ .out (outgo[@"(concat (int-to-string (+ (* 8 @) 7)) \":\" (int-to-string ( * 8 @)))"]));
+ */
+
+ bt BT0 (/*AUTOINST*/
+ // Outputs
+ .out (outgo[7:0]), // Templated
+ // Inputs
+ .in (incom[7:0])); // Templated
+ bt BT1 (/*AUTOINST*/
+ // Outputs
+ .out (outgo[15:8]), // Templated
+ // Inputs
+ .in (incom[15:8])); // Templated
+ bt BT2 (/*AUTOINST*/
+ // Outputs
+ .out (outgo[23:16]), // Templated
+ // Inputs
+ .in (incom[23:16])); // Templated
+ bt BT3 (/*AUTOINST*/
+ // Outputs
+ .out (outgo[31:24]), // Templated
+ // Inputs
+ .in (incom[31:24])); // Templated
+
+endmodule // top
+
+
+
diff --git a/tests_ok/sol_asense.v b/tests_ok/sol_asense.v
new file mode 100644
index 0000000..039d4bf
--- /dev/null
+++ b/tests_ok/sol_asense.v
@@ -0,0 +1,92 @@
+module x (/*AUTOARG*/
+ // Inputs
+ MIERHW, MBOOTH_P, CEIopMADH_E_D2_R, CEIopMAZH_E_D2_R, DDATAH, DIV2HI, HI_R, MCLA, MCLASH,
+ MULTSHCYC, MULTUSCYC, HI_P
+ );
+
+ input [18:0] MIERHW;
+ integer i;
+ integer MTEMP1;
+ integer MTEMP2;
+ input MBOOTH_P;
+ input CEIopMADH_E_D2_R;
+ input CEIopMAZH_E_D2_R;
+ input DDATAH;
+ input DIV2HI;
+ input HI_R;
+ input MCLA;
+ input MCLASH;
+ input MULTSHCYC;
+ input MULTUSCYC;
+ input HI_P;
+
+ /*AUTOREG*/
+
+ /*AUTOINPUT*/
+
+ /*AUTOOUTPUT*/
+
+ always @(/*AUTOSENSE*/MIERHW) begin
+
+ for (i=0; i<=5; i=i+1) begin
+
+ MTEMP1[3:0] = {MIERHW[i*3+3],
+ MIERHW[i*3+2],
+ MIERHW[i*3+1],
+ MIERHW[i*3+0]};
+
+ casex (MTEMP1)
+
+ 4'b0000: MTEMP2 = 4'b0101; // +0
+ 4'b0001: MTEMP2 = 4'b0001; // +1
+ 4'b0010: MTEMP2 = 4'b0001; // +1
+ 4'b0011: MTEMP2 = 4'b0010; // +2
+ 4'b0100: MTEMP2 = 4'b0010; // +2
+ 4'b0101: MTEMP2 = 4'b0100; // +3
+ 4'b0110: MTEMP2 = 4'b0100; // +3
+ 4'b0111: MTEMP2 = 4'b1000; // +4
+ 4'b1000: MTEMP2 = 4'b0111; // -4
+ 4'b1001: MTEMP2 = 4'b1011; // -3
+ 4'b1010: MTEMP2 = 4'b1011; // -3
+ 4'b1011: MTEMP2 = 4'b1101; // -2
+ 4'b1100: MTEMP2 = 4'b1101; // -2
+ 4'b1101: MTEMP2 = 4'b1110; // -1
+ 4'b1110: MTEMP2 = 4'b1110; // -1
+ 4'b1111: MTEMP2 = 4'b1010; // -0
+
+ endcase
+
+ end
+
+ {MBOOTH_P[i*4+3],
+ MBOOTH_P[i*4+2],
+ MBOOTH_P[i*4+1],
+ MBOOTH_P[i*4+0]} = MTEMP2[3:0];
+
+ end
+
+ // always @(/*AUTOnotSENSE*/
+ // __CEIopMADH_E_D2_R or __CEIopMAZH_E_D2_R or __DIV2HI or
+ // __MULTUSCYC or __MULTSHCYC or
+ // __DDATAH or __HI_R or __MCLA or __MCLASH) begin
+
+ // always @(/*AUTOSENSE*/DDATAH or HI_R or MCLA or MCLASH) begin
+`define DMCLASH MCLASH
+`define DCONST 1'b1
+ always @(/*AUTOSENSE*/CEIopMADH_E_D2_R or CEIopMAZH_E_D2_R or DDATAH or DIV2HI or MCLA or MCLASH
+ or MULTSHCYC or MULTUSCYC) begin
+
+ case (1'b1)
+ CEIopMADH_E_D2_R: HI_P = MCLA;
+ CEIopMAZH_E_D2_R: HI_P = MCLA;
+ DIV2HI: HI_P = DDATAH;
+ MULTUSCYC: HI_P = MCLA;
+ MULTSHCYC: HI_P = `DMCLASH;
+ default: HI_P = `DCONST;
+ endcase
+ end
+endmodule
+
+// Local Variables:
+// verilog-auto-read-includes:t
+// End:
diff --git a/tests_ok/src_frag.vs b/tests_ok/src_frag.vs
new file mode 100644
index 0000000..7a58e3c
--- /dev/null
+++ b/tests_ok/src_frag.vs
@@ -0,0 +1,77 @@
+module src_frag (
+ input logic inp_signal_0, // Input Signal 0
+ input logic inp_signal_1, // Input Signal 1
+ input logic inp_signal_2, // Input Signal 2
+ input logic [10:0] inp_signal_3; // Input Signal 3
+ input logic inp_signal_4, // Input Signal 4
+ output logic outp_signal_0, // Output Signal 0
+ inout logic test,
+ output logic outp_signal_1 // Output Signal 1
+ );
+
+ logic [7:0] local_0; // Local Signal 0
+ logic local_1; // Local Signal 1
+ logic local_3; // Local Signal 3
+ var logic local_4; // Local Signal 4
+ var logic local_5; // Local Signal 5
+ logic signed [1:0] local_6;
+
+ logic local_1; // Local Signal 1
+ input logic in_lg;
+ inout logic io_lg;
+ output logic o_lg;
+ ref logic r_lg;
+ const logic c_rg;
+ static logic s_rg;
+ protected logic p_lg;
+ local logic l_lg;
+ localparam logic lp_lg = 23;
+ parameter logic p_lg = 32;
+ typedef logic td_lg;
+ input wire foo;
+ logic local_3; // Local Signal 3
+ var logic local_5; // Local Signal 5
+ byte B;
+ shortint si;
+ int f;
+ longint li;
+ integer I;
+ int unsigned uI;
+ time t;
+ bit b;
+ logic l;
+ reg r;
+ shortreal sR;
+ real R;
+ realtime Rt;
+ supply0 s0;
+ supply1 s1;
+ tri tr;
+ triand tra;
+ trior tro;
+ trireg trr;
+ tri0 tr0;
+ tri1 tr1;
+ uwire uw;
+ wire w;
+ wand wa;
+ wor wo;
+ string s;
+ event e;
+ chandle ch;
+ virtual v;
+ enum en;
+ genvar g;
+ struct st;
+ union u;
+ mailbox mb;
+ semaphore sm;
+
+
+ defparam v_lg = 56;
+
+endmodule // src_frag
+
+// Local Variables:
+// mode: Verilog
+// End:
diff --git a/tests_ok/sv_import.v b/tests_ok/sv_import.v
new file mode 100644
index 0000000..1aa89ef
--- /dev/null
+++ b/tests_ok/sv_import.v
@@ -0,0 +1,7 @@
+module dpi_test ();
+ /* FIXME
+ import "DPI-C" context task c_task (input int i,
+ output int o);
+ logic [7:0] byte_array[1:20];
+ */
+endmodule // dpi_test
diff --git a/tests_ok/t_autoinst_def_clk.v b/tests_ok/t_autoinst_def_clk.v
new file mode 100644
index 0000000..ae19ba9
--- /dev/null
+++ b/tests_ok/t_autoinst_def_clk.v
@@ -0,0 +1,41 @@
+module t_autoinst_def_clk
+ (/*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input a, // To sub of sub.v
+ input b, // To sub of sub.v
+ input clk, // To sub of sub.v
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output c // From sub of sub.v
+ // End of automatics
+ );
+
+ sub sub
+ (/*AUTOINST*/
+ // Outputs
+ .c (c),
+ // Inputs
+ .clk (clk),
+ .a (a),
+ .b (b));
+
+endmodule // sdc_wombat
+
+module sub
+ (input clk,
+
+ input a,
+ input b,
+
+ output c
+ );
+
+ clocking cb
+ @(posedge clk);
+ endclocking
+
+ default clocking cb;
+
+endmodule
diff --git a/tests_ok/task.v b/tests_ok/task.v
new file mode 100644
index 0000000..3052a57
--- /dev/null
+++ b/tests_ok/task.v
@@ -0,0 +1,14 @@
+module foo(input bit [3:0] def,
+ input bit ghi,
+ input bit [1:0] jkl);
+
+ task cba(input bit [3:0] a,
+ input b,
+ c);
+ endtask // cba
+ task abc(input bit [3:0] def,
+ input bit ghi,
+ input bit [1:0] jkl);
+
+ endtask // abc
+endmodule // foo
diff --git a/tests_ok/testcase.sv b/tests_ok/testcase.sv
new file mode 100644
index 0000000..1ccf7d8
--- /dev/null
+++ b/tests_ok/testcase.sv
@@ -0,0 +1,17 @@
+`define moo 1
+class foo;
+ extern function void bar();
+endclass: foo
+
+function void foo::bar();
+ int variable;
+endfunction: bar
+
+`define moo 1
+class fu;
+ extern function void br();
+endclass: fu
+
+function void fu::br();
+ int variable;
+endfunction: br
diff --git a/tests_ok/testcases.v b/tests_ok/testcases.v
new file mode 100644
index 0000000..33c84a2
--- /dev/null
+++ b/tests_ok/testcases.v
@@ -0,0 +1,217 @@
+//Verilint 182 off // WARNING: Illegal statement for synthesis: $realtobits (in1)
+//Verilint 311 off // WARNING: Converting real to unsigned: $realtobits (in1)
+//Verilint 20 off // WARNING: Assign statement may not be synthesizable: assign out7[i] = ...;
+//Verilint 599 off // WARNING: This construct is not supported by Synopsys
+//Verilint 433 off // WARNING: More than one top level module
+//Verilint 71 off // WARNING: Case statement without default clause
+
+module testmodule (/*AUTOARG*/
+ // Outputs
+ out1, out2, out3, out4, out5, out7, out8, outb2, outb3, outb4, outb6, outb7, outb8, outb9,
+ outb10, outw1, outw2, outw3,
+ // Inputs
+ in1, in2, in3, in4, in5
+ );
+
+
+ function [2:0] ffs;
+ input [2:0] in;
+ ffs = in & 3'b010;
+ endfunction
+
+ task show;
+ input [2:0] in;
+ begin
+ $display ("Hi %x", in);
+ end
+ endtask
+
+ input [2:0] in1,in2,in3,in4,in5;
+ output [2:0] out1, out2,out3,out4,out5,out7,out8;
+ output outb2,outb3,outb4,outb6,outb7,outb8,outb9,outb10;
+ output [7:0] outw1,outw2,outw3;
+ reg [2:0] memarry [0:2];
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg [2:0] out1;
+ reg [2:0] out2;
+ reg [2:0] out3;
+ reg [2:0] out4;
+ reg [2:0] out5;
+ reg [2:0] out8;
+ reg outb2;
+ reg outb3;
+ reg outb4;
+ reg outb6;
+ reg outb7;
+ reg [7:0] outw1;
+ reg [7:0] outw2;
+ reg [7:0] outw3;
+ // End of automatics
+
+ wire outb8=1'b1, outb9=|{in1[0],in2[0]}, outb10=1'b0;
+
+ always @(/*AUTOSENSE*/in1 or in2 or in3 or in4) begin
+ :ignore_label
+ out1 = $realtobits(in1);
+ out2 = ffs(in1 | (in2) );
+ out3 = ffs /*check*/ (in2);
+ $display ("chk ", in1);
+ show (in4);
+ if (|in3) out4=1; else out4=0;
+ end
+
+ always @ (/*AUTOSENSE*/in1 or in2 or in3 or in5) begin
+ casex ({in5[1:0], (3'b010==in2)})
+ 3'bx_1_0: out5=3'b000;
+ 3'bx_1_1: out5=3'b010;
+ 3'bx_0_x: out5=3'b100;
+ endcase
+ casex ({in3[in1]})
+ 1'bx: out5=3'b000;
+ endcase
+ end
+
+ /*AUTO_CONSTANT (`temp) */
+
+`define temp 3'b010
+ always @(/*AUTOSENSE*/in3) begin
+ outb6 = (in3 == `temp);
+ end
+
+ integer i;
+ reg [2:0] out7;
+ always @ (/*AUTOSENSE*/in1) begin
+ for (i=0; i<3; i=i+1) begin
+ assign out7[i] = ~in1[i];
+ end
+ end
+
+ always @ (/*AUTOSENSE*/in1 or in2 or in3) begin
+ {outw1 [ffs(in1)], outw2 [ffs(in2)]} = 2'b10;
+ {outw3[(|in1)?in2:in3], outb2} = 2'b10;
+ end
+
+ initial memarry[0] = in2;
+ always @ (/*AUTOSENSE*/ /*memory or*/ in1) begin
+ $display (memarry[in1]);
+ end
+
+ always @(/*AUTOSENSE*/in1 or in2)
+ casex(in1[1:0]) // synopsys full_case parallel_case
+ 2'b01 : out8 = 3'b001;
+ 2'b10 : out8 = 3'b010;
+ default
+ out8 = in2;
+ endcase
+
+ parameter READ = 3'b111,
+ //WRITE = 3'b111,
+ CFG = 3'b010;
+ //supply1 one;
+
+ always @(/*AUTOSENSE*/in1 or in2) begin
+ outb7 = (in1==READ) || (in2==CFG);
+ end
+
+ always @(/*AUTOSENSE*/in1) begin
+ if (|in1) $display("We're at %t\n",$time);
+ end // case: default
+
+`define shift_instr 5'b01011
+ always @(/*AUTOSENSE*/in1 or in2 or in3 or in4 or in5 or outw1)
+ /*AUTO_CONSTANT(`shift_instr)*/
+ begin: label_no_sense
+ casex (outw1) // synopsys full_case parallel_case
+ {`shift_instr,3'bxxx}:
+ outb3 = in3[0];
+ 8'b00001x10: outb3 = in4[0];
+ 8'b00110011:
+ if (in5[0])
+ outb3 = in1[0];
+ else
+ outb3 = in2[1];
+ default
+ outb3 = in4[0];
+ endcase
+ end
+
+ parameter WIDLE = 0; // No Manual Write Burst
+
+ always @ (/*AUTOSENSE*/in1 or in2 or in3 or in4) begin
+ case(1'b1)
+ in2[WIDLE]:
+ outb4 = in1[0];
+ in3[in4]:
+ outb4 = in1[0];
+ default:
+ outb4 = 1'bx;
+ endcase
+ end
+
+endmodule
+
+module darren_jones_2 (/*AUTOARG*/
+ // Outputs
+ next_WSTATE,
+ // Inputs
+ WSTATE
+ );
+ input [1:0] WSTATE;
+ output [1:0] next_WSTATE;
+ reg [1:0] next_WSTATE;
+ parameter
+ WIDLE = 0, // No Manual Write Burst
+ WCB0 = 1; // 1st of the 4 Manual Write Burst
+
+ always @ (/*AUTOSENSE*/WSTATE) begin
+ next_WSTATE = 2'b0;
+ case (1'b1)
+ WSTATE[WIDLE]:
+ next_WSTATE[1'b0] = 1'b1;
+ WSTATE[WCB0]:
+ next_WSTATE[WCB0] = 1'b1;
+ endcase
+ end
+endmodule
+
+module darren_jones_3 (/*AUTOARG*/
+ // Outputs
+ var1,
+ // Inputs
+ state
+ );
+ input [2:1] state;
+ output var1;
+ reg var1;
+
+ parameter
+ IDLE = 1,
+ CAS1 = 2;
+
+ always @(/*AUTOSENSE*/state) begin
+ case (1'b1)
+ state[IDLE] : begin
+ var1 = 1'b1;
+ end
+ state[CAS1] : begin
+ var1 = 1'b1;
+ end
+ default : begin
+ var1 = 1'b1;
+ end
+ endcase
+ end
+
+ always @(/*AUTOSENSE*/add or lo or mc_32pff or mc_losel or slo or var1) begin
+ case(mc_losel)
+ 6'b000001: lo_mux = mc_32pff ? {add[39:0],lo[31:8]} :
+ {add[7:0],lo[63:8]};
+
+ 6'b010000: lo_mux = lo;
+ 6'b100000: lo_mux = var1 ? IDLE : slo;
+ endcase
+ end // always @ (...
+
+endmodule
diff --git a/tests_ok/tss_max32.v b/tests_ok/tss_max32.v
new file mode 100644
index 0000000..05b654c
--- /dev/null
+++ b/tests_ok/tss_max32.v
@@ -0,0 +1,43 @@
+// $Id: tss_max32.v,v 1.6 1999/01/20 17:34:54 wsnyder Exp $
+//============================================================================
+
+`time_scale
+
+module tss_max32 (/*AUTOARG*/
+ // Outputs
+ max,
+ // Inputs
+ a, b
+ );
+
+ //======================================================================
+ // Inputs/Outputs
+ //======================================================================
+
+ input [31:0] a; // Time a
+ input [31:0] b; // Time b
+ output [31:0] max; // MAX (a,b)
+
+ //======================================================================
+ // Automatic Wire/Register Declarations
+ //======================================================================
+
+ /*AUTOREG*/
+
+ //======================================================================
+ // Comparison
+ //======================================================================
+
+ wire alessb; // a<b or carry
+ //Verilint 110 off // WARNING: Incompatible width
+ DW01_cmp2 #(31) cmp (.LT_LE(alessb), .GE_GT(unused_ok),
+ .A(a[30:0]),
+ .B(b[30:0]),
+ .LEQ(1'b0), .TC(1'b0));
+ //Verilint 110 on // WARNING: Incompatible width
+
+ // Note because a has more bits we MUST choose it if a[31:8]==b[31:8]!
+ wire sela = ((a[31] != b[31]) ^ alessb);
+ wire [31:0] max = (sela ? b : a);
+
+endmodule
diff --git a/tests_ok/two_modules.v b/tests_ok/two_modules.v
new file mode 100644
index 0000000..b4c782d
--- /dev/null
+++ b/tests_ok/two_modules.v
@@ -0,0 +1,63 @@
+// Example module that doesn't instantiate
+module appendix1 (/*AUTOARG*/
+ // Outputs
+ z,
+ // Inputs
+ i
+ );
+ input i;
+ output z;
+
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg z;
+ // End of automatics
+
+ /*AUTOWIRE*/
+
+ always @ (/*AUTOSENSE*/i) begin
+ z = i;
+ end
+endmodule
+
+// Example module that does instantiate
+module appendix2 (/*AUTOARG*/
+ // Outputs
+ z,
+ // Inputs
+ i
+ );
+
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input i; // To apx10 of appendix1.v, ...
+ // End of automatics
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [11:10] z; // From apx10 of appendix1.v, ...
+ // End of automatics
+
+ /*AUTOREG*/
+
+ /*AUTOWIRE*/
+
+ /*
+ appendix1 AUTO_TEMPLATE (
+ .z (z[@]),
+ );
+ */
+
+ appendix1 apx10 (/*AUTOINST*/
+ // Outputs
+ .z (z[10]), // Templated
+ // Inputs
+ .i (i));
+
+ appendix1 apx11 (/*AUTOINST*/
+ // Outputs
+ .z (z[11]), // Templated
+ // Inputs
+ .i (i));
+
+endmodule
diff --git a/tests_ok/v2k_inst_hicks.v b/tests_ok/v2k_inst_hicks.v
new file mode 100644
index 0000000..1e59580
--- /dev/null
+++ b/tests_ok/v2k_inst_hicks.v
@@ -0,0 +1,28 @@
+
+// 2001 Parameter Style
+module v2k_inst_hicks (
+ output wire [7:0] relay,
+ output wire relay_f,
+ output wire swen_f0_n,
+ input [31:0] dcb,
+ input relay_ce,
+ input wire simReset,
+ input wire clock
+ );
+
+ input [31:0] dcb_n2k;
+
+ // AUTOINST results NOT OK
+ v2k_inst_hicks v2k_inst_hicks (/*AUTOINST*/
+ // Outputs
+ .relay (relay[7:0]),
+ .relay_f (relay_f),
+ .swen_f0_n (swen_f0_n),
+ // Inputs
+ .dcb (dcb[31:0]),
+ .relay_ce (relay_ce),
+ .simReset (simReset),
+ .clock (clock),
+ .dcb_n2k (dcb_n2k[31:0]));
+
+endmodule
diff --git a/tests_ok/v2k_localparam.v b/tests_ok/v2k_localparam.v
new file mode 100644
index 0000000..06be0b1
--- /dev/null
+++ b/tests_ok/v2k_localparam.v
@@ -0,0 +1,14 @@
+
+// 2001 Parameter Style
+module v2k_localparam;
+
+ localparam X = 10;
+ parameter Y = 10;
+
+ reg z;
+
+ always @ (/*AS*/) begin
+ z = X | Y;
+ end
+
+endmodule
diff --git a/tests_ok/v2k_signed_kundsen.v b/tests_ok/v2k_signed_kundsen.v
new file mode 100644
index 0000000..382c815
--- /dev/null
+++ b/tests_ok/v2k_signed_kundsen.v
@@ -0,0 +1,21 @@
+module foo_bar (/*AUTOARG*/
+ // Outputs
+ result,
+ // Inputs
+ clk, rst, data, addr
+ )
+
+ input clk;
+ input rst;
+ input signed [15:-15] data;
+ input [11:0] addr;
+ output signed [15:0] result;
+
+ wire signed [15:-15] data;
+ reg signed [15:0] result;
+
+ always @ (/*AS*/rst) begin
+ result = 32'sh22 | rst;
+ end
+
+endmodule // foo_bar
diff --git a/tests_ok/v2k_typedef_yee.v b/tests_ok/v2k_typedef_yee.v
new file mode 100644
index 0000000..b4ec074
--- /dev/null
+++ b/tests_ok/v2k_typedef_yee.v
@@ -0,0 +1,82 @@
+
+`include "v2k_typedef_yee_inc.v"
+module v2k_typedef_yee
+ (/*AUTOARG*/
+ // Outputs
+ sub2_out_pixel, ready, sub1_to_sub2_and_top,
+ // Inputs
+ sub1_in_pixel, reset, pixel_ff, cp
+ );
+
+ //-----------------------
+ // Output definitions
+ //
+ output logic_t sub1_to_sub2_and_top; // Explicit output port
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output logic_t ready; // From itest_sub2 of v2k_typedef_yee_sub2.v
+ output pixel24_t sub2_out_pixel; // From itest_sub2 of v2k_typedef_yee_sub2.v
+ // End of automatics
+
+
+ //-----------------------
+ // Input definitions
+ //
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input logic_t cp; // To itest_sub1 of v2k_typedef_yee_sub1.v, ...
+ input logic_t pixel24_t pixel_ff; // To itest_sub2 of v2k_typedef_yee_sub2.v
+ input logic_t reset; // To itest_sub1 of v2k_typedef_yee_sub1.v, ...
+ input pixel24_t sub1_in_pixel; // To itest_sub1 of v2k_typedef_yee_sub1.v
+ // End of automatics
+
+
+ //-----------------------
+ // Wire definitions
+ //
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ pixel24_t sub1_out_pixel; // From itest_sub1 of v2k_typedef_yee_sub1.v
+ logic_t sub1_to_sub2; // From itest_sub1 of v2k_typedef_yee_sub1.v
+ // End of automatics
+
+
+
+ //-----------------------
+ // Module instantiations
+ //
+ v2k_typedef_yee_sub1 itest_sub1
+ (/*AUTOINST*/
+ // Outputs
+ .sub1_out_pixel (sub1_out_pixel),
+ .sub1_to_sub2 (sub1_to_sub2),
+ .sub1_to_sub2_and_top (sub1_to_sub2_and_top),
+ // Inputs
+ .sub1_in_pixel (sub1_in_pixel),
+ .cp (cp),
+ .reset (reset));
+
+ /*v2k_typedef_yee_sub2 AUTO_TEMPLATE (
+ .sub2_in_pixel (sub1_out_pixel),
+ )
+ */
+ v2k_typedef_yee_sub2 itest_sub2
+ (/*AUTOINST*/
+ // Outputs
+ .sub2_out_pixel (sub2_out_pixel),
+ .ready (ready),
+ // Inputs
+ .sub2_in_pixel (sub1_out_pixel), // Templated
+ .cp (cp),
+ .reset (reset),
+ .sub1_to_sub2 (sub1_to_sub2),
+ .sub1_to_sub2_and_top (sub1_to_sub2_and_top),
+ .pixel_ff (pixel_ff));
+
+
+endmodule
+
+// Local Variables:
+// verilog-typedef-regexp: "_t$"
+// End:
diff --git a/tests_ok/v2k_typedef_yee_inc.v b/tests_ok/v2k_typedef_yee_inc.v
new file mode 100644
index 0000000..be9f5a2
--- /dev/null
+++ b/tests_ok/v2k_typedef_yee_inc.v
@@ -0,0 +1,28 @@
+`ifdef __TEST_I
+
+`else
+
+ `define __TEST_I
+
+ `ifdef TWO_STATE_LOGIC
+typedef bit logic_t; // Use two-state logic
+ `else
+typedef logic logic_t; // Use four-state logic
+ `endif
+
+typedef reg ff_t; // Default F/F type
+typedef reg lat_t; // Default latch type
+
+//----------------------------
+// 24 bit wide pixel types
+//
+typedef union packed {
+ logic_t [23:0] bits;
+ struct packed {
+ logic_t [7:0] red;
+ logic_t [7:0] grn;
+ logic_t [7:0] blu;
+ } color;
+} pixel24_t;
+
+`endif
diff --git a/tests_ok/v2k_typedef_yee_sub1.v b/tests_ok/v2k_typedef_yee_sub1.v
new file mode 100644
index 0000000..923ccce
--- /dev/null
+++ b/tests_ok/v2k_typedef_yee_sub1.v
@@ -0,0 +1,29 @@
+
+`include "v2k_typedef_yee_inc.v"
+module v2k_typedef_yee_sub1
+ (
+ output pixel24_t sub1_out_pixel,
+ input pixel24_t sub1_in_pixel,
+ input logic_t cp,
+ input logic_t reset,
+ output logic_t sub1_to_sub2,
+ output logic_t sub1_to_sub2_and_top
+ );
+
+
+ pixel24_t pixel_ff;
+
+
+ always_ff @(posedge cp) begin
+ pixel_ff <= sub1_in_pixel;
+ end
+
+ assign sub1_out_pixel = pixel_ff;
+ assign sub1_to_sub2 = '1;
+ assign sub1_to_sub2_and_top = '1;
+
+endmodule
+
+// Local Variables:
+// verilog-typedef-regexp: "_t$"
+// End:
diff --git a/tests_ok/v2k_typedef_yee_sub2.v b/tests_ok/v2k_typedef_yee_sub2.v
new file mode 100644
index 0000000..108bdd6
--- /dev/null
+++ b/tests_ok/v2k_typedef_yee_sub2.v
@@ -0,0 +1,35 @@
+
+`include "v2k_typedef_yee_inc.v"
+module v2k_typedef_yee_sub2
+ (/*AUTOARG*/
+ // Outputs
+ sub2_out_pixel, ready,
+ // Inputs
+ sub2_in_pixel, cp, reset, sub1_to_sub2, sub1_to_sub2_and_top, pixel_ff
+ );
+
+ output pixel24_t sub2_out_pixel,
+ output logic_t ready,
+ input pixel24_t sub2_in_pixel,
+ input logic_t cp,
+ input logic_t reset,
+ input logic_t sub1_to_sub2,
+ input logic_t sub1_to_sub2_and_top
+
+ pixel24_t pixel_ff;
+ ff_t sub1_to_sub2_ff;
+
+
+ always_ff @(posedge cp) begin
+ pixel_ff <= sub2_in_pixel;
+ sub1_to_sub2_ff <= sub1_to_sub2;
+ end
+
+ assign sub2_out_pixel = pixel_ff;
+ assign ready = sub1_to_sub2_ff;
+
+endmodule
+
+// Local Variables:
+// verilog-typedef-regexp: "_t$"
+// End:
diff --git a/tests_ok/verilint_113.v b/tests_ok/verilint_113.v
new file mode 100644
index 0000000..62e9e96
--- /dev/null
+++ b/tests_ok/verilint_113.v
@@ -0,0 +1,26 @@
+module cdl_io (/*AUTOARG*/
+ // Outputs
+ topsig,
+ // Inputs
+ clk
+ );
+
+ input clk;
+ output topsig;
+
+ //Verilint 113 off // WARNING: in macro RSV_CDLBASE_RDWR, Multiple drivers to a flipflop
+
+ reg topsig;
+`define TOPSIG {topsig}
+
+ always @ (posedge clk) begin
+ `TOPSIG <= #0 1'b1;
+ end
+
+ task direct_write;
+ input val;
+ begin
+ `TOPSIG = val;
+ end
+ endtask
+endmodule
diff --git a/tests_ok/vmm_regressions.sv b/tests_ok/vmm_regressions.sv
new file mode 100644
index 0000000..a67c922
--- /dev/null
+++ b/tests_ok/vmm_regressions.sv
@@ -0,0 +1,251 @@
+
+`include "vmm.sv"
+
+class my_xactor extends vmm_xactor;
+ typedef enum { AA, BB, CC } e_myenum;
+ typedef class t_mydata;
+ typedef class t_myclass;
+
+ int myint;
+ int myintarr[10];
+ int myintda[];
+ int myintaa_int[int];
+ int myintaa_str[string];
+
+ string mystr;
+ string mystrarr[10];
+ string mystrda[];
+ string mystraa_int[int];
+ string mystraa_str[string];
+
+ e_myenum myenum;
+ e_myenum myenumarr[10];
+ e_myenum myenumda[];
+ e_myenum myenumaa_int[int];
+ e_myenum myenumaa_str[string];
+
+ t_mydata mydata;
+ t_mydata mydataarr[10];
+ t_mydata mydatada[];
+ t_mydata mydataaa_int[int];
+ t_mydata mydataaa_str[string];
+
+ t_myclass myclass;
+ t_myclass myclassarr[10];
+ t_myclass myclassda[];
+ t_myclass myclassaa_int[int];
+ t_myclass myclassaa_str[string];
+
+ vmm_channel mych;
+ vmm_channel mycharr[10];
+ vmm_channel mychda[];
+ vmm_channel mychaa_int[int];
+ vmm_channel mychaa_str[string];
+
+ vmm_xactor myxact;
+ vmm_xactor myxactarr[10];
+ vmm_xactor myxactda[];
+ vmm_xactor myxactaa_int[int];
+ vmm_xactor myxactaa_str[string];
+
+ vmm_subenv mysub;
+ vmm_subenv mysubarr[10];
+ vmm_subenv mysubda[];
+ vmm_subenv mysubaa_int[int];
+ vmm_subenv mysubaa_str[string];
+
+ vmm_scenario mysc;
+
+ `vmm_data_member_begin(my_xactor)
+ `vmm_data_member_scalar(myint, DO_ALL)
+ `vmm_data_member_scalar_array(myintarr, DO_ALL )
+ `vmm_data_member_da(myintda, DO_ALL )
+ `vmm_data_member_scalar_aa_scalar(myintaa_int, DO_ALL )
+ `vmm_data_member_scalar_aa_string(myintaa_str, DO_ALL )
+
+ `vmm_data_member_string(mystr, DO_ALL)
+ `vmm_data_member_string_array(mystrarr, DO_ALL)
+ `vmm_data_member_string_da(mystrda, DO_ALL)
+ `vmm_data_member_string_aa_scalar(mystraa_int, DO_ALL)
+ `vmm_data_member_string_aa_string(mystraa_str, DO_ALL)
+
+ `vmm_data_member_enum(myenum, DO_ALL)
+ `vmm_data_member_enum_array(myenumarr, DO_ALL)
+ `vmm_data_member_enum_da(myenumda, DO_ALL)
+ `vmm_data_member_enum_aa_scalar(myenumaa_int, DO_ALL)
+ `vmm_data_member_enum_aa_string(myenumaa_str, DO_ALL)
+
+ `vmm_data_member_vmm_data(mydata, DO_ALL, DO_DEEP )
+ `vmm_data_member_vmm_data_array(mydataarr, DO_ALL, DO_DEEP )
+ `vmm_data_member_vmm_data_da(mydatada, DO_ALL, DO_DEEP )
+ `vmm_data_member_vmm_data_aa_scalar(mydataaa_int, DO_ALL, DO_DEEP )
+ `vmm_data_member_vmm_data_aa_string(mydataaa_str, DO_ALL, DO_DEEP )
+
+ `vmm_data_member_handle(myclass, DO_ALL )
+ `vmm_data_member_handle_array(myclassarr, DO_ALL )
+ `vmm_data_member_handle_da(myclassda, DO_ALL )
+ `vmm_data_member_handle_aa_scalar(myclassaa_int, DO_ALL )
+ `vmm_data_member_handle_aa_string(myclassaa_str, DO_ALL )
+ `vmm_data_member_end(my_xactor)
+
+ `vmm_env_member_begin(my_xactor)
+ `vmm_env_member_scalar(myint, DO_ALL)
+ `vmm_env_member_scalar_array(myintarr, DO_ALL )
+ `vmm_env_member_da(myintda, DO_ALL )
+ `vmm_env_member_scalar_aa_scalar(myintaa_int, DO_ALL )
+ `vmm_env_member_scalar_aa_string(myintaa_str, DO_ALL )
+
+ `vmm_env_member_string(mystr, DO_ALL)
+ `vmm_env_member_string_array(mystrarr, DO_ALL)
+ `vmm_env_member_string_da(mystrda, DO_ALL)
+ `vmm_env_member_string_aa_scalar(mystraa_int, DO_ALL)
+ `vmm_env_member_string_aa_string(mystraa_str, DO_ALL)
+
+ `vmm_env_member_enum(myenum, DO_ALL)
+ `vmm_env_member_enum_array(myenumarr, DO_ALL)
+ `vmm_env_member_enum_da(myenumda, DO_ALL)
+ `vmm_env_member_enum_aa_scalar(myenumaa_int, DO_ALL)
+ `vmm_env_member_enum_aa_string(myenumaa_str, DO_ALL)
+
+ `vmm_env_member_vmm_data(mydata, DO_ALL )
+ `vmm_env_member_vmm_data_array(mydataarr, DO_ALL )
+ `vmm_env_member_vmm_data_da(mydatada, DO_ALL )
+ `vmm_env_member_vmm_data_aa_scalar(mydataaa_int, DO_ALL )
+ `vmm_env_member_vmm_data_aa_string(mydataaa_str, DO_ALL )
+
+ `vmm_env_member_channel(mych, DO_ALL )
+ `vmm_env_member_channel_array(mycharr, DO_ALL )
+ `vmm_env_member_channel_da(mychda, DO_ALL )
+ `vmm_env_member_channel_aa_scalar(mychaa_int, DO_ALL )
+ `vmm_env_member_channel_aa_string(mychaa_str, DO_ALL )
+
+ `vmm_env_member_xactor(myxact, DO_ALL )
+ `vmm_env_member_xactor_array(myxactarr, DO_ALL )
+ `vmm_env_member_xactor_da(myxactda, DO_ALL )
+ `vmm_env_member_xactor_aa_scalar(myxactaa_int, DO_ALL )
+ `vmm_env_member_xactor_aa_string(myxactaa_str, DO_ALL )
+
+ `vmm_env_member_subenv(mysub, DO_ALL )
+ `vmm_env_member_subenv_array(mysubarr, DO_ALL )
+ `vmm_env_member_subenv_da(mysubda, DO_ALL )
+ `vmm_env_member_subenv_aa_scalar(mysubaa_int, DO_ALL )
+ `vmm_env_member_subenv_aa_string(mysubaa_str, DO_ALL )
+ `vmm_env_member_end(my_xactor)
+
+ `vmm_scenario_member_begin(my_xactor)
+ `vmm_scenario_member_scalar(myint, DO_ALL)
+ `vmm_scenario_member_scalar_array(myintarr, DO_ALL )
+ `vmm_scenario_member_da(myintda, DO_ALL )
+ `vmm_scenario_member_scalar_aa_scalar(myintaa_int, DO_ALL )
+ `vmm_scenario_member_scalar_aa_string(myintaa_str, DO_ALL )
+
+ `vmm_scenario_member_string(mystr, DO_ALL)
+ `vmm_scenario_member_string_array(mystrarr, DO_ALL)
+ `vmm_scenario_member_string_da(mystrda, DO_ALL)
+ `vmm_scenario_member_string_aa_scalar(mystraa_int, DO_ALL)
+ `vmm_scenario_member_string_aa_string(mystraa_str, DO_ALL)
+
+ `vmm_scenario_member_enum(myenum, DO_ALL)
+ `vmm_scenario_member_enum_array(myenumarr, DO_ALL)
+ `vmm_scenario_member_enum_da(myenumda, DO_ALL)
+ `vmm_scenario_member_enum_aa_scalar(myenumaa_int, DO_ALL)
+ `vmm_scenario_member_enum_aa_string(myenumaa_str, DO_ALL)
+
+ `vmm_scenario_member_vmm_data(mydata, DO_ALL, DO_DEEP )
+ `vmm_scenario_member_vmm_data_array(mydataarr, DO_ALL, DO_DEEP )
+ `vmm_scenario_member_vmm_data_da(mydatada, DO_ALL, DO_DEEP )
+ `vmm_scenario_member_vmm_data_aa_scalar(mydataaa_int, DO_ALL, DO_DEEP )
+ `vmm_scenario_member_vmm_data_aa_string(mydataaa_str, DO_ALL, DO_DEEP )
+
+ `vmm_scenario_member_handle(myclass, DO_ALL )
+ `vmm_scenario_member_handle_array(myclassarr, DO_ALL )
+ `vmm_scenario_member_handle_da(myclassda, DO_ALL )
+ `vmm_scenario_member_handle_aa_scalar(myclassaa_int, DO_ALL )
+ `vmm_scenario_member_handle_aa_string(myclassaa_str, DO_ALL )
+
+ `vmm_scenario_member_vmm_scenario(mysc, DO_ALL )
+ `vmm_scenario_member_end(my_xactor)
+
+ `vmm_subenv_member_begin(my_xactor)
+ `vmm_subenv_member_scalar(myint, DO_ALL)
+ `vmm_subenv_member_scalar_array(myintarr, DO_ALL )
+ `vmm_subenv_member_da(myintda, DO_ALL )
+ `vmm_subenv_member_scalar_aa_scalar(myintaa_int, DO_ALL )
+ `vmm_subenv_member_scalar_aa_string(myintaa_str, DO_ALL )
+
+ `vmm_subenv_member_string(mystr, DO_ALL)
+ `vmm_subenv_member_string_array(mystrarr, DO_ALL)
+ `vmm_subenv_member_string_da(mystrda, DO_ALL)
+ `vmm_subenv_member_string_aa_scalar(mystraa_int, DO_ALL)
+ `vmm_subenv_member_string_aa_string(mystraa_str, DO_ALL)
+
+ `vmm_subenv_member_enum(myenum, DO_ALL)
+ `vmm_subenv_member_enum_array(myenumarr, DO_ALL)
+ `vmm_subenv_member_enum_da(myenumda, DO_ALL)
+ `vmm_subenv_member_enum_aa_scalar(myenumaa_int, DO_ALL)
+ `vmm_subenv_member_enum_aa_string(myenumaa_str, DO_ALL)
+
+ `vmm_subenv_member_vmm_data(mydata, DO_ALL )
+ `vmm_subenv_member_vmm_data_array(mydataarr, DO_ALL )
+ `vmm_subenv_member_vmm_data_da(mydatada, DO_ALL )
+ `vmm_subenv_member_vmm_data_aa_scalar(mydataaa_int, DO_ALL )
+ `vmm_subenv_member_vmm_data_aa_string(mydataaa_str, DO_ALL )
+
+ `vmm_subenv_member_channel(mych, DO_ALL )
+ `vmm_subenv_member_channel_array(mycharr, DO_ALL )
+ `vmm_subenv_member_channel_da(mychda, DO_ALL )
+ `vmm_subenv_member_channel_aa_scalar(mychaa_int, DO_ALL )
+ `vmm_subenv_member_channel_aa_string(mychaa_str, DO_ALL )
+
+ `vmm_subenv_member_xactor(myxact, DO_ALL )
+ `vmm_subenv_member_xactor_array(myxactarr, DO_ALL )
+ `vmm_subenv_member_xactor_da(myxactda, DO_ALL )
+ `vmm_subenv_member_xactor_aa_scalar(myxactaa_int, DO_ALL )
+ `vmm_subenv_member_xactor_aa_string(myxactaa_str, DO_ALL )
+
+ `vmm_subenv_member_subenv(mysub, DO_ALL )
+ `vmm_subenv_member_subenv_array(mysubarr, DO_ALL )
+ `vmm_subenv_member_subenv_da(mysubda, DO_ALL )
+ `vmm_subenv_member_subenv_aa_scalar(mysubaa_int, DO_ALL )
+ `vmm_subenv_member_subenv_aa_string(mysubaa_str, DO_ALL )
+ `vmm_subenv_member_end(my_xactor)
+
+ `vmm_xactor_member_begin(my_xactor)
+ `vmm_xactor_member_scalar(myint, DO_ALL)
+ `vmm_xactor_member_scalar_array(myintarr, DO_ALL )
+ `vmm_xactor_member_da(myintda, DO_ALL )
+ `vmm_xactor_member_scalar_aa_scalar(myintaa_int, DO_ALL )
+ `vmm_xactor_member_scalar_aa_string(myintaa_str, DO_ALL )
+
+ `vmm_xactor_member_string(mystr, DO_ALL)
+ `vmm_xactor_member_string_array(mystrarr, DO_ALL)
+ `vmm_xactor_member_string_da(mystrda, DO_ALL)
+ `vmm_xactor_member_string_aa_scalar(mystraa_int, DO_ALL)
+ `vmm_xactor_member_string_aa_string(mystraa_str, DO_ALL)
+
+ `vmm_xactor_member_enum(myenum, DO_ALL)
+ `vmm_xactor_member_enum_array(myenumarr, DO_ALL)
+ `vmm_xactor_member_enum_da(myenumda, DO_ALL)
+ `vmm_xactor_member_enum_aa_scalar(myenumaa_int, DO_ALL)
+ `vmm_xactor_member_enum_aa_string(myenumaa_str, DO_ALL)
+
+ `vmm_xactor_member_vmm_data(mydata, DO_ALL )
+ `vmm_xactor_member_vmm_data_array(mydataarr, DO_ALL )
+ `vmm_xactor_member_vmm_data_da(mydatada, DO_ALL )
+ `vmm_xactor_member_vmm_data_aa_scalar(mydataaa_int, DO_ALL )
+ `vmm_xactor_member_vmm_data_aa_string(mydataaa_str, DO_ALL )
+
+ `vmm_xactor_member_channel(mych, DO_ALL )
+ `vmm_xactor_member_channel_array(mycharr, DO_ALL )
+ `vmm_xactor_member_channel_da(mychda, DO_ALL )
+ `vmm_xactor_member_channel_aa_scalar(mychaa_int, DO_ALL )
+ `vmm_xactor_member_channel_aa_string(mychaa_str, DO_ALL )
+
+ `vmm_xactor_member_xactor(myxact, DO_ALL )
+ `vmm_xactor_member_xactor_array(myxactarr, DO_ALL )
+ `vmm_xactor_member_xactor_da(myxactda, DO_ALL )
+ `vmm_xactor_member_xactor_aa_scalar(myxactaa_int, DO_ALL )
+ `vmm_xactor_member_xactor_aa_string(myxactaa_str, DO_ALL )
+ `vmm_xactor_member_end(my_xactor)
+
+endclass: my_xactor
diff --git a/tests_ok/wasson.v b/tests_ok/wasson.v
new file mode 100644
index 0000000..8143fdf
--- /dev/null
+++ b/tests_ok/wasson.v
@@ -0,0 +1,12 @@
+`define FOO 1'b1
+module foo(__a,b);
+
+ input __a;
+ output b;
+
+ always @(/*AUTOSENSE*/__a or `FOO) begin
+ b = __a ^ `FOO ;
+ end
+
+endmodule
+
diff --git a/tests_ok/xx.v b/tests_ok/xx.v
new file mode 100644
index 0000000..76e24b0
--- /dev/null
+++ b/tests_ok/xx.v
@@ -0,0 +1,13 @@
+always
+ @(w or c_int)
+ begin
+ if ((w == 1'b0) && ((status_register[7]) == 1'b1))
+ begin
+ write_protect <= `TRUE ;
+ end
+ if (w == 1'b1)
+ begin
+ write_protect <= `FALSE ;
+ end
+ end
+
diff --git a/verilog-mode.el b/verilog-mode.el
new file mode 100644
index 0000000..8626680
--- /dev/null
+++ b/verilog-mode.el
@@ -0,0 +1,14497 @@
+;;; verilog-mode.el --- major mode for editing verilog source in Emacs
+
+;; Copyright (C) 1996-2016 Free Software Foundation, Inc.
+
+;; Author: Michael McNamara <mac@verilog.com>
+;; Wilson Snyder <wsnyder@wsnyder.org>
+;; http://www.verilog.com
+;; http://www.veripool.org
+;; Created: 3 Jan 1996
+;; Keywords: languages
+
+;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
+;; file on 19/3/2008, and the maintainer agreed that when a bug is
+;; filed in the Emacs bug reporting system against this file, a copy
+;; of the bug report be sent to the maintainer's email address.
+
+;; This code supports Emacs 21.1 and later
+;; And XEmacs 21.1 and later
+;; Please do not make changes that break Emacs 21. Thanks!
+;;
+;;
+
+;; This file is part of GNU Emacs.
+
+;; GNU Emacs is free software: you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation, either version 3 of the License, or
+;; (at your option) any later version.
+
+;; GNU Emacs is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GNU Emacs. If not, see <http://www.gnu.org/licenses/>.
+
+;;; Commentary:
+
+;; USAGE
+;; =====
+
+;; A major mode for editing Verilog and SystemVerilog HDL source code (IEEE
+;; 1364-2005 and IEEE 1800-2012 standards). When you have entered Verilog
+;; mode, you may get more info by pressing C-h m. You may also get online
+;; help describing various functions by: C-h f <Name of function you want
+;; described>
+
+;; KNOWN BUGS / BUG REPORTS
+;; =======================
+
+;; SystemVerilog is a rapidly evolving language, and hence this mode is
+;; under continuous development. Please report any issues to the issue
+;; tracker at
+;;
+;; http://www.veripool.org/verilog-mode
+;;
+;; Please use verilog-submit-bug-report to submit a report; type C-c
+;; C-b to invoke this and as a result we will have a much easier time
+;; of reproducing the bug you find, and hence fixing it.
+
+;; INSTALLING THE MODE
+;; ===================
+
+;; An older version of this mode may be already installed as a part of
+;; your environment, and one method of updating would be to update
+;; your Emacs environment. Sometimes this is difficult for local
+;; political/control reasons, and hence you can always install a
+;; private copy (or even a shared copy) which overrides the system
+;; default.
+
+;; You can get step by step help in installing this file by going to
+;; <http://www.verilog.com/emacs_install.html>
+
+;; The short list of installation instructions are: To set up
+;; automatic Verilog mode, put this file in your load path, and put
+;; the following in code (please un comment it first!) in your
+;; .emacs, or in your site's site-load.el
+
+;; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
+;; (add-to-list 'auto-mode-alist '("\\.[ds]?vh?\\'" . verilog-mode))
+
+;; Be sure to examine at the help for verilog-auto, and the other
+;; verilog-auto-* functions for some major coding time savers.
+;;
+;; If you want to customize Verilog mode to fit your needs better,
+;; you may add the below lines (the values of the variables presented
+;; here are the defaults). Note also that if you use an Emacs that
+;; supports custom, it's probably better to use the custom menu to
+;; edit these. If working as a member of a large team these settings
+;; should be common across all users (in a site-start file), or set
+;; in Local Variables in every file. Otherwise, different people's
+;; AUTO expansion may result different whitespace changes.
+;;
+;; ;; Enable syntax highlighting of **all** languages
+;; (global-font-lock-mode t)
+;;
+;; ;; User customization for Verilog mode
+;; (setq verilog-indent-level 3
+;; verilog-indent-level-module 3
+;; verilog-indent-level-declaration 3
+;; verilog-indent-level-behavioral 3
+;; verilog-indent-level-directive 1
+;; verilog-case-indent 2
+;; verilog-auto-newline t
+;; verilog-auto-indent-on-newline t
+;; verilog-tab-always-indent t
+;; verilog-auto-endcomments t
+;; verilog-minimum-comment-distance 40
+;; verilog-indent-begin-after-if t
+;; verilog-auto-lineup 'declarations
+;; verilog-highlight-p1800-keywords nil
+;; verilog-linter "my_lint_shell_command"
+;; )
+
+
+;;; History:
+;;
+;; See commit history at http://www.veripool.org/verilog-mode.html
+;; (This section is required to appease checkdoc.)
+
+;;; Code:
+;;
+
+;; This variable will always hold the version number of the mode
+(defconst verilog-mode-version "__VMVERSION__-__VMREVISION__-__VMPACKAGER__"
+ "Version of this Verilog mode.")
+(defconst verilog-mode-release-emacs nil
+ "If non-nil, this version of Verilog mode was released with Emacs itself.")
+
+(defun verilog-version ()
+ "Inform caller of the version of this file."
+ (interactive)
+ (message "Using verilog-mode version %s" verilog-mode-version))
+
+;; Insure we have certain packages, and deal with it if we don't
+;; Be sure to note which Emacs flavor and version added each feature.
+(eval-when-compile
+ ;; Provide stuff if we are XEmacs
+ (when (featurep 'xemacs)
+ (condition-case nil
+ (require 'easymenu)
+ (error nil))
+ (condition-case nil
+ (require 'regexp-opt)
+ (error nil))
+ ;; Bug in 19.28 through 19.30 skeleton.el, not provided.
+ (condition-case nil
+ (load "skeleton")
+ (error nil))
+ (condition-case nil
+ (if (fboundp 'when)
+ nil ; fab
+ (defmacro when (cond &rest body)
+ (list 'if cond (cons 'progn body))))
+ (error nil))
+ (condition-case nil
+ (if (fboundp 'unless)
+ nil ; fab
+ (defmacro unless (cond &rest body)
+ (cons 'if (cons cond (cons nil body)))))
+ (error nil))
+ (condition-case nil
+ (if (fboundp 'store-match-data)
+ nil ; fab
+ (defmacro store-match-data (&rest _args) nil))
+ (error nil))
+ (condition-case nil
+ (if (fboundp 'char-before)
+ nil ; great
+ (defmacro char-before (&rest _body)
+ (char-after (1- (point)))))
+ (error nil))
+ (condition-case nil
+ (if (fboundp 'when)
+ nil ; fab
+ (defsubst point-at-bol (&optional N)
+ (save-excursion (beginning-of-line N) (point))))
+ (error nil))
+ (condition-case nil
+ (if (fboundp 'when)
+ nil ; fab
+ (defsubst point-at-eol (&optional N)
+ (save-excursion (end-of-line N) (point))))
+ (error nil))
+ (condition-case nil
+ (require 'custom)
+ (error nil))
+ (condition-case nil
+ (if (fboundp 'match-string-no-properties)
+ nil ; great
+ (defsubst match-string-no-properties (num &optional string)
+ "Return string of text matched by last search, without text properties.
+NUM specifies which parenthesized expression in the last regexp.
+ Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
+Zero means the entire text matched by the whole regexp or whole string.
+STRING should be given if the last search was by `string-match' on STRING."
+ (if (match-beginning num)
+ (if string
+ (let ((result
+ (substring string
+ (match-beginning num) (match-end num))))
+ (set-text-properties 0 (length result) nil result)
+ result)
+ (buffer-substring-no-properties (match-beginning num)
+ (match-end num)
+ (current-buffer)))))
+ )
+ (error nil))
+ (if (and (featurep 'custom) (fboundp 'custom-declare-variable))
+ nil ; We've got what we needed
+ ;; We have the old custom-library, hack around it!
+ (defmacro defgroup (&rest _args) nil)
+ (defmacro customize (&rest _args)
+ (message
+ "Sorry, Customize is not available with this version of Emacs"))
+ (defmacro defcustom (var value doc &rest _args)
+ `(defvar ,var ,value ,doc))
+ )
+ (if (fboundp 'defface)
+ nil ; great!
+ (defmacro defface (var values doc &rest _args)
+ `(make-face ,var))
+ )
+
+ (if (and (featurep 'custom) (fboundp 'customize-group))
+ nil ; We've got what we needed
+ ;; We have an intermediate custom-library, hack around it!
+ (defmacro customize-group (var &rest _args)
+ `(customize ,var))
+ )
+
+ (defvar inhibit-modification-hooks)
+ (defvar inhibit-point-motion-hooks)
+ (defvar deactivate-mark)
+ )
+ ;;
+ ;; OK, do this stuff if we are NOT XEmacs:
+ (unless (featurep 'xemacs)
+ (unless (fboundp 'region-active-p)
+ (defmacro region-active-p ()
+ `(and transient-mark-mode mark-active))))
+ )
+
+;; Provide a regular expression optimization routine, using regexp-opt
+;; if provided by the user's elisp libraries
+(eval-and-compile
+ ;; The below were disabled when GNU Emacs 22 was released;
+ ;; perhaps some still need to be there to support Emacs 21.
+ (if (featurep 'xemacs)
+ (if (fboundp 'regexp-opt)
+ ;; regexp-opt is defined, does it take 3 or 2 arguments?
+ (if (fboundp 'function-max-args)
+ (let ((args (function-max-args `regexp-opt)))
+ (cond
+ ((eq args 3) ; It takes 3
+ (condition-case nil ; Hide this defun from emacses
+ ; with just a two input regexp
+ (defun verilog-regexp-opt (a b)
+ "Deal with differing number of required arguments for `regexp-opt'.
+ Call `regexp-opt' on A and B."
+ (regexp-opt a b t))
+ (error nil))
+ )
+ ((eq args 2) ; It takes 2
+ (defun verilog-regexp-opt (a b)
+ "Call `regexp-opt' on A and B."
+ (regexp-opt a b))
+ )
+ (t nil)))
+ ;; We can't tell; assume it takes 2
+ (defun verilog-regexp-opt (a b)
+ "Call `regexp-opt' on A and B."
+ (regexp-opt a b))
+ )
+ ;; There is no regexp-opt, provide our own
+ (defun verilog-regexp-opt (strings &optional paren _shy)
+ (let ((open (if paren "\\(" "")) (close (if paren "\\)" "")))
+ (concat open (mapconcat 'regexp-quote strings "\\|") close)))
+ )
+ ;; Emacs.
+ (defalias 'verilog-regexp-opt 'regexp-opt)))
+
+;; emacs >=22 has looking-back, but older emacs and xemacs don't.
+;; This function is lifted directly from emacs's subr.el
+;; so that it can be used by xemacs.
+;; The idea for this was borrowed from org-mode via this link:
+;; https://lists.gnu.org/archive/html/emacs-orgmode/2009-12/msg00032.html
+(eval-and-compile
+ (cond
+ ((fboundp 'looking-back)
+ (defalias 'verilog-looking-back 'looking-back))
+ (t
+ (defun verilog-looking-back (regexp limit &optional greedy)
+ "Return non-nil if text before point matches regular expression REGEXP.
+Like `looking-at' except matches before point, and is slower.
+LIMIT if non-nil speeds up the search by specifying a minimum
+starting position, to avoid checking matches that would start
+before LIMIT.
+
+If GREEDY is non-nil, extend the match backwards as far as
+possible, stopping when a single additional previous character
+cannot be part of a match for REGEXP. When the match is
+extended, its starting position is allowed to occur before
+LIMIT.
+
+As a general recommendation, try to avoid using `looking-back'
+wherever possible, since it is slow."
+ (let ((start (point))
+ (pos
+ (save-excursion
+ (and (re-search-backward (concat "\\(?:" regexp "\\)\\=") limit t)
+ (point)))))
+ (if (and greedy pos)
+ (save-restriction
+ (narrow-to-region (point-min) start)
+ (while (and (> pos (point-min))
+ (save-excursion
+ (goto-char pos)
+ (backward-char 1)
+ (looking-at (concat "\\(?:" regexp "\\)\\'"))))
+ (setq pos (1- pos)))
+ (save-excursion
+ (goto-char pos)
+ (looking-at (concat "\\(?:" regexp "\\)\\'")))))
+ (not (null pos)))))))
+
+(eval-and-compile
+ (cond
+ ((fboundp 'restore-buffer-modified-p)
+ ;; Faster, as does not update mode line when nothing changes
+ (defalias 'verilog-restore-buffer-modified-p 'restore-buffer-modified-p))
+ (t
+ (defalias 'verilog-restore-buffer-modified-p 'set-buffer-modified-p))))
+
+(eval-and-compile
+ ;; Both xemacs and emacs
+ (condition-case nil
+ (require 'diff) ; diff-command and diff-switches
+ (error nil))
+ (condition-case nil
+ (require 'compile) ; compilation-error-regexp-alist-alist
+ (error nil))
+ (condition-case nil
+ (unless (fboundp 'buffer-chars-modified-tick) ; Emacs 22 added
+ (defmacro buffer-chars-modified-tick () (buffer-modified-tick)))
+ (error nil))
+ ;; Added in Emacs 24.1
+ (condition-case nil
+ (unless (fboundp 'prog-mode)
+ (define-derived-mode prog-mode fundamental-mode "Prog"))
+ (error nil))
+ ;; Added in Emacs 25.1
+ (condition-case nil
+ (unless (fboundp 'forward-word-strictly)
+ (defalias 'forward-word-strictly 'forward-word))
+ (error nil)))
+
+(eval-when-compile
+ (defun verilog-regexp-words (a)
+ "Call `regexp-opt' with word delimiters for the words A."
+ (concat "\\<" (verilog-regexp-opt a t) "\\>")))
+(defun verilog-regexp-words (a)
+ "Call `regexp-opt' with word delimiters for the words A."
+ ;; The FAQ references this function, so user LISP sometimes calls it
+ (concat "\\<" (verilog-regexp-opt a t) "\\>"))
+
+(defun verilog-easy-menu-filter (menu)
+ "Filter `easy-menu-define' MENU to support new features."
+ (cond ((not (featurep 'xemacs))
+ menu) ; GNU Emacs - passthru
+ ;; XEmacs doesn't support :help. Strip it.
+ ;; Recursively filter the a submenu
+ ((listp menu)
+ (mapcar 'verilog-easy-menu-filter menu))
+ ;; Look for [:help "blah"] and remove
+ ((vectorp menu)
+ (let ((i 0) (out []))
+ (while (< i (length menu))
+ (if (equal `:help (aref menu i))
+ (setq i (+ 2 i))
+ (setq out (vconcat out (vector (aref menu i)))
+ i (1+ i))))
+ out))
+ (t menu))) ; Default - ok
+;;(verilog-easy-menu-filter
+;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
+;; "----" ["MB" nil :help "Help MB"]))
+
+(defun verilog-define-abbrev (table name expansion &optional hook)
+ "Filter `define-abbrev' TABLE NAME EXPANSION and call HOOK.
+Provides SYSTEM-FLAG in newer Emacs."
+ (condition-case nil
+ (define-abbrev table name expansion hook 0 t)
+ (error
+ (define-abbrev table name expansion hook))))
+
+(defun verilog-customize ()
+ "Customize variables and other settings used by Verilog-Mode."
+ (interactive)
+ (customize-group 'verilog-mode))
+
+(defun verilog-font-customize ()
+ "Customize fonts used by Verilog-Mode."
+ (interactive)
+ (if (fboundp 'customize-apropos)
+ (customize-apropos "font-lock-*" 'faces)))
+
+(defun verilog-booleanp (value)
+ "Return t if VALUE is boolean.
+This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs.
+This function may be removed when Emacs 21 is no longer supported."
+ (or (equal value t) (equal value nil)))
+
+(defun verilog-insert-last-command-event ()
+ "Insert the `last-command-event'."
+ (insert (if (featurep 'xemacs)
+ ;; XEmacs 21.5 doesn't like last-command-event
+ last-command-char
+ ;; And GNU Emacs 22 has obsoleted last-command-char
+ last-command-event)))
+
+(defvar verilog-no-change-functions nil
+ "True if `after-change-functions' is disabled.
+Use of `syntax-ppss' may break, as ppss's cache may get corrupted.")
+
+(defvar verilog-in-hooks nil
+ "True when within a `verilog-run-hooks' block.")
+
+(defmacro verilog-run-hooks (&rest hooks)
+ "Run each hook in HOOKS using `run-hooks'.
+Set `verilog-in-hooks' during this time, to assist AUTO caches."
+ `(let ((verilog-in-hooks t))
+ (run-hooks ,@hooks)))
+
+(defun verilog-syntax-ppss (&optional pos)
+ (when verilog-no-change-functions
+ (if verilog-in-hooks
+ (verilog-scan-cache-flush)
+ ;; else don't let the AUTO code itself get away with flushing the cache,
+ ;; as that'll make things very slow
+ (backtrace)
+ (error "%s: Internal problem; use of syntax-ppss when cache may be corrupt"
+ (verilog-point-text))))
+ (if (fboundp 'syntax-ppss)
+ (syntax-ppss pos)
+ (parse-partial-sexp (point-min) (or pos (point)))))
+
+(defgroup verilog-mode nil
+ "Major mode for Verilog source code."
+ :version "22.2"
+ :group 'languages)
+
+;; (defgroup verilog-mode-fonts nil
+;; "Facilitates easy customization fonts used in Verilog source text"
+;; :link '(customize-apropos "font-lock-*" 'faces)
+;; :group 'verilog-mode)
+
+(defgroup verilog-mode-indent nil
+ "Customize indentation and highlighting of Verilog source text."
+ :group 'verilog-mode)
+
+(defgroup verilog-mode-actions nil
+ "Customize actions on Verilog source text."
+ :group 'verilog-mode)
+
+(defgroup verilog-mode-auto nil
+ "Customize AUTO actions when expanding Verilog source text."
+ :group 'verilog-mode)
+
+(defvar verilog-debug nil
+ "Non-nil means enable debug messages for `verilog-mode' internals.")
+
+(defvar verilog-warn-fatal nil
+ "Non-nil means `verilog-warn-error' warnings are fatal `error's.")
+
+(defcustom verilog-linter
+ "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
+ "Unix program and arguments to call to run a lint checker on Verilog source.
+Depending on the `verilog-set-compile-command', this may be invoked when
+you type \\[compile]. When the compile completes, \\[next-error] will take
+you to the next lint error."
+ :type 'string
+ :group 'verilog-mode-actions)
+;; We don't mark it safe, as it's used as a shell command
+
+(defcustom verilog-coverage
+ "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
+ "Program and arguments to use to annotate for coverage Verilog source.
+Depending on the `verilog-set-compile-command', this may be invoked when
+you type \\[compile]. When the compile completes, \\[next-error] will take
+you to the next lint error."
+ :type 'string
+ :group 'verilog-mode-actions)
+;; We don't mark it safe, as it's used as a shell command
+
+(defcustom verilog-simulator
+ "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
+ "Program and arguments to use to interpret Verilog source.
+Depending on the `verilog-set-compile-command', this may be invoked when
+you type \\[compile]. When the compile completes, \\[next-error] will take
+you to the next lint error."
+ :type 'string
+ :group 'verilog-mode-actions)
+;; We don't mark it safe, as it's used as a shell command
+
+(defcustom verilog-compiler
+ "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
+ "Program and arguments to use to compile Verilog source.
+Depending on the `verilog-set-compile-command', this may be invoked when
+you type \\[compile]. When the compile completes, \\[next-error] will take
+you to the next lint error."
+ :type 'string
+ :group 'verilog-mode-actions)
+;; We don't mark it safe, as it's used as a shell command
+
+(defcustom verilog-preprocessor
+ ;; Very few tools give preprocessed output, so we'll default to Verilog-Perl
+ "vppreproc __FLAGS__ __FILE__"
+ "Program and arguments to use to preprocess Verilog source.
+This is invoked with `verilog-preprocess', and depending on the
+`verilog-set-compile-command', may also be invoked when you type
+\\[compile]. When the compile completes, \\[next-error] will
+take you to the next lint error."
+ :type 'string
+ :group 'verilog-mode-actions)
+;; We don't mark it safe, as it's used as a shell command
+
+(defvar verilog-preprocess-history nil
+ "History for `verilog-preprocess'.")
+
+(defvar verilog-tool 'verilog-linter
+ "Which tool to use for building compiler-command.
+Either nil, `verilog-linter', `verilog-compiler',
+`verilog-coverage', `verilog-preprocessor', or `verilog-simulator'.
+Alternatively use the \"Choose Compilation Action\" menu. See
+`verilog-set-compile-command' for more information.")
+
+(defcustom verilog-highlight-translate-off nil
+ "Non-nil means background-highlight code excluded from translation.
+That is, all code between \"// synopsys translate_off\" and
+\"// synopsys translate_on\" is highlighted using a different background color
+\(face `verilog-font-lock-translate-off-face').
+
+Note: This will slow down on-the-fly fontification (and thus editing).
+
+Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
+entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
+ :type 'boolean
+ :group 'verilog-mode-indent)
+;; Note we don't use :safe, as that would break on Emacsen before 22.0.
+(put 'verilog-highlight-translate-off 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-lineup 'declarations
+ "Type of statements to lineup across multiple lines.
+If `all' is selected, then all line ups described below are done.
+
+If `declarations', then just declarations are lined up with any
+preceding declarations, taking into account widths and the like,
+so or example the code:
+ reg [31:0] a;
+ reg b;
+would become
+ reg [31:0] a;
+ reg b;
+
+If `assignment', then assignments are lined up with any preceding
+assignments, so for example the code
+ a_long_variable <= b + c;
+ d = e + f;
+would become
+ a_long_variable <= b + c;
+ d = e + f;
+
+In order to speed up editing, large blocks of statements are lined up
+only when a \\[verilog-pretty-expr] is typed; and large blocks of declarations
+are lineup only when \\[verilog-pretty-declarations] is typed."
+
+ :type '(radio (const :tag "Line up Assignments and Declarations" all)
+ (const :tag "Line up Assignment statements" assignments )
+ (const :tag "Line up Declarations" declarations)
+ (function :tag "Other"))
+ :group 'verilog-mode-indent )
+(put 'verilog-auto-lineup 'safe-local-variable
+ '(lambda (x) (memq x '(nil all assignments declarations))))
+
+(defcustom verilog-indent-level 3
+ "Indentation of Verilog statements with respect to containing block."
+ :group 'verilog-mode-indent
+ :type 'integer)
+(put 'verilog-indent-level 'safe-local-variable 'integerp)
+
+(defcustom verilog-indent-level-module 3
+ "Indentation of Module level Verilog statements (eg always, initial).
+Set to 0 to get initial and always statements lined up on the left side of
+your screen."
+ :group 'verilog-mode-indent
+ :type 'integer)
+(put 'verilog-indent-level-module 'safe-local-variable 'integerp)
+
+(defcustom verilog-indent-level-declaration 3
+ "Indentation of declarations with respect to containing block.
+Set to 0 to get them list right under containing block."
+ :group 'verilog-mode-indent
+ :type 'integer)
+(put 'verilog-indent-level-declaration 'safe-local-variable 'integerp)
+
+(defcustom verilog-indent-declaration-macros nil
+ "How to treat macro expansions in a declaration.
+If nil, indent as:
+ input [31:0] a;
+ input \\=`CP;
+ output c;
+If non nil, treat as:
+ input [31:0] a;
+ input \\=`CP ;
+ output c;"
+ :group 'verilog-mode-indent
+ :type 'boolean)
+(put 'verilog-indent-declaration-macros 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-indent-lists t
+ "How to treat indenting items in a list.
+If t (the default), indent as:
+ always @( posedge a or
+ reset ) begin
+
+If nil, treat as:
+ always @( posedge a or
+ reset ) begin"
+ :group 'verilog-mode-indent
+ :type 'boolean)
+(put 'verilog-indent-lists 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-indent-level-behavioral 3
+ "Absolute indentation of first begin in a task or function block.
+Set to 0 to get such code to start at the left side of the screen."
+ :group 'verilog-mode-indent
+ :type 'integer)
+(put 'verilog-indent-level-behavioral 'safe-local-variable 'integerp)
+
+(defcustom verilog-indent-level-directive 1
+ "Indentation to add to each level of \\=`ifdef declarations.
+Set to 0 to have all directives start at the left side of the screen."
+ :group 'verilog-mode-indent
+ :type 'integer)
+(put 'verilog-indent-level-directive 'safe-local-variable 'integerp)
+
+(defcustom verilog-cexp-indent 2
+ "Indentation of Verilog statements split across lines."
+ :group 'verilog-mode-indent
+ :type 'integer)
+(put 'verilog-cexp-indent 'safe-local-variable 'integerp)
+
+(defcustom verilog-case-indent 2
+ "Indentation for case statements."
+ :group 'verilog-mode-indent
+ :type 'integer)
+(put 'verilog-case-indent 'safe-local-variable 'integerp)
+
+(defcustom verilog-auto-newline t
+ "Non-nil means automatically newline after semicolons."
+ :group 'verilog-mode-indent
+ :type 'boolean)
+(put 'verilog-auto-newline 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-indent-on-newline t
+ "Non-nil means automatically indent line after newline."
+ :group 'verilog-mode-indent
+ :type 'boolean)
+(put 'verilog-auto-indent-on-newline 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-tab-always-indent t
+ "Non-nil means TAB should always re-indent the current line.
+A nil value means TAB will only reindent when at the beginning of the line."
+ :group 'verilog-mode-indent
+ :type 'boolean)
+(put 'verilog-tab-always-indent 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-tab-to-comment nil
+ "Non-nil means TAB moves to the right hand column in preparation for a comment."
+ :group 'verilog-mode-actions
+ :type 'boolean)
+(put 'verilog-tab-to-comment 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-indent-begin-after-if t
+ "Non-nil means indent begin statements following if, else, while, etc.
+Otherwise, line them up."
+ :group 'verilog-mode-indent
+ :type 'boolean)
+(put 'verilog-indent-begin-after-if 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-align-ifelse nil
+ "Non-nil means align `else' under matching `if'.
+Otherwise else is lined up with first character on line holding matching if."
+ :group 'verilog-mode-indent
+ :type 'boolean)
+(put 'verilog-align-ifelse 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-minimum-comment-distance 10
+ "Minimum distance (in lines) between begin and end required before a comment.
+Setting this variable to zero results in every end acquiring a comment; the
+default avoids too many redundant comments in tight quarters."
+ :group 'verilog-mode-indent
+ :type 'integer)
+(put 'verilog-minimum-comment-distance 'safe-local-variable 'integerp)
+
+(defcustom verilog-highlight-p1800-keywords nil
+ "Non-nil means highlight words newly reserved by IEEE-1800.
+These will appear in `verilog-font-lock-p1800-face' in order to gently
+suggest changing where these words are used as variables to something else.
+A nil value means highlight these words as appropriate for the SystemVerilog
+IEEE-1800 standard. Note that changing this will require restarting Emacs
+to see the effect as font color choices are cached by Emacs."
+ :group 'verilog-mode-indent
+ :type 'boolean)
+(put 'verilog-highlight-p1800-keywords 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-highlight-grouping-keywords nil
+ "Non-nil means highlight grouping keywords more dramatically.
+If false, these words are in the `font-lock-type-face'; if True
+then they are in `verilog-font-lock-grouping-keywords-face'.
+Some find that special highlighting on these grouping constructs
+allow the structure of the code to be understood at a glance."
+ :group 'verilog-mode-indent
+ :type 'boolean)
+(put 'verilog-highlight-grouping-keywords 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-highlight-modules nil
+ "Non-nil means highlight module statements for `verilog-load-file-at-point'.
+When true, mousing over module names will allow jumping to the
+module definition. If false, this is not supported. Setting
+this is experimental, and may lead to bad performance."
+ :group 'verilog-mode-indent
+ :type 'boolean)
+(put 'verilog-highlight-modules 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-highlight-includes t
+ "Non-nil means highlight module statements for `verilog-load-file-at-point'.
+When true, mousing over include file names will allow jumping to the
+file referenced. If false, this is not supported."
+ :group 'verilog-mode-indent
+ :type 'boolean)
+(put 'verilog-highlight-includes 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-declare-nettype nil
+ "Non-nil specifies the data type to use with `verilog-auto-input' etc.
+Set this to \"wire\" if the Verilog code uses \"\\=`default_nettype
+none\". Note using \\=`default_nettype none isn't recommended practice; this
+mode is experimental."
+ :version "24.1" ; rev670
+ :group 'verilog-mode-actions
+ :type 'boolean)
+(put 'verilog-auto-declare-nettype 'safe-local-variable `stringp)
+
+(defcustom verilog-auto-wire-comment t
+ "Non-nil indicates to insert to/from comments with `verilog-auto-wire' etc."
+ :version "25.1"
+ :group 'verilog-mode-actions
+ :type 'boolean)
+(put 'verilog-auto-wire-comment 'safe-local-variable `verilog-booleanp)
+
+(defcustom verilog-auto-wire-type nil
+ "Non-nil specifies the data type to use with `verilog-auto-wire' etc.
+Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'."
+ :version "24.1" ; rev673
+ :group 'verilog-mode-actions
+ :type 'boolean)
+(put 'verilog-auto-wire-type 'safe-local-variable `stringp)
+
+(defcustom verilog-auto-endcomments t
+ "Non-nil means insert a comment /* ... */ after `end's.
+The name of the function or case will be set between the braces."
+ :group 'verilog-mode-actions
+ :type 'boolean)
+(put 'verilog-auto-endcomments 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-delete-trailing-whitespace nil
+ "Non-nil means to `delete-trailing-whitespace' in `verilog-auto'."
+ :version "24.1" ; rev703
+ :group 'verilog-mode-actions
+ :type 'boolean)
+(put 'verilog-auto-delete-trailing-whitespace 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-ignore-concat nil
+ "Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc.
+This will exclude signals referenced as pin connections in {...}
+from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
+for backward compatibility only and not set in new designs; it
+may be removed in future versions."
+ :group 'verilog-mode-actions
+ :type 'boolean)
+(put 'verilog-auto-ignore-concat 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-read-includes nil
+ "Non-nil means to automatically read includes before AUTOs.
+This will do a `verilog-read-defines' and `verilog-read-includes' before
+each AUTO expansion. This makes it easier to embed defines and includes,
+but can result in very slow reading times if there are many or large
+include files."
+ :group 'verilog-mode-actions
+ :type 'boolean)
+(put 'verilog-auto-read-includes 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-save-policy nil
+ "Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
+A value of `force' will always do a \\[verilog-auto] automatically if
+needed on every save. A value of `detect' will do \\[verilog-auto]
+automatically when it thinks necessary. A value of `ask' will query the
+user when it thinks updating is needed.
+
+You should not rely on the `ask' or `detect' policies, they are safeguards
+only. They do not detect when AUTOINSTs need to be updated because a
+sub-module's port list has changed."
+ :group 'verilog-mode-actions
+ :type '(choice (const nil) (const ask) (const detect) (const force)))
+
+(defcustom verilog-auto-star-expand t
+ "Non-nil means to expand SystemVerilog .* instance ports.
+They will be expanded in the same way as if there was an AUTOINST in the
+instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
+ :group 'verilog-mode-actions
+ :type 'boolean)
+(put 'verilog-auto-star-expand 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-star-save nil
+ "Non-nil means save to disk SystemVerilog .* instance expansions.
+A nil value indicates direct connections will be removed before saving.
+Only meaningful to those created due to `verilog-auto-star-expand' being set.
+
+Instead of setting this, you may want to use /*AUTOINST*/, which will
+always be saved."
+ :group 'verilog-mode-actions
+ :type 'boolean)
+(put 'verilog-auto-star-save 'safe-local-variable 'verilog-booleanp)
+
+(defvar verilog-auto-update-tick nil
+ "Modification tick at which autos were last performed.")
+
+(defvar verilog-auto-last-file-locals nil
+ "Text from file-local-variables during last evaluation.")
+
+(defvar verilog-diff-function 'verilog-diff-report
+ "Function to run when `verilog-diff-auto' detects differences.
+Function takes three arguments, the original buffer, the
+difference buffer, and the point in original buffer with the
+first difference.")
+
+(defvar verilog-diff-ignore-regexp nil
+ "Non-nil specifies regexp which `verilog-diff-auto' will ignore.
+This is typically nil.")
+
+;;; Compile support:
+;;
+
+(require 'compile)
+
+(defvar verilog-error-regexp-added nil)
+
+(defvar verilog-error-regexp-emacs-alist
+ '(
+ (verilog-xl-1
+ "\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
+ (verilog-xl-2
+ "([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 3)
+ (verilog-IES
+ ".*\\*[WE],[0-9A-Z]+\\(\\[[0-9A-Z_,]+\\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)" 2 3)
+ (verilog-surefire-1
+ "[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
+ (verilog-surefire-2
+ "\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\),\\s-+\\(line \\)?\\([0-9]+\\):" 2 4 )
+ (verilog-verbose
+ "\
+\\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
+:\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
+ (verilog-xsim
+ "\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
+ (verilog-vcs-1
+ "\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
+ (verilog-vcs-2
+ "Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
+ (verilog-vcs-3
+ "\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
+ (verilog-vcs-4
+ "syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
+ (verilog-verilator
+ "%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
+ (verilog-leda
+ "^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 2)
+ )
+ "List of regexps for Verilog compilers.
+See `compilation-error-regexp-alist' for the formatting. For Emacs 22+.")
+
+(defvar verilog-error-regexp-xemacs-alist
+ ;; Emacs form is '((v-tool "re" 1 2) ...)
+ ;; XEmacs form is '(verilog ("re" 1 2) ...)
+ ;; So we can just map from Emacs to XEmacs
+ (cons 'verilog (mapcar 'cdr verilog-error-regexp-emacs-alist))
+ "List of regexps for Verilog compilers.
+See `compilation-error-regexp-alist-alist' for the formatting. For XEmacs.")
+
+(defvar verilog-error-font-lock-keywords
+ '(
+ ;; verilog-xl-1
+ ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
+ ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
+ ;; verilog-xl-2
+ ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 bold t)
+ ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 3 bold t)
+ ;; verilog-IES (nc-verilog)
+ (".*\\*[WE],[0-9A-Z]+\\(\\[[0-9A-Z_,]+\\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t)
+ (".*\\*[WE],[0-9A-Z]+\\(\\[[0-9A-Z_,]+\\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 3 bold t)
+ ;; verilog-surefire-1
+ ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t)
+ ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t)
+ ;; verilog-surefire-2
+ ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t)
+ ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t)
+ ;; verilog-verbose
+ ("\
+\\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
+:\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
+ ("\
+\\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
+:\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
+ ;; verilog-vcs-1
+ ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t)
+ ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t)
+ ;; verilog-vcs-2
+ ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
+ ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
+ ;; verilog-vcs-3
+ ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
+ ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t)
+ ;; verilog-vcs-4
+ ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t)
+ ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
+ ;; verilog-verilator
+ (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t)
+ (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t)
+ ;; verilog-leda
+ ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 bold t)
+ ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 2 bold t)
+ )
+ "Keywords to also highlight in Verilog *compilation* buffers.
+Only used in XEmacs; GNU Emacs uses `verilog-error-regexp-emacs-alist'.")
+
+(defcustom verilog-library-flags '("")
+ "List of standard Verilog arguments to use for /*AUTOINST*/.
+These arguments are used to find files for `verilog-auto', and match
+the flags accepted by a standard Verilog-XL simulator.
+
+ -f filename Reads more `verilog-library-flags' from the filename.
+ +incdir+dir Adds the directory to `verilog-library-directories'.
+ -Idir Adds the directory to `verilog-library-directories'.
+ -y dir Adds the directory to `verilog-library-directories'.
+ +libext+.v Adds the extensions to `verilog-library-extensions'.
+ -v filename Adds the filename to `verilog-library-files'.
+
+ filename Adds the filename to `verilog-library-files'.
+ This is not recommended, -v is a better choice.
+
+You might want these defined in each file; put at the *END* of your file
+something like:
+
+ // Local Variables:
+ // verilog-library-flags:(\"-y dir -y otherdir\")
+ // End:
+
+Verilog-mode attempts to detect changes to this local variable, but they
+are only insured to be correct when the file is first visited. Thus if you
+have problems, use \\[find-alternate-file] RET to have these take effect.
+
+See also the variables mentioned above."
+ :group 'verilog-mode-auto
+ :type '(repeat string))
+(put 'verilog-library-flags 'safe-local-variable 'listp)
+
+(defcustom verilog-library-directories '(".")
+ "List of directories when looking for files for /*AUTOINST*/.
+The directory may be relative to the current file, or absolute.
+Environment variables are also expanded in the directory names.
+Having at least the current directory is a good idea.
+
+You might want these defined in each file; put at the *END* of your file
+something like:
+
+ // Local Variables:
+ // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
+ // End:
+
+Verilog-mode attempts to detect changes to this local variable, but they
+are only insured to be correct when the file is first visited. Thus if you
+have problems, use \\[find-alternate-file] RET to have these take effect.
+
+See also `verilog-library-flags', `verilog-library-files'
+and `verilog-library-extensions'."
+ :group 'verilog-mode-auto
+ :type '(repeat file))
+(put 'verilog-library-directories 'safe-local-variable 'listp)
+
+(defcustom verilog-library-files '()
+ "List of files to search for modules.
+AUTOINST will use this when it needs to resolve a module name.
+This is a complete path, usually to a technology file with many standard
+cells defined in it.
+
+You might want these defined in each file; put at the *END* of your file
+something like:
+
+ // Local Variables:
+ // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
+ // End:
+
+Verilog-mode attempts to detect changes to this local variable, but they
+are only insured to be correct when the file is first visited. Thus if you
+have problems, use \\[find-alternate-file] RET to have these take effect.
+
+See also `verilog-library-flags', `verilog-library-directories'."
+ :group 'verilog-mode-auto
+ :type '(repeat directory))
+(put 'verilog-library-files 'safe-local-variable 'listp)
+
+(defcustom verilog-library-extensions '(".v" ".sv")
+ "List of extensions to use when looking for files for /*AUTOINST*/.
+See also `verilog-library-flags', `verilog-library-directories'."
+ :type '(repeat string)
+ :group 'verilog-mode-auto)
+(put 'verilog-library-extensions 'safe-local-variable 'listp)
+
+(defcustom verilog-active-low-regexp nil
+ "If true, treat signals matching this regexp as active low.
+This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
+you will probably also need `verilog-auto-reset-widths' set."
+ :group 'verilog-mode-auto
+ :type '(choice (const nil) regexp))
+(put 'verilog-active-low-regexp 'safe-local-variable 'stringp)
+
+(defcustom verilog-auto-sense-include-inputs nil
+ "Non-nil means AUTOSENSE should include all inputs.
+If nil, only inputs that are NOT output signals in the same block are
+included."
+ :group 'verilog-mode-auto
+ :type 'boolean)
+(put 'verilog-auto-sense-include-inputs 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-sense-defines-constant nil
+ "Non-nil means AUTOSENSE should assume all defines represent constants.
+When true, the defines will not be included in sensitivity lists. To
+maintain compatibility with other sites, this should be set at the bottom
+of each Verilog file that requires it, rather than being set globally."
+ :group 'verilog-mode-auto
+ :type 'boolean)
+(put 'verilog-auto-sense-defines-constant 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-reset-blocking-in-non t
+ "Non-nil means AUTORESET will reset blocking statements.
+When true, AUTORESET will reset in blocking statements those
+signals which were assigned with blocking assignments (=) even in
+a block with non-blocking assignments (<=).
+
+If nil, all blocking assigned signals are ignored when any
+non-blocking assignment is in the AUTORESET block. This allows
+blocking assignments to be used for temporary values and not have
+those temporaries reset. See example in `verilog-auto-reset'."
+ :version "24.1" ; rev718
+ :type 'boolean
+ :group 'verilog-mode-auto)
+(put 'verilog-auto-reset-blocking-in-non 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-reset-widths t
+ "True means AUTORESET should determine the width of signals.
+This is then used to set the width of the zero (32'h0 for example). This
+is required by some lint tools that aren't smart enough to ignore widths of
+the constant zero. This may result in ugly code when parameters determine
+the MSB or LSB of a signal inside an AUTORESET.
+
+If nil, AUTORESET uses \"0\" as the constant.
+
+If `unbased', AUTORESET used the unbased unsized literal \"\\='0\"
+as the constant. This setting is strongly recommended for
+SystemVerilog designs."
+ :type 'boolean
+ :group 'verilog-mode-auto)
+(put 'verilog-auto-reset-widths 'safe-local-variable
+ '(lambda (x) (memq x '(nil t unbased))))
+
+(defcustom verilog-assignment-delay ""
+ "Text used for delays in delayed assignments. Add a trailing space if set."
+ :group 'verilog-mode-auto
+ :type 'string)
+(put 'verilog-assignment-delay 'safe-local-variable 'stringp)
+
+(defcustom verilog-auto-arg-format 'packed
+ "Formatting to use for AUTOARG signal names.
+If `packed', then as many inputs and outputs that fit within
+`fill-column' will be put onto one line.
+
+If `single', then a single input or output will be put onto each
+line."
+ :version "25.1"
+ :type '(radio (const :tag "Line up Assignments and Declarations" packed)
+ (const :tag "Line up Assignment statements" single))
+ :group 'verilog-mode-auto)
+(put 'verilog-auto-arg-format 'safe-local-variable
+ '(lambda (x) (memq x '(packed single))))
+
+(defcustom verilog-auto-arg-sort nil
+ "Non-nil means AUTOARG signal names will be sorted, not in declaration order.
+Declaration order is advantageous with order based instantiations
+and is the default for backward compatibility. Sorted order
+reduces changes when declarations are moved around in a file, and
+it's bad practice to rely on order based instantiations anyhow.
+
+See also `verilog-auto-inst-sort'."
+ :group 'verilog-mode-auto
+ :type 'boolean)
+(put 'verilog-auto-arg-sort 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-inst-dot-name nil
+ "Non-nil means when creating ports with AUTOINST, use .name syntax.
+This will use \".port\" instead of \".port(port)\" when possible.
+This is only legal in SystemVerilog files, and will confuse older
+simulators. Setting `verilog-auto-inst-vector' to nil may also
+be desirable to increase how often .name will be used."
+ :group 'verilog-mode-auto
+ :type 'boolean)
+(put 'verilog-auto-inst-dot-name 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-inst-param-value nil
+ "Non-nil means AUTOINST will replace parameters with the parameter value.
+If nil, leave parameters as symbolic names.
+
+Parameters must be in Verilog 2001 format #(...), and if a parameter is not
+listed as such there (as when the default value is acceptable), it will not
+be replaced, and will remain symbolic.
+
+For example, imagine a submodule uses parameters to declare the size of its
+inputs. This is then used by an upper module:
+
+ module InstModule (o,i);
+ parameter WIDTH;
+ input [WIDTH-1:0] i;
+ parameter type OUT_t;
+ output OUT_t o;
+ endmodule
+
+ module ExampInst;
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs
+ output OUT_t o;
+ // End of automatics
+
+ InstModule
+ #(.WIDTH(10),
+ ,.OUT_t(upper_t))
+ instName
+ (/*AUTOINST*/
+ .i (i[WIDTH-1:0]),
+ .o (o));
+
+Note even though WIDTH=10, the AUTOINST has left the parameter as
+a symbolic name. Likewise the OUT_t is preserved as the name
+from the instantiated module.
+
+If `verilog-auto-inst-param-value' is set, this will
+instead expand to:
+
+ module ExampInst;
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs
+ output upper_t o;
+ // End of automatics
+
+ InstModule
+ #(.WIDTH(10),
+ ,.OUT_t(upper_t))
+ instName
+ (/*AUTOINST*/
+ .i (i[9:0]),
+ .o (o));
+
+Note that the instantiation now has \"i[9:0]\" as the WIDTH
+was expanded. Likewise the data type of \"o\" in the AUTOOUTPUT
+is now upper_t, from the OUT_t parameter override.
+This second expansion of parameter types can be overridden with
+`verilog-auto-inst-param-value-type'."
+ :group 'verilog-mode-auto
+ :type 'boolean)
+(put 'verilog-auto-inst-param-value 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-inst-param-value-type t
+ "Non-nil means expand parameter type in instantiations.
+If nil, leave parameter types as symbolic names.
+
+See `verilog-auto-inst-param-value'."
+ :version "25.1"
+ :group 'verilog-mode-auto
+ :type 'boolean)
+(put 'verilog-auto-inst-param-value-type 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-inst-sort nil
+ "Non-nil means AUTOINST signals will be sorted, not in declaration order.
+Also affects AUTOINSTPARAM. Declaration order is the default for
+backward compatibility, and as some teams prefer signals that are
+declared together to remain together. Sorted order reduces
+changes when declarations are moved around in a file.
+
+See also `verilog-auto-arg-sort'."
+ :version "24.1" ; rev688
+ :group 'verilog-mode-auto
+ :type 'boolean)
+(put 'verilog-auto-inst-sort 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-inst-vector t
+ "Non-nil means when creating default ports with AUTOINST, use bus subscripts.
+If nil, skip the subscript when it matches the entire bus as declared in
+the module (AUTOWIRE signals always are subscripted, you must manually
+declare the wire to have the subscripts removed.) Setting this to nil may
+speed up some simulators, but is less general and harder to read, so avoid."
+ :group 'verilog-mode-auto
+ :type 'boolean)
+(put 'verilog-auto-inst-vector 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-inst-template-numbers nil
+ "If true, when creating templated ports with AUTOINST, add a comment.
+
+If t, the comment will add the line number of the template that
+was used for that port declaration. This setting is suggested
+only for debugging use, as regular use may cause a large numbers
+of merge conflicts.
+
+If `lhs', the comment will show the left hand side of the
+AUTO_TEMPLATE rule that is matched. This is less precise than
+numbering (t) when multiple rules have the same pin name, but
+won't merge conflict."
+ :group 'verilog-mode-auto
+ :type '(choice (const nil) (const t) (const lhs)))
+(put 'verilog-auto-inst-template-numbers 'safe-local-variable
+ '(lambda (x) (memq x '(nil t lhs))))
+
+(defcustom verilog-auto-inst-column 40
+ "Indent-to column number for net name part of AUTOINST created pin."
+ :group 'verilog-mode-indent
+ :type 'integer)
+(put 'verilog-auto-inst-column 'safe-local-variable 'integerp)
+
+(defcustom verilog-auto-inst-interfaced-ports nil
+ "Non-nil means include interfaced ports in AUTOINST expansions."
+ :version "24.3" ; rev773, default change rev815
+ :group 'verilog-mode-auto
+ :type 'boolean)
+(put 'verilog-auto-inst-interfaced-ports 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-input-ignore-regexp nil
+ "If non-nil, when creating AUTOINPUT, ignore signals matching this regexp.
+See the \\[verilog-faq] for examples on using this."
+ :group 'verilog-mode-auto
+ :type '(choice (const nil) regexp))
+(put 'verilog-auto-input-ignore-regexp 'safe-local-variable 'stringp)
+
+(defcustom verilog-auto-inout-ignore-regexp nil
+ "If non-nil, when creating AUTOINOUT, ignore signals matching this regexp.
+See the \\[verilog-faq] for examples on using this."
+ :group 'verilog-mode-auto
+ :type '(choice (const nil) regexp))
+(put 'verilog-auto-inout-ignore-regexp 'safe-local-variable 'stringp)
+
+(defcustom verilog-auto-output-ignore-regexp nil
+ "If non-nil, when creating AUTOOUTPUT, ignore signals matching this regexp.
+See the \\[verilog-faq] for examples on using this."
+ :group 'verilog-mode-auto
+ :type '(choice (const nil) regexp))
+(put 'verilog-auto-output-ignore-regexp 'safe-local-variable 'stringp)
+
+(defcustom verilog-auto-template-warn-unused nil
+ "Non-nil means report warning if an AUTO_TEMPLATE line is not used.
+This feature is not supported before Emacs 21.1 or XEmacs 21.4."
+ :version "24.3" ; rev787
+ :group 'verilog-mode-auto
+ :type 'boolean)
+(put 'verilog-auto-template-warn-unused 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-auto-tieoff-declaration "wire"
+ "Data type used for the declaration for AUTOTIEOFF.
+If \"wire\" then create a wire, if \"assign\" create an
+assignment, else the data type for variable creation."
+ :version "24.1" ; rev713
+ :group 'verilog-mode-auto
+ :type 'string)
+(put 'verilog-auto-tieoff-declaration 'safe-local-variable 'stringp)
+
+(defcustom verilog-auto-tieoff-ignore-regexp nil
+ "If non-nil, when creating AUTOTIEOFF, ignore signals matching this regexp.
+See the \\[verilog-faq] for examples on using this."
+ :group 'verilog-mode-auto
+ :type '(choice (const nil) regexp))
+(put 'verilog-auto-tieoff-ignore-regexp 'safe-local-variable 'stringp)
+
+(defcustom verilog-auto-unused-ignore-regexp nil
+ "If non-nil, when creating AUTOUNUSED, ignore signals matching this regexp.
+See the \\[verilog-faq] for examples on using this."
+ :group 'verilog-mode-auto
+ :type '(choice (const nil) regexp))
+(put 'verilog-auto-unused-ignore-regexp 'safe-local-variable 'stringp)
+
+(defcustom verilog-case-fold t
+ "Non-nil means `verilog-mode' regexps should ignore case.
+This variable is t for backward compatibility; nil is suggested."
+ :version "24.4"
+ :group 'verilog-mode
+ :type 'boolean)
+(put 'verilog-case-fold 'safe-local-variable 'verilog-booleanp)
+
+(defcustom verilog-typedef-regexp nil
+ "If non-nil, regular expression that matches Verilog-2001 typedef names.
+For example, \"_t$\" matches typedefs named with _t, as in the C language.
+See also `verilog-case-fold'."
+ :group 'verilog-mode-auto
+ :type '(choice (const nil) regexp))
+(put 'verilog-typedef-regexp 'safe-local-variable 'stringp)
+
+(defcustom verilog-mode-hook 'verilog-set-compile-command
+ "Hook run after Verilog mode is loaded."
+ :type 'hook
+ :group 'verilog-mode)
+
+(defcustom verilog-auto-hook nil
+ "Hook run after `verilog-mode' updates AUTOs."
+ :group 'verilog-mode-auto
+ :type 'hook)
+
+(defcustom verilog-before-auto-hook nil
+ "Hook run before `verilog-mode' updates AUTOs."
+ :group 'verilog-mode-auto
+ :type 'hook)
+
+(defcustom verilog-delete-auto-hook nil
+ "Hook run after `verilog-mode' deletes AUTOs."
+ :group 'verilog-mode-auto
+ :type 'hook)
+
+(defcustom verilog-before-delete-auto-hook nil
+ "Hook run before `verilog-mode' deletes AUTOs."
+ :group 'verilog-mode-auto
+ :type 'hook)
+
+(defcustom verilog-getopt-flags-hook nil
+ "Hook run after `verilog-getopt-flags' determines the Verilog option lists."
+ :group 'verilog-mode-auto
+ :type 'hook)
+
+(defcustom verilog-before-getopt-flags-hook nil
+ "Hook run before `verilog-getopt-flags' determines the Verilog option lists."
+ :group 'verilog-mode-auto
+ :type 'hook)
+
+(defcustom verilog-before-save-font-hook nil
+ "Hook run before `verilog-save-font-mods' removes highlighting."
+ :version "24.3" ; rev735
+ :group 'verilog-mode-auto
+ :type 'hook)
+
+(defcustom verilog-after-save-font-hook nil
+ "Hook run after `verilog-save-font-mods' restores highlighting."
+ :version "24.3" ; rev735
+ :group 'verilog-mode-auto
+ :type 'hook)
+
+(defvar verilog-imenu-generic-expression
+ '((nil "^\\s-*\\(?:m\\(?:odule\\|acromodule\\)\\|p\\(?:rimitive\\|rogram\\|ackage\\)\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 1)
+ ("*Variables*" "^\\s-*\\(reg\\|wire\\|logic\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3)
+ ("*Classes*" "^\\s-*\\(?:\\(?:virtual\\|interface\\)\\s-+\\)?class\\s-+\\([A-Za-z_][A-Za-z0-9_]+\\)" 1)
+ ("*Tasks*" "^\\s-*\\(?:\\(?:static\\|pure\\|virtual\\|local\\|protected\\)\\s-+\\)*task\\s-+\\(?:\\(?:static\\|automatic\\)\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_:]+\\)" 1)
+ ("*Functions*" "^\\s-*\\(?:\\(?:static\\|pure\\|virtual\\|local\\|protected\\)\\s-+\\)*function\\s-+\\(?:\\(?:static\\|automatic\\)\\s-+\\)?\\(?:\\w+\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_:]+\\)" 1)
+ ("*Interfaces*" "^\\s-*interface\\s-+\\([a-zA-Z_0-9]+\\)" 1)
+ ("*Types*" "^\\s-*typedef\\s-+.*\\s-+\\([a-zA-Z_0-9]+\\)\\s-*;" 1))
+ "Imenu expression for Verilog mode. See `imenu-generic-expression'.")
+
+;;
+;; provide a verilog-header function.
+;; Customization variables:
+;;
+(defvar verilog-date-scientific-format nil
+ "If non-nil, dates are written in scientific format (e.g. 1997/09/17).
+If nil, in European format (e.g. 17.09.1997). The brain-dead American
+format (e.g. 09/17/1997) is not supported.")
+
+(defvar verilog-company nil
+ "Default name of Company for Verilog header.
+If set will become buffer local.")
+(make-variable-buffer-local 'verilog-company)
+
+(defvar verilog-project nil
+ "Default name of Project for Verilog header.
+If set will become buffer local.")
+(make-variable-buffer-local 'verilog-project)
+
+;;; Keymap and Menu:
+;;
+
+(defvar verilog-mode-map
+ (let ((map (make-sparse-keymap)))
+ (define-key map ";" 'electric-verilog-semi)
+ (define-key map [(control 59)] 'electric-verilog-semi-with-comment)
+ (define-key map ":" 'electric-verilog-colon)
+ ;;(define-key map "=" 'electric-verilog-equal)
+ (define-key map "`" 'electric-verilog-tick)
+ (define-key map "\t" 'electric-verilog-tab)
+ (define-key map "\r" 'electric-verilog-terminate-line)
+ ;; backspace/delete key bindings
+ (define-key map [backspace] 'backward-delete-char-untabify)
+ (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
+ (define-key map [delete] 'delete-char)
+ (define-key map [(meta delete)] 'kill-word))
+ (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
+ (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
+ (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
+ (define-key map "\M-\t" 'verilog-complete-word)
+ (define-key map "\M-?" 'verilog-show-completions)
+ ;; Note \C-c and letter are reserved for users
+ (define-key map "\C-c`" 'verilog-lint-off)
+ (define-key map "\C-c*" 'verilog-delete-auto-star-implicit)
+ (define-key map "\C-c?" 'verilog-diff-auto)
+ (define-key map "\C-c\C-r" 'verilog-label-be)
+ (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
+ (define-key map "\C-c=" 'verilog-pretty-expr)
+ (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
+ (define-key map "\C-c/" 'verilog-star-comment)
+ (define-key map "\C-c\C-c" 'verilog-comment-region)
+ (define-key map "\C-c\C-u" 'verilog-uncomment-region)
+ (when (featurep 'xemacs)
+ (define-key map [(meta control h)] 'verilog-mark-defun)
+ (define-key map "\M-\C-a" 'verilog-beg-of-defun)
+ (define-key map "\M-\C-e" 'verilog-end-of-defun))
+ (define-key map "\C-c\C-d" 'verilog-goto-defun)
+ (define-key map "\C-c\C-k" 'verilog-delete-auto)
+ (define-key map "\C-c\C-a" 'verilog-auto)
+ (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
+ (define-key map "\C-c\C-p" 'verilog-preprocess)
+ (define-key map "\C-c\C-z" 'verilog-inject-auto)
+ (define-key map "\C-c\C-e" 'verilog-expand-vector)
+ (define-key map "\C-c\C-h" 'verilog-header)
+ map)
+ "Keymap used in Verilog mode.")
+
+;; menus
+(easy-menu-define
+ verilog-menu verilog-mode-map "Menu for Verilog mode"
+ (verilog-easy-menu-filter
+ '("Verilog"
+ ("Choose Compilation Action"
+ ["None"
+ (progn
+ (setq verilog-tool nil)
+ (verilog-set-compile-command))
+ :style radio
+ :selected (equal verilog-tool nil)
+ :help "When invoking compilation, use compile-command"]
+ ["Lint"
+ (progn
+ (setq verilog-tool 'verilog-linter)
+ (verilog-set-compile-command))
+ :style radio
+ :selected (equal verilog-tool `verilog-linter)
+ :help "When invoking compilation, use lint checker"]
+ ["Coverage"
+ (progn
+ (setq verilog-tool 'verilog-coverage)
+ (verilog-set-compile-command))
+ :style radio
+ :selected (equal verilog-tool `verilog-coverage)
+ :help "When invoking compilation, annotate for coverage"]
+ ["Simulator"
+ (progn
+ (setq verilog-tool 'verilog-simulator)
+ (verilog-set-compile-command))
+ :style radio
+ :selected (equal verilog-tool `verilog-simulator)
+ :help "When invoking compilation, interpret Verilog source"]
+ ["Compiler"
+ (progn
+ (setq verilog-tool 'verilog-compiler)
+ (verilog-set-compile-command))
+ :style radio
+ :selected (equal verilog-tool `verilog-compiler)
+ :help "When invoking compilation, compile Verilog source"]
+ ["Preprocessor"
+ (progn
+ (setq verilog-tool 'verilog-preprocessor)
+ (verilog-set-compile-command))
+ :style radio
+ :selected (equal verilog-tool `verilog-preprocessor)
+ :help "When invoking compilation, preprocess Verilog source, see also `verilog-preprocess'"]
+ )
+ ("Move"
+ ["Beginning of function" verilog-beg-of-defun
+ :keys "C-M-a"
+ :help "Move backward to the beginning of the current function or procedure"]
+ ["End of function" verilog-end-of-defun
+ :keys "C-M-e"
+ :help "Move forward to the end of the current function or procedure"]
+ ["Mark function" verilog-mark-defun
+ :keys "C-M-h"
+ :help "Mark the current Verilog function or procedure"]
+ ["Goto function/module" verilog-goto-defun
+ :help "Move to specified Verilog module/task/function"]
+ ["Move to beginning of block" electric-verilog-backward-sexp
+ :help "Move backward over one balanced expression"]
+ ["Move to end of block" electric-verilog-forward-sexp
+ :help "Move forward over one balanced expression"]
+ )
+ ("Comments"
+ ["Comment Region" verilog-comment-region
+ :help "Put marked area into a comment"]
+ ["UnComment Region" verilog-uncomment-region
+ :help "Uncomment an area commented with Comment Region"]
+ ["Multi-line comment insert" verilog-star-comment
+ :help "Insert Verilog /* */ comment at point"]
+ ["Lint error to comment" verilog-lint-off
+ :help "Convert a Verilog linter warning line into a disable statement"]
+ )
+ "----"
+ ["Compile" compile
+ :help "Perform compilation-action (above) on the current buffer"]
+ ["AUTO, Save, Compile" verilog-auto-save-compile
+ :help "Recompute AUTOs, save buffer, and compile"]
+ ["Next Compile Error" next-error
+ :help "Visit next compilation error message and corresponding source code"]
+ ["Ignore Lint Warning at point" verilog-lint-off
+ :help "Convert a Verilog linter warning line into a disable statement"]
+ "----"
+ ["Line up declarations around point" verilog-pretty-declarations
+ :help "Line up declarations around point"]
+ ["Line up equations around point" verilog-pretty-expr
+ :help "Line up expressions around point"]
+ ["Redo/insert comments on every end" verilog-label-be
+ :help "Label matching begin ... end statements"]
+ ["Expand [x:y] vector line" verilog-expand-vector
+ :help "Take a signal vector on the current line and expand it to multiple lines"]
+ ["Insert begin-end block" verilog-insert-block
+ :help "Insert begin ... end"]
+ ["Complete word" verilog-complete-word
+ :help "Complete word at point"]
+ "----"
+ ["Recompute AUTOs" verilog-auto
+ :help "Expand AUTO meta-comment statements"]
+ ["Kill AUTOs" verilog-delete-auto
+ :help "Remove AUTO expansions"]
+ ["Diff AUTOs" verilog-diff-auto
+ :help "Show differences in AUTO expansions"]
+ ["Inject AUTOs" verilog-inject-auto
+ :help "Inject AUTOs into legacy non-AUTO buffer"]
+ ("AUTO Help..."
+ ["AUTO General" (describe-function 'verilog-auto)
+ :help "Help introduction on AUTOs"]
+ ["AUTO Library Flags" (describe-variable 'verilog-library-flags)
+ :help "Help on verilog-library-flags"]
+ ["AUTO Library Path" (describe-variable 'verilog-library-directories)
+ :help "Help on verilog-library-directories"]
+ ["AUTO Library Files" (describe-variable 'verilog-library-files)
+ :help "Help on verilog-library-files"]
+ ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions)
+ :help "Help on verilog-library-extensions"]
+ ["AUTO `define Reading" (describe-function 'verilog-read-defines)
+ :help "Help on reading `defines"]
+ ["AUTO `include Reading" (describe-function 'verilog-read-includes)
+ :help "Help on parsing `includes"]
+ ["AUTOARG" (describe-function 'verilog-auto-arg)
+ :help "Help on AUTOARG - declaring module port list"]
+ ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
+ :help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
+ ["AUTOASSIGNMODPORT" (describe-function 'verilog-auto-assign-modport)
+ :help "Help on AUTOASSIGNMODPORT - creating assignments to/from modports"]
+ ["AUTOINOUT" (describe-function 'verilog-auto-inout)
+ :help "Help on AUTOINOUT - adding inouts from cells"]
+ ["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-comp)
+ :help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
+ ["AUTOINOUTIN" (describe-function 'verilog-auto-inout-in)
+ :help "Help on AUTOINOUTIN - copying i/o from another file as all inputs"]
+ ["AUTOINOUTMODPORT" (describe-function 'verilog-auto-inout-modport)
+ :help "Help on AUTOINOUTMODPORT - copying i/o from an interface modport"]
+ ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
+ :help "Help on AUTOINOUTMODULE - copying i/o from another file"]
+ ["AUTOINOUTPARAM" (describe-function 'verilog-auto-inout-param)
+ :help "Help on AUTOINOUTPARAM - copying parameters from another file"]
+ ["AUTOINPUT" (describe-function 'verilog-auto-input)
+ :help "Help on AUTOINPUT - adding inputs from cells"]
+ ["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp)
+ :help "Help on AUTOINSERTLISP - insert text from a lisp function"]
+ ["AUTOINSERTLAST" (describe-function 'verilog-auto-insert-last)
+ :help "Help on AUTOINSERTLISPLAST - insert text from a lisp function"]
+ ["AUTOINST" (describe-function 'verilog-auto-inst)
+ :help "Help on AUTOINST - adding pins for cells"]
+ ["AUTOINST (.*)" (describe-function 'verilog-auto-star)
+ :help "Help on expanding Verilog-2001 .* pins"]
+ ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param)
+ :help "Help on AUTOINSTPARAM - adding parameter pins to cells"]
+ ["AUTOLOGIC" (describe-function 'verilog-auto-logic)
+ :help "Help on AUTOLOGIC - declaring logic signals"]
+ ["AUTOOUTPUT" (describe-function 'verilog-auto-output)
+ :help "Help on AUTOOUTPUT - adding outputs from cells"]
+ ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every)
+ :help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
+ ["AUTOREG" (describe-function 'verilog-auto-reg)
+ :help "Help on AUTOREG - declaring registers for non-wires"]
+ ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input)
+ :help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
+ ["AUTORESET" (describe-function 'verilog-auto-reset)
+ :help "Help on AUTORESET - resetting always blocks"]
+ ["AUTOSENSE or AS" (describe-function 'verilog-auto-sense)
+ :help "Help on AUTOSENSE - sensitivity lists for always blocks"]
+ ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
+ :help "Help on AUTOTIEOFF - tying off unused outputs"]
+ ["AUTOUNDEF" (describe-function 'verilog-auto-undef)
+ :help "Help on AUTOUNDEF - undefine all local defines"]
+ ["AUTOUNUSED" (describe-function 'verilog-auto-unused)
+ :help "Help on AUTOUNUSED - terminating unused inputs"]
+ ["AUTOWIRE" (describe-function 'verilog-auto-wire)
+ :help "Help on AUTOWIRE - declaring wires for cells"]
+ )
+ "----"
+ ["Submit bug report" verilog-submit-bug-report
+ :help "Submit via mail a bug report on verilog-mode.el"]
+ ["Version and FAQ" verilog-faq
+ :help "Show the current version, and where to get the FAQ etc"]
+ ["Customize Verilog Mode..." verilog-customize
+ :help "Customize variables and other settings used by Verilog-Mode"]
+ ["Customize Verilog Fonts & Colors" verilog-font-customize
+ :help "Customize fonts used by Verilog-Mode."])))
+
+(easy-menu-define
+ verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
+ (verilog-easy-menu-filter
+ '("Statements"
+ ["Header" verilog-sk-header
+ :help "Insert a header block at the top of file"]
+ ["Comment" verilog-sk-comment
+ :help "Insert a comment block"]
+ "----"
+ ["Module" verilog-sk-module
+ :help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
+ ["OVM Class" verilog-sk-ovm-class
+ :help "Insert an OVM class block"]
+ ["UVM Object" verilog-sk-uvm-object
+ :help "Insert an UVM object block"]
+ ["UVM Component" verilog-sk-uvm-component
+ :help "Insert an UVM component block"]
+ ["Primitive" verilog-sk-primitive
+ :help "Insert a primitive .. (.. );.. endprimitive block"]
+ "----"
+ ["Input" verilog-sk-input
+ :help "Insert an input declaration"]
+ ["Output" verilog-sk-output
+ :help "Insert an output declaration"]
+ ["Inout" verilog-sk-inout
+ :help "Insert an inout declaration"]
+ ["Wire" verilog-sk-wire
+ :help "Insert a wire declaration"]
+ ["Reg" verilog-sk-reg
+ :help "Insert a register declaration"]
+ ["Define thing under point as a register" verilog-sk-define-signal
+ :help "Define signal under point as a register at the top of the module"]
+ "----"
+ ["Initial" verilog-sk-initial
+ :help "Insert an initial begin .. end block"]
+ ["Always" verilog-sk-always
+ :help "Insert an always @(AS) begin .. end block"]
+ ["Function" verilog-sk-function
+ :help "Insert a function .. begin .. end endfunction block"]
+ ["Task" verilog-sk-task
+ :help "Insert a task .. begin .. end endtask block"]
+ ["Specify" verilog-sk-specify
+ :help "Insert a specify .. endspecify block"]
+ ["Generate" verilog-sk-generate
+ :help "Insert a generate .. endgenerate block"]
+ "----"
+ ["Begin" verilog-sk-begin
+ :help "Insert a begin .. end block"]
+ ["If" verilog-sk-if
+ :help "Insert an if (..) begin .. end block"]
+ ["(if) else" verilog-sk-else-if
+ :help "Insert an else if (..) begin .. end block"]
+ ["For" verilog-sk-for
+ :help "Insert a for (...) begin .. end block"]
+ ["While" verilog-sk-while
+ :help "Insert a while (...) begin .. end block"]
+ ["Fork" verilog-sk-fork
+ :help "Insert a fork begin .. end .. join block"]
+ ["Repeat" verilog-sk-repeat
+ :help "Insert a repeat (..) begin .. end block"]
+ ["Case" verilog-sk-case
+ :help "Insert a case block, prompting for details"]
+ ["Casex" verilog-sk-casex
+ :help "Insert a casex (...) item: begin.. end endcase block"]
+ ["Casez" verilog-sk-casez
+ :help "Insert a casez (...) item: begin.. end endcase block"])))
+
+(defvar verilog-mode-abbrev-table nil
+ "Abbrev table in use in Verilog-mode buffers.")
+
+(define-abbrev-table 'verilog-mode-abbrev-table ())
+(verilog-define-abbrev verilog-mode-abbrev-table "class" "" 'verilog-sk-ovm-class)
+(verilog-define-abbrev verilog-mode-abbrev-table "always" "" 'verilog-sk-always)
+(verilog-define-abbrev verilog-mode-abbrev-table "begin" nil `verilog-sk-begin)
+(verilog-define-abbrev verilog-mode-abbrev-table "case" "" `verilog-sk-case)
+(verilog-define-abbrev verilog-mode-abbrev-table "for" "" `verilog-sk-for)
+(verilog-define-abbrev verilog-mode-abbrev-table "generate" "" `verilog-sk-generate)
+(verilog-define-abbrev verilog-mode-abbrev-table "initial" "" `verilog-sk-initial)
+(verilog-define-abbrev verilog-mode-abbrev-table "fork" "" `verilog-sk-fork)
+(verilog-define-abbrev verilog-mode-abbrev-table "module" "" `verilog-sk-module)
+(verilog-define-abbrev verilog-mode-abbrev-table "primitive" "" `verilog-sk-primitive)
+(verilog-define-abbrev verilog-mode-abbrev-table "repeat" "" `verilog-sk-repeat)
+(verilog-define-abbrev verilog-mode-abbrev-table "specify" "" `verilog-sk-specify)
+(verilog-define-abbrev verilog-mode-abbrev-table "task" "" `verilog-sk-task)
+(verilog-define-abbrev verilog-mode-abbrev-table "while" "" `verilog-sk-while)
+(verilog-define-abbrev verilog-mode-abbrev-table "casex" "" `verilog-sk-casex)
+(verilog-define-abbrev verilog-mode-abbrev-table "casez" "" `verilog-sk-casez)
+(verilog-define-abbrev verilog-mode-abbrev-table "if" "" `verilog-sk-if)
+(verilog-define-abbrev verilog-mode-abbrev-table "else if" "" `verilog-sk-else-if)
+(verilog-define-abbrev verilog-mode-abbrev-table "assign" "" `verilog-sk-assign)
+(verilog-define-abbrev verilog-mode-abbrev-table "function" "" `verilog-sk-function)
+(verilog-define-abbrev verilog-mode-abbrev-table "input" "" `verilog-sk-input)
+(verilog-define-abbrev verilog-mode-abbrev-table "output" "" `verilog-sk-output)
+(verilog-define-abbrev verilog-mode-abbrev-table "inout" "" `verilog-sk-inout)
+(verilog-define-abbrev verilog-mode-abbrev-table "wire" "" `verilog-sk-wire)
+(verilog-define-abbrev verilog-mode-abbrev-table "reg" "" `verilog-sk-reg)
+
+;;
+;; Macros
+;;
+
+(defsubst verilog-within-string ()
+ (nth 3 (parse-partial-sexp (point-at-bol) (point))))
+
+(defsubst verilog-string-match-fold (regexp string &optional start)
+ "Like `string-match', but use `verilog-case-fold'.
+Return index of start of first match for REGEXP in STRING, or nil.
+Matching ignores case if `verilog-case-fold' is non-nil.
+If third arg START is non-nil, start search at that index in STRING."
+ (let ((case-fold-search verilog-case-fold))
+ (string-match regexp string start)))
+
+(defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
+ "Replace occurrences of FROM-STRING with TO-STRING.
+FIXEDCASE and LITERAL as in `replace-match'. STRING is what to replace.
+The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
+will break, as the o's continuously replace. xa -> x works ok though."
+ ;; Hopefully soon to an Emacs built-in
+ ;; Also note \ in the replacement prevent multiple replacements; IE
+ ;; (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil "wire@_@")
+ ;; Gives "wire\([0-9]+\)_@" not "wire\([0-9]+\)_\([0-9]+\)"
+ (let ((start 0))
+ (while (string-match from-string string start)
+ (setq string (replace-match to-string fixedcase literal string)
+ start (min (length string) (+ (match-beginning 0) (length to-string)))))
+ string))
+
+(defsubst verilog-string-remove-spaces (string)
+ "Remove spaces surrounding STRING."
+ (save-match-data
+ (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
+ (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
+ string))
+
+(defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
+ ;; checkdoc-params: (REGEXP BOUND NOERROR)
+ "Like `re-search-forward', but skips over match in comments or strings."
+ (let ((mdata '(nil nil))) ; So match-end will return nil if no matches found
+ (while (and
+ (re-search-forward REGEXP BOUND NOERROR)
+ (setq mdata (match-data))
+ (and (verilog-skip-forward-comment-or-string)
+ (progn
+ (setq mdata '(nil nil))
+ (if BOUND
+ (< (point) BOUND)
+ t)))))
+ (store-match-data mdata)
+ (match-end 0)))
+
+(defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
+ ;; checkdoc-params: (REGEXP BOUND NOERROR)
+ "Like `re-search-backward', but skips over match in comments or strings."
+ (let ((mdata '(nil nil))) ; So match-end will return nil if no matches found
+ (while (and
+ (re-search-backward REGEXP BOUND NOERROR)
+ (setq mdata (match-data))
+ (and (verilog-skip-backward-comment-or-string)
+ (progn
+ (setq mdata '(nil nil))
+ (if BOUND
+ (> (point) BOUND)
+ t)))))
+ (store-match-data mdata)
+ (match-end 0)))
+
+(defsubst verilog-re-search-forward-quick (regexp bound noerror)
+ "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
+but trashes match data and is faster for REGEXP that doesn't match often.
+This uses `verilog-scan' and text properties to ignore comments,
+so there may be a large up front penalty for the first search."
+ (let (pt)
+ (while (and (not pt)
+ (re-search-forward regexp bound noerror))
+ (if (verilog-inside-comment-or-string-p (match-beginning 0))
+ (re-search-forward "[/\"\n]" nil t) ; Only way a comment or quote can end
+ (setq pt (match-end 0))))
+ pt))
+
+(defsubst verilog-re-search-backward-quick (regexp bound noerror)
+ ;; checkdoc-params: (REGEXP BOUND NOERROR)
+ "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
+but trashes match data and is faster for REGEXP that doesn't match often.
+This uses `verilog-scan' and text properties to ignore comments,
+so there may be a large up front penalty for the first search."
+ (let (pt)
+ (while (and (not pt)
+ (re-search-backward regexp bound noerror))
+ (if (verilog-inside-comment-or-string-p (match-beginning 0))
+ (re-search-backward "[/\"]" nil t) ; Only way a comment or quote can begin
+ (setq pt (match-beginning 0))))
+ pt))
+
+(defsubst verilog-re-search-forward-substr (substr regexp bound noerror)
+ "Like `re-search-forward', but first search for SUBSTR constant.
+Then searched for the normal REGEXP (which contains SUBSTR), with given
+BOUND and NOERROR. The REGEXP must fit within a single line.
+This speeds up complicated regexp matches."
+ ;; Problem with overlap: search-forward BAR then FOOBARBAZ won't match.
+ ;; thus require matches to be on one line, and use beginning-of-line.
+ (let (done)
+ (while (and (not done)
+ (search-forward substr bound noerror))
+ (save-excursion
+ (beginning-of-line)
+ (setq done (re-search-forward regexp (point-at-eol) noerror)))
+ (unless (and (<= (match-beginning 0) (point))
+ (>= (match-end 0) (point)))
+ (setq done nil)))
+ (when done (goto-char done))
+ done))
+;;(verilog-re-search-forward-substr "-end" "get-end-of" nil t) ; -end (test bait)
+
+(defsubst verilog-re-search-backward-substr (substr regexp bound noerror)
+ "Like `re-search-backward', but first search for SUBSTR constant.
+Then searched for the normal REGEXP (which contains SUBSTR), with given
+BOUND and NOERROR. The REGEXP must fit within a single line.
+This speeds up complicated regexp matches."
+ ;; Problem with overlap: search-backward BAR then FOOBARBAZ won't match.
+ ;; thus require matches to be on one line, and use beginning-of-line.
+ (let (done)
+ (while (and (not done)
+ (search-backward substr bound noerror))
+ (save-excursion
+ (end-of-line)
+ (setq done (re-search-backward regexp (point-at-bol) noerror)))
+ (unless (and (<= (match-beginning 0) (point))
+ (>= (match-end 0) (point)))
+ (setq done nil)))
+ (when done (goto-char done))
+ done))
+;;(verilog-re-search-backward-substr "-end" "get-end-of" nil t) ; -end (test bait)
+
+(defun verilog-delete-trailing-whitespace ()
+ "Delete trailing spaces or tabs, but not newlines nor linefeeds.
+Also add missing final newline.
+
+To call this from the command line, see \\[verilog-batch-diff-auto].
+
+To call on \\[verilog-auto], set `verilog-auto-delete-trailing-whitespace'."
+ ;; Similar to `delete-trailing-whitespace' but that's not present in XEmacs
+ (save-excursion
+ (goto-char (point-min))
+ (while (re-search-forward "[ \t]+$" nil t) ; Not syntactic WS as no formfeed
+ (replace-match "" nil nil))
+ (goto-char (point-max))
+ (unless (bolp) (insert "\n"))))
+
+(defvar compile-command)
+(defvar create-lockfiles) ; Emacs 24
+
+;; compilation program
+(defun verilog-set-compile-command ()
+ "Function to compute shell command to compile Verilog.
+
+This reads `verilog-tool' and sets `compile-command'. This specifies the
+program that executes when you type \\[compile] or
+\\[verilog-auto-save-compile].
+
+By default `verilog-tool' uses a Makefile if one exists in the
+current directory. If not, it is set to the `verilog-linter',
+`verilog-compiler', `verilog-coverage', `verilog-preprocessor',
+or `verilog-simulator' variables, as selected with the Verilog ->
+\"Choose Compilation Action\" menu.
+
+You should set `verilog-tool' or the other variables to the path and
+arguments for your Verilog simulator. For example:
+ \"vcs -p123 -O\"
+or a string like:
+ \"(cd /tmp; surecov %s)\".
+
+In the former case, the path to the current buffer is concat'ed to the
+value of `verilog-tool'; in the later, the path to the current buffer is
+substituted for the %s.
+
+Where __FLAGS__ appears in the string `verilog-current-flags'
+will be substituted.
+
+Where __FILE__ appears in the string, the variable
+`buffer-file-name' of the current buffer, without the directory
+portion, will be substituted."
+ (interactive)
+ (cond
+ ((or (file-exists-p "makefile") ;If there is a makefile, use it
+ (file-exists-p "Makefile"))
+ (set (make-local-variable 'compile-command) "make "))
+ (t
+ (set (make-local-variable 'compile-command)
+ (if verilog-tool
+ (if (string-match "%s" (eval verilog-tool))
+ (format (eval verilog-tool) (or buffer-file-name ""))
+ (concat (eval verilog-tool) " " (or buffer-file-name "")))
+ ""))))
+ (verilog-modify-compile-command))
+
+(defun verilog-expand-command (command)
+ "Replace meta-information in COMMAND and return it.
+Where __FLAGS__ appears in the string `verilog-current-flags'
+will be substituted. Where __FILE__ appears in the string, the
+current buffer's file-name, without the directory portion, will
+be substituted."
+ (setq command (verilog-string-replace-matches
+ ;; Note \\b only works if under verilog syntax table
+ "\\b__FLAGS__\\b" (verilog-current-flags)
+ t t command))
+ (setq command (verilog-string-replace-matches
+ "\\b__FILE__\\b" (file-name-nondirectory
+ (or (buffer-file-name) ""))
+ t t command))
+ command)
+
+(defun verilog-modify-compile-command ()
+ "Update `compile-command' using `verilog-expand-command'."
+ (when (and
+ (stringp compile-command)
+ (string-match "\\b\\(__FLAGS__\\|__FILE__\\)\\b" compile-command))
+ (set (make-local-variable 'compile-command)
+ (verilog-expand-command compile-command))))
+
+(if (featurep 'xemacs)
+ ;; Following code only gets called from compilation-mode-hook on XEmacs to add error handling.
+ (defun verilog-error-regexp-add-xemacs ()
+ "Teach XEmacs about verilog errors.
+Called by `compilation-mode-hook'. This allows \\[next-error] to
+find the errors."
+ (interactive)
+ (if (boundp 'compilation-error-regexp-systems-alist)
+ (if (and
+ (not (equal compilation-error-regexp-systems-list 'all))
+ (not (member compilation-error-regexp-systems-list 'verilog)))
+ (push 'verilog compilation-error-regexp-systems-list)))
+ (if (boundp 'compilation-error-regexp-alist-alist)
+ (if (not (assoc 'verilog compilation-error-regexp-alist-alist))
+ (setcdr compilation-error-regexp-alist-alist
+ (cons verilog-error-regexp-xemacs-alist
+ (cdr compilation-error-regexp-alist-alist)))))
+ (if (boundp 'compilation-font-lock-keywords)
+ (progn
+ (set (make-local-variable 'compilation-font-lock-keywords)
+ verilog-error-font-lock-keywords)
+ (font-lock-set-defaults)))
+ ;; Need to re-run compilation-error-regexp builder
+ (if (fboundp 'compilation-build-compilation-error-regexp-alist)
+ (compilation-build-compilation-error-regexp-alist))
+ ))
+
+;; Following code only gets called from compilation-mode-hook on Emacs to add error handling.
+(defun verilog-error-regexp-add-emacs ()
+ "Tell Emacs compile that we are Verilog.
+Called by `compilation-mode-hook'. This allows \\[next-error] to
+find the errors."
+ (interactive)
+ (when (boundp 'compilation-error-regexp-alist-alist)
+ (when (not (assoc 'verilog-xl-1 compilation-error-regexp-alist-alist))
+ (mapcar
+ (lambda (item)
+ (push (car item) compilation-error-regexp-alist)
+ (push item compilation-error-regexp-alist-alist))
+ verilog-error-regexp-emacs-alist))))
+
+(if (featurep 'xemacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-xemacs))
+(if (featurep 'emacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-emacs))
+
+(defconst verilog-compiler-directives
+ (eval-when-compile
+ '(
+ ;; compiler directives, from IEEE 1800-2012 section 22.1
+ "`__FILE__" "`__LINE" "`begin_keywords" "`celldefine" "`default_nettype"
+ "`define" "`else" "`elsif" "`end_keywords" "`endcelldefine" "`endif"
+ "`ifdef" "`ifndef" "`include" "`line" "`nounconnected_drive" "`pragma"
+ "`resetall" "`timescale" "`unconnected_drive" "`undef" "`undefineall"
+ ;; compiler directives not covered by IEEE 1800
+ "`case" "`default" "`endfor" "`endprotect" "`endswitch" "`endwhile" "`for"
+ "`format" "`if" "`let" "`protect" "`switch" "`timescale" "`time_scale"
+ "`while"
+ ))
+ "List of Verilog compiler directives.")
+
+(defconst verilog-directive-re
+ (verilog-regexp-words verilog-compiler-directives))
+
+(defconst verilog-directive-re-1
+ (concat "[ \t]*" verilog-directive-re))
+
+(defconst verilog-directive-begin
+ "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
+
+(defconst verilog-directive-middle
+ "\\<`\\(else\\|elsif\\|default\\|case\\)\\>")
+
+(defconst verilog-directive-end
+ "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
+
+(defconst verilog-ovm-begin-re
+ (eval-when-compile
+ (verilog-regexp-opt
+ '(
+ "`ovm_component_utils_begin"
+ "`ovm_component_param_utils_begin"
+ "`ovm_field_utils_begin"
+ "`ovm_object_utils_begin"
+ "`ovm_object_param_utils_begin"
+ "`ovm_sequence_utils_begin"
+ "`ovm_sequencer_utils_begin"
+ ) nil )))
+
+(defconst verilog-ovm-end-re
+ (eval-when-compile
+ (verilog-regexp-opt
+ '(
+ "`ovm_component_utils_end"
+ "`ovm_field_utils_end"
+ "`ovm_object_utils_end"
+ "`ovm_sequence_utils_end"
+ "`ovm_sequencer_utils_end"
+ ) nil )))
+
+(defconst verilog-uvm-begin-re
+ (eval-when-compile
+ (verilog-regexp-opt
+ '(
+ "`uvm_component_utils_begin"
+ "`uvm_component_param_utils_begin"
+ "`uvm_field_utils_begin"
+ "`uvm_object_utils_begin"
+ "`uvm_object_param_utils_begin"
+ "`uvm_sequence_utils_begin"
+ "`uvm_sequencer_utils_begin"
+ ) nil )))
+
+(defconst verilog-uvm-end-re
+ (eval-when-compile
+ (verilog-regexp-opt
+ '(
+ "`uvm_component_utils_end"
+ "`uvm_field_utils_end"
+ "`uvm_object_utils_end"
+ "`uvm_sequence_utils_end"
+ "`uvm_sequencer_utils_end"
+ ) nil )))
+
+(defconst verilog-vmm-begin-re
+ (eval-when-compile
+ (verilog-regexp-opt
+ '(
+ "`vmm_data_member_begin"
+ "`vmm_env_member_begin"
+ "`vmm_scenario_member_begin"
+ "`vmm_subenv_member_begin"
+ "`vmm_xactor_member_begin"
+ ) nil ) ) )
+
+(defconst verilog-vmm-end-re
+ (eval-when-compile
+ (verilog-regexp-opt
+ '(
+ "`vmm_data_member_end"
+ "`vmm_env_member_end"
+ "`vmm_scenario_member_end"
+ "`vmm_subenv_member_end"
+ "`vmm_xactor_member_end"
+ ) nil ) ) )
+
+(defconst verilog-vmm-statement-re
+ (eval-when-compile
+ (verilog-regexp-opt
+ '(
+ "`vmm_\\(data\\|env\\|scenario\\|subenv\\|xactor\\)_member_\\(scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\\)\\(_array\\)?"
+ ;; "`vmm_xactor_member_enum_array"
+ ;; "`vmm_xactor_member_scalar_array"
+ ;; "`vmm_xactor_member_scalar"
+ ) nil )))
+
+(defconst verilog-ovm-statement-re
+ (eval-when-compile
+ (verilog-regexp-opt
+ '(
+ ;; Statements
+ "`DUT_ERROR"
+ "`MESSAGE"
+ "`dut_error"
+ "`message"
+ "`ovm_analysis_imp_decl"
+ "`ovm_blocking_get_imp_decl"
+ "`ovm_blocking_get_peek_imp_decl"
+ "`ovm_blocking_master_imp_decl"
+ "`ovm_blocking_peek_imp_decl"
+ "`ovm_blocking_put_imp_decl"
+ "`ovm_blocking_slave_imp_decl"
+ "`ovm_blocking_transport_imp_decl"
+ "`ovm_component_registry"
+ "`ovm_component_registry_param"
+ "`ovm_component_utils"
+ "`ovm_create"
+ "`ovm_create_seq"
+ "`ovm_declare_sequence_lib"
+ "`ovm_do"
+ "`ovm_do_seq"
+ "`ovm_do_seq_with"
+ "`ovm_do_with"
+ "`ovm_error"
+ "`ovm_fatal"
+ "`ovm_field_aa_int_byte"
+ "`ovm_field_aa_int_byte_unsigned"
+ "`ovm_field_aa_int_int"
+ "`ovm_field_aa_int_int_unsigned"
+ "`ovm_field_aa_int_integer"
+ "`ovm_field_aa_int_integer_unsigned"
+ "`ovm_field_aa_int_key"
+ "`ovm_field_aa_int_longint"
+ "`ovm_field_aa_int_longint_unsigned"
+ "`ovm_field_aa_int_shortint"
+ "`ovm_field_aa_int_shortint_unsigned"
+ "`ovm_field_aa_int_string"
+ "`ovm_field_aa_object_int"
+ "`ovm_field_aa_object_string"
+ "`ovm_field_aa_string_int"
+ "`ovm_field_aa_string_string"
+ "`ovm_field_array_int"
+ "`ovm_field_array_object"
+ "`ovm_field_array_string"
+ "`ovm_field_enum"
+ "`ovm_field_event"
+ "`ovm_field_int"
+ "`ovm_field_object"
+ "`ovm_field_queue_int"
+ "`ovm_field_queue_object"
+ "`ovm_field_queue_string"
+ "`ovm_field_sarray_int"
+ "`ovm_field_string"
+ "`ovm_field_utils"
+ "`ovm_file"
+ "`ovm_get_imp_decl"
+ "`ovm_get_peek_imp_decl"
+ "`ovm_info"
+ "`ovm_info1"
+ "`ovm_info2"
+ "`ovm_info3"
+ "`ovm_info4"
+ "`ovm_line"
+ "`ovm_master_imp_decl"
+ "`ovm_msg_detail"
+ "`ovm_non_blocking_transport_imp_decl"
+ "`ovm_nonblocking_get_imp_decl"
+ "`ovm_nonblocking_get_peek_imp_decl"
+ "`ovm_nonblocking_master_imp_decl"
+ "`ovm_nonblocking_peek_imp_decl"
+ "`ovm_nonblocking_put_imp_decl"
+ "`ovm_nonblocking_slave_imp_decl"
+ "`ovm_object_registry"
+ "`ovm_object_registry_param"
+ "`ovm_object_utils"
+ "`ovm_peek_imp_decl"
+ "`ovm_phase_func_decl"
+ "`ovm_phase_task_decl"
+ "`ovm_print_aa_int_object"
+ "`ovm_print_aa_string_int"
+ "`ovm_print_aa_string_object"
+ "`ovm_print_aa_string_string"
+ "`ovm_print_array_int"
+ "`ovm_print_array_object"
+ "`ovm_print_array_string"
+ "`ovm_print_object_queue"
+ "`ovm_print_queue_int"
+ "`ovm_print_string_queue"
+ "`ovm_put_imp_decl"
+ "`ovm_rand_send"
+ "`ovm_rand_send_with"
+ "`ovm_send"
+ "`ovm_sequence_utils"
+ "`ovm_slave_imp_decl"
+ "`ovm_transport_imp_decl"
+ "`ovm_update_sequence_lib"
+ "`ovm_update_sequence_lib_and_item"
+ "`ovm_warning"
+ "`static_dut_error"
+ "`static_message") nil )))
+
+(defconst verilog-uvm-statement-re
+ (eval-when-compile
+ (verilog-regexp-opt
+ '(
+ ;; Statements
+ "`uvm_analysis_imp_decl"
+ "`uvm_blocking_get_imp_decl"
+ "`uvm_blocking_get_peek_imp_decl"
+ "`uvm_blocking_master_imp_decl"
+ "`uvm_blocking_peek_imp_decl"
+ "`uvm_blocking_put_imp_decl"
+ "`uvm_blocking_slave_imp_decl"
+ "`uvm_blocking_transport_imp_decl"
+ "`uvm_component_param_utils"
+ "`uvm_component_registry"
+ "`uvm_component_registry_param"
+ "`uvm_component_utils"
+ "`uvm_create"
+ "`uvm_create_on"
+ "`uvm_create_seq" ; Undocumented in 1.1
+ "`uvm_declare_p_sequencer"
+ "`uvm_declare_sequence_lib" ; Deprecated in 1.1
+ "`uvm_do"
+ "`uvm_do_callbacks"
+ "`uvm_do_callbacks_exit_on"
+ "`uvm_do_obj_callbacks"
+ "`uvm_do_obj_callbacks_exit_on"
+ "`uvm_do_on"
+ "`uvm_do_on_pri"
+ "`uvm_do_on_pri_with"
+ "`uvm_do_on_with"
+ "`uvm_do_pri"
+ "`uvm_do_pri_with"
+ "`uvm_do_seq" ; Undocumented in 1.1
+ "`uvm_do_seq_with" ; Undocumented in 1.1
+ "`uvm_do_with"
+ "`uvm_error"
+ "`uvm_error_context"
+ "`uvm_fatal"
+ "`uvm_fatal_context"
+ "`uvm_field_aa_int_byte"
+ "`uvm_field_aa_int_byte_unsigned"
+ "`uvm_field_aa_int_enum"
+ "`uvm_field_aa_int_int"
+ "`uvm_field_aa_int_int_unsigned"
+ "`uvm_field_aa_int_integer"
+ "`uvm_field_aa_int_integer_unsigned"
+ "`uvm_field_aa_int_key"
+ "`uvm_field_aa_int_longint"
+ "`uvm_field_aa_int_longint_unsigned"
+ "`uvm_field_aa_int_shortint"
+ "`uvm_field_aa_int_shortint_unsigned"
+ "`uvm_field_aa_int_string"
+ "`uvm_field_aa_object_int"
+ "`uvm_field_aa_object_string"
+ "`uvm_field_aa_string_int"
+ "`uvm_field_aa_string_string"
+ "`uvm_field_array_enum"
+ "`uvm_field_array_int"
+ "`uvm_field_array_object"
+ "`uvm_field_array_string"
+ "`uvm_field_enum"
+ "`uvm_field_event"
+ "`uvm_field_int"
+ "`uvm_field_object"
+ "`uvm_field_queue_enum"
+ "`uvm_field_queue_int"
+ "`uvm_field_queue_object"
+ "`uvm_field_queue_string"
+ "`uvm_field_real"
+ "`uvm_field_sarray_enum"
+ "`uvm_field_sarray_int"
+ "`uvm_field_sarray_object"
+ "`uvm_field_sarray_string"
+ "`uvm_field_string"
+ "`uvm_field_utils"
+ "`uvm_file" ; Undocumented in 1.1, use `__FILE__
+ "`uvm_get_imp_decl"
+ "`uvm_get_peek_imp_decl"
+ "`uvm_info"
+ "`uvm_info_context"
+ "`uvm_line" ; Undocumented in 1.1, use `__LINE__
+ "`uvm_master_imp_decl"
+ "`uvm_non_blocking_transport_imp_decl" ; Deprecated in 1.1
+ "`uvm_nonblocking_get_imp_decl"
+ "`uvm_nonblocking_get_peek_imp_decl"
+ "`uvm_nonblocking_master_imp_decl"
+ "`uvm_nonblocking_peek_imp_decl"
+ "`uvm_nonblocking_put_imp_decl"
+ "`uvm_nonblocking_slave_imp_decl"
+ "`uvm_nonblocking_transport_imp_decl"
+ "`uvm_object_param_utils"
+ "`uvm_object_registry"
+ "`uvm_object_registry_param" ; Undocumented in 1.1
+ "`uvm_object_utils"
+ "`uvm_pack_array"
+ "`uvm_pack_arrayN"
+ "`uvm_pack_enum"
+ "`uvm_pack_enumN"
+ "`uvm_pack_int"
+ "`uvm_pack_intN"
+ "`uvm_pack_queue"
+ "`uvm_pack_queueN"
+ "`uvm_pack_real"
+ "`uvm_pack_sarray"
+ "`uvm_pack_sarrayN"
+ "`uvm_pack_string"
+ "`uvm_peek_imp_decl"
+ "`uvm_put_imp_decl"
+ "`uvm_rand_send"
+ "`uvm_rand_send_pri"
+ "`uvm_rand_send_pri_with"
+ "`uvm_rand_send_with"
+ "`uvm_record_attribute"
+ "`uvm_record_field"
+ "`uvm_register_cb"
+ "`uvm_send"
+ "`uvm_send_pri"
+ "`uvm_sequence_utils" ; Deprecated in 1.1
+ "`uvm_set_super_type"
+ "`uvm_slave_imp_decl"
+ "`uvm_transport_imp_decl"
+ "`uvm_unpack_array"
+ "`uvm_unpack_arrayN"
+ "`uvm_unpack_enum"
+ "`uvm_unpack_enumN"
+ "`uvm_unpack_int"
+ "`uvm_unpack_intN"
+ "`uvm_unpack_queue"
+ "`uvm_unpack_queueN"
+ "`uvm_unpack_real"
+ "`uvm_unpack_sarray"
+ "`uvm_unpack_sarrayN"
+ "`uvm_unpack_string"
+ "`uvm_update_sequence_lib" ; Deprecated in 1.1
+ "`uvm_update_sequence_lib_and_item" ; Deprecated in 1.1
+ "`uvm_warning"
+ "`uvm_warning_context") nil )))
+
+
+;;
+;; Regular expressions used to calculate indent, etc.
+;;
+(defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
+;; Want to match
+;; aa :
+;; aa,bb :
+;; a[34:32] :
+;; a,
+;; b :
+(defconst verilog-assignment-operator-re
+ (eval-when-compile
+ (verilog-regexp-opt
+ `(
+ ;; blocking assignment_operator
+ "=" "+=" "-=" "*=" "/=" "%=" "&=" "|=" "^=" "<<=" ">>=" "<<<=" ">>>="
+ ;; non blocking assignment operator
+ "<="
+ ;; comparison
+ "==" "!=" "===" "!==" "<=" ">=" "==?" "!=?" "<->"
+ ;; event_trigger
+ "->" "->>"
+ ;; property_expr
+ "|->" "|=>" "#-#" "#=#"
+ ;; distribution weighting
+ ":=" ":/"
+ ) 't
+ )))
+(defconst verilog-assignment-operation-re
+ (concat
+ ;; "\\(^\\s-*[A-Za-z0-9_]+\\(\\[\\([A-Za-z0-9_]+\\)\\]\\)*\\s-*\\)"
+ ;; "\\(^\\s-*[^=<>+-*/%&|^:\\s-]+[^=<>+-*/%&|^\n]*?\\)"
+ "\\(^.*?\\)" "\\B" verilog-assignment-operator-re "\\B" ))
+
+(defconst verilog-label-re (concat verilog-symbol-re "\\s-*:\\s-*"))
+(defconst verilog-property-re
+ (concat "\\(" verilog-label-re "\\)?"
+ ;; "\\(assert\\|assume\\|cover\\)\\s-+property\\>"
+ "\\(\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(assert\\)"))
+
+(defconst verilog-no-indent-begin-re
+ (eval-when-compile
+ (verilog-regexp-words
+ '("always" "always_comb" "always_ff" "always_latch" "initial" "final" ; procedural blocks
+ "if" "else" ; conditional statements
+ "while" "for" "foreach" "repeat" "do" "forever" )))) ; loop statements
+
+(defconst verilog-ends-re
+ ;; Parenthesis indicate type of keyword found
+ (concat
+ "\\(\\<else\\>\\)\\|" ; 1
+ "\\(\\<if\\>\\)\\|" ; 2
+ "\\(\\<assert\\>\\)\\|" ; 3
+ "\\(\\<end\\>\\)\\|" ; 3.1
+ "\\(\\<endcase\\>\\)\\|" ; 4
+ "\\(\\<endfunction\\>\\)\\|" ; 5
+ "\\(\\<endtask\\>\\)\\|" ; 6
+ "\\(\\<endspecify\\>\\)\\|" ; 7
+ "\\(\\<endtable\\>\\)\\|" ; 8
+ "\\(\\<endgenerate\\>\\)\\|" ; 9
+ "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
+ "\\(\\<endclass\\>\\)\\|" ; 11
+ "\\(\\<endgroup\\>\\)\\|" ; 12
+ ;; VMM
+ "\\(\\<`vmm_data_member_end\\>\\)\\|"
+ "\\(\\<`vmm_env_member_end\\>\\)\\|"
+ "\\(\\<`vmm_scenario_member_end\\>\\)\\|"
+ "\\(\\<`vmm_subenv_member_end\\>\\)\\|"
+ "\\(\\<`vmm_xactor_member_end\\>\\)\\|"
+ ;; OVM
+ "\\(\\<`ovm_component_utils_end\\>\\)\\|"
+ "\\(\\<`ovm_field_utils_end\\>\\)\\|"
+ "\\(\\<`ovm_object_utils_end\\>\\)\\|"
+ "\\(\\<`ovm_sequence_utils_end\\>\\)\\|"
+ "\\(\\<`ovm_sequencer_utils_end\\>\\)"
+ ;; UVM
+ "\\(\\<`uvm_component_utils_end\\>\\)\\|"
+ "\\(\\<`uvm_field_utils_end\\>\\)\\|"
+ "\\(\\<`uvm_object_utils_end\\>\\)\\|"
+ "\\(\\<`uvm_sequence_utils_end\\>\\)\\|"
+ "\\(\\<`uvm_sequencer_utils_end\\>\\)"
+ ))
+
+(defconst verilog-auto-end-comment-lines-re
+ ;; Matches to names in this list cause auto-end-commenting
+ (concat "\\("
+ verilog-directive-re "\\)\\|\\("
+ (eval-when-compile
+ (verilog-regexp-words
+ `( "begin"
+ "else"
+ "end"
+ "endcase"
+ "endclass"
+ "endclocking"
+ "endgroup"
+ "endfunction"
+ "endmodule"
+ "endprogram"
+ "endprimitive"
+ "endinterface"
+ "endpackage"
+ "endsequence"
+ "endproperty"
+ "endspecify"
+ "endtable"
+ "endtask"
+ "join"
+ "join_any"
+ "join_none"
+ "module"
+ "macromodule"
+ "primitive"
+ "interface"
+ "package")))
+ "\\)"))
+
+;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
+;; verilog-end-block-ordered-re matches exactly the same strings.
+(defconst verilog-end-block-ordered-re
+ ;; Parenthesis indicate type of keyword found
+ (concat "\\(\\<endcase\\>\\)\\|" ; 1
+ "\\(\\<end\\>\\)\\|" ; 2
+ "\\(\\<end" ; 3, but not used
+ "\\(" ; 4, but not used
+ "\\(function\\)\\|" ; 5
+ "\\(task\\)\\|" ; 6
+ "\\(module\\)\\|" ; 7
+ "\\(primitive\\)\\|" ; 8
+ "\\(interface\\)\\|" ; 9
+ "\\(package\\)\\|" ; 10
+ "\\(class\\)\\|" ; 11
+ "\\(group\\)\\|" ; 12
+ "\\(program\\)\\|" ; 13
+ "\\(sequence\\)\\|" ; 14
+ "\\(clocking\\)\\|" ; 15
+ "\\(property\\)\\|" ; 16
+ "\\)\\>\\)"))
+(defconst verilog-end-block-re
+ (eval-when-compile
+ (verilog-regexp-words
+
+ `("end" ; closes begin
+ "endcase" ; closes any of case, casex casez or randcase
+ "join" "join_any" "join_none" ; closes fork
+ "endclass"
+ "endtable"
+ "endspecify"
+ "endfunction"
+ "endgenerate"
+ "endtask"
+ "endgroup"
+ "endproperty"
+ "endinterface"
+ "endpackage"
+ "endprogram"
+ "endsequence"
+ "endclocking"
+ ;; OVM
+ "`ovm_component_utils_end"
+ "`ovm_field_utils_end"
+ "`ovm_object_utils_end"
+ "`ovm_sequence_utils_end"
+ "`ovm_sequencer_utils_end"
+ ;; UVM
+ "`uvm_component_utils_end"
+ "`uvm_field_utils_end"
+ "`uvm_object_utils_end"
+ "`uvm_sequence_utils_end"
+ "`uvm_sequencer_utils_end"
+ ;; VMM
+ "`vmm_data_member_end"
+ "`vmm_env_member_end"
+ "`vmm_scenario_member_end"
+ "`vmm_subenv_member_end"
+ "`vmm_xactor_member_end"
+ ))))
+
+
+(defconst verilog-endcomment-reason-re
+ ;; Parenthesis indicate type of keyword found
+ (concat
+ "\\(\\<begin\\>\\)\\|" ; 1
+ "\\(\\<else\\>\\)\\|" ; 2
+ "\\(\\<end\\>\\s-+\\<else\\>\\)\\|" ; 3
+ "\\(\\<always\\(?:_ff\\)?\\>\\(?:[ \t]*@\\)\\)\\|" ; 4 (matches always or always_ff w/ @...)
+ "\\(\\<always\\(?:_comb\\|_latch\\)?\\>\\)\\|" ; 5 (matches always, always_comb, always_latch w/o @...)
+ "\\(\\<fork\\>\\)\\|" ; 7
+ "\\(\\<if\\>\\)\\|"
+ verilog-property-re "\\|"
+ "\\(\\(" verilog-label-re "\\)?\\<assert\\>\\)\\|"
+ "\\(\\<clocking\\>\\)\\|"
+ "\\(\\<task\\>\\)\\|"
+ "\\(\\<function\\>\\)\\|"
+ "\\(\\<initial\\>\\)\\|"
+ "\\(\\<interface\\>\\)\\|"
+ "\\(\\<package\\>\\)\\|"
+ "\\(\\<final\\>\\)\\|"
+ "\\(@\\)\\|"
+ "\\(\\<while\\>\\)\\|\\(\\<do\\>\\)\\|"
+ "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
+ "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
+ "#"))
+
+(defconst verilog-named-block-re "begin[ \t]*:")
+
+;; These words begin a block which can occur inside a module which should be indented,
+;; and closed with the respective word from the end-block list
+
+(defconst verilog-beg-block-re
+ (eval-when-compile
+ (verilog-regexp-words
+ `("begin"
+ "case" "casex" "casez" "randcase"
+ "clocking"
+ "generate"
+ "fork"
+ "function"
+ "property"
+ "specify"
+ "table"
+ "task"
+ ;; OVM
+ "`ovm_component_utils_begin"
+ "`ovm_component_param_utils_begin"
+ "`ovm_field_utils_begin"
+ "`ovm_object_utils_begin"
+ "`ovm_object_param_utils_begin"
+ "`ovm_sequence_utils_begin"
+ "`ovm_sequencer_utils_begin"
+ ;; UVM
+ "`uvm_component_utils_begin"
+ "`uvm_component_param_utils_begin"
+ "`uvm_field_utils_begin"
+ "`uvm_object_utils_begin"
+ "`uvm_object_param_utils_begin"
+ "`uvm_sequence_utils_begin"
+ "`uvm_sequencer_utils_begin"
+ ;; VMM
+ "`vmm_data_member_begin"
+ "`vmm_env_member_begin"
+ "`vmm_scenario_member_begin"
+ "`vmm_subenv_member_begin"
+ "`vmm_xactor_member_begin"
+ ))))
+;; These are the same words, in a specific order in the regular
+;; expression so that matching will work nicely for
+;; verilog-forward-sexp and verilog-calc-indent
+(defconst verilog-beg-block-re-ordered
+ ( concat "\\(\\<begin\\>\\)" ;1
+ "\\|\\(\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\>\\)" ; 2,3
+ "\\|\\(\\(\\<disable\\>\\s-+\\|\\<wait\\>\\s-+\\)?fork\\>\\)" ;4,5
+ "\\|\\(\\<class\\>\\)" ;6
+ "\\|\\(\\<table\\>\\)" ;7
+ "\\|\\(\\<specify\\>\\)" ;8
+ "\\|\\(\\<function\\>\\)" ;9
+ "\\|\\(\\(?:\\<\\(?:virtual\\|protected\\|static\\)\\>\\s-+\\)*\\<function\\>\\)" ;10
+ "\\|\\(\\<task\\>\\)" ;11
+ "\\|\\(\\(?:\\<\\(?:virtual\\|protected\\|static\\)\\>\\s-+\\)*\\<task\\>\\)" ;12
+ "\\|\\(\\<generate\\>\\)" ;13
+ "\\|\\(\\<covergroup\\>\\)" ;14
+ "\\|\\(\\(?:\\(?:\\<cover\\>\\s-+\\)\\|\\(?:\\<assert\\>\\s-+\\)\\)*\\<property\\>\\)" ;15
+ "\\|\\(\\<\\(?:rand\\)?sequence\\>\\)" ;16
+ "\\|\\(\\<clocking\\>\\)" ;17
+ "\\|\\(\\<`[ou]vm_[a-z_]+_begin\\>\\)" ;18
+ "\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)"
+ ;;
+ ))
+
+(defconst verilog-end-block-ordered-rry
+ [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
+ "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
+ "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
+ "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
+ "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
+ "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
+ "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
+ "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
+ "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
+ "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
+ "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
+ "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
+ "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
+ ] )
+
+(defconst verilog-nameable-item-re
+ (eval-when-compile
+ (verilog-regexp-words
+ `("begin"
+ "fork"
+ "join" "join_any" "join_none"
+ "end"
+ "endcase"
+ "endchecker"
+ "endclass"
+ "endclocking"
+ "endconfig"
+ "endfunction"
+ "endgenerate"
+ "endgroup"
+ "endmodule"
+ "endprimitive"
+ "endinterface"
+ "endpackage"
+ "endprogram"
+ "endproperty"
+ "endsequence"
+ "endspecify"
+ "endtable"
+ "endtask" )
+ )))
+
+(defconst verilog-declaration-opener
+ (eval-when-compile
+ (verilog-regexp-words
+ `("module" "begin" "task" "function"))))
+
+(defconst verilog-declaration-prefix-re
+ (eval-when-compile
+ (verilog-regexp-words
+ `(
+ ;; port direction
+ "inout" "input" "output" "ref"
+ ;; changeableness
+ "const" "static" "protected" "local"
+ ;; parameters
+ "localparam" "parameter" "var"
+ ;; type creation
+ "typedef"
+ ))))
+(defconst verilog-declaration-core-re
+ (eval-when-compile
+ (verilog-regexp-words
+ `(
+ ;; port direction (by themselves)
+ "inout" "input" "output"
+ ;; integer_atom_type
+ "byte" "shortint" "int" "longint" "integer" "time"
+ ;; integer_vector_type
+ "bit" "logic" "reg"
+ ;; non_integer_type
+ "shortreal" "real" "realtime"
+ ;; net_type
+ "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
+ ;; misc
+ "string" "event" "chandle" "virtual" "enum" "genvar"
+ "struct" "union"
+ ;; builtin classes
+ "mailbox" "semaphore"
+ ))))
+(defconst verilog-declaration-re
+ (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
+(defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
+(defconst verilog-optional-signed-re "\\s-*\\(\\(un\\)?signed\\)?")
+(defconst verilog-optional-signed-range-re
+ (concat
+ "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<\\(un\\)?signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
+(defconst verilog-macroexp-re "`\\sw+")
+
+(defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
+(defconst verilog-declaration-re-2-no-macro
+ (concat "\\s-*" verilog-declaration-re
+ "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
+ "\\)?"))
+(defconst verilog-declaration-re-2-macro
+ (concat "\\s-*" verilog-declaration-re
+ "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
+ "\\|\\(" verilog-macroexp-re "\\)"
+ "\\)?"))
+(defconst verilog-declaration-re-1-macro
+ (concat "^" verilog-declaration-re-2-macro))
+
+(defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
+
+(defconst verilog-defun-re
+ (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
+(defconst verilog-end-defun-re
+ (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
+(defconst verilog-zero-indent-re
+ (concat verilog-defun-re "\\|" verilog-end-defun-re))
+(defconst verilog-inst-comment-re
+ (eval-when-compile (verilog-regexp-words `("Outputs" "Inouts" "Inputs" "Interfaces" "Interfaced"))))
+
+(defconst verilog-behavioral-block-beg-re
+ (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
+ "function" "task"))))
+(defconst verilog-coverpoint-re "\\w+\\s*:\\s*\\(coverpoint\\|cross\\constraint\\)" )
+(defconst verilog-in-constraint-re ; keywords legal in constraint blocks starting a statement/block
+ (eval-when-compile (verilog-regexp-words `("if" "else" "solve" "foreach"))))
+
+(defconst verilog-indent-re
+ (eval-when-compile
+ (verilog-regexp-words
+ `(
+ "{"
+ "always" "always_latch" "always_ff" "always_comb"
+ "begin" "end"
+ ;; "unique" "priority"
+ "case" "casex" "casez" "randcase" "endcase"
+ "class" "endclass"
+ "clocking" "endclocking"
+ "config" "endconfig"
+ "covergroup" "endgroup"
+ "fork" "join" "join_any" "join_none"
+ "function" "endfunction"
+ "final"
+ "generate" "endgenerate"
+ "initial"
+ "interface" "endinterface"
+ "module" "macromodule" "endmodule"
+ "package" "endpackage"
+ "primitive" "endprimitive"
+ "program" "endprogram"
+ "property" "endproperty"
+ "sequence" "randsequence" "endsequence"
+ "specify" "endspecify"
+ "table" "endtable"
+ "task" "endtask"
+ "virtual"
+ "`case"
+ "`default"
+ "`define" "`undef"
+ "`if" "`ifdef" "`ifndef" "`else" "`elsif" "`endif"
+ "`while" "`endwhile"
+ "`for" "`endfor"
+ "`format"
+ "`include"
+ "`let"
+ "`protect" "`endprotect"
+ "`switch" "`endswitch"
+ "`timescale"
+ "`time_scale"
+ ;; OVM Begin tokens
+ "`ovm_component_utils_begin"
+ "`ovm_component_param_utils_begin"
+ "`ovm_field_utils_begin"
+ "`ovm_object_utils_begin"
+ "`ovm_object_param_utils_begin"
+ "`ovm_sequence_utils_begin"
+ "`ovm_sequencer_utils_begin"
+ ;; OVM End tokens
+ "`ovm_component_utils_end"
+ "`ovm_field_utils_end"
+ "`ovm_object_utils_end"
+ "`ovm_sequence_utils_end"
+ "`ovm_sequencer_utils_end"
+ ;; UVM Begin tokens
+ "`uvm_component_utils_begin"
+ "`uvm_component_param_utils_begin"
+ "`uvm_field_utils_begin"
+ "`uvm_object_utils_begin"
+ "`uvm_object_param_utils_begin"
+ "`uvm_sequence_utils_begin"
+ "`uvm_sequencer_utils_begin"
+ ;; UVM End tokens
+ "`uvm_component_utils_end" ; Typo in spec, it's not uvm_component_end
+ "`uvm_field_utils_end"
+ "`uvm_object_utils_end"
+ "`uvm_sequence_utils_end"
+ "`uvm_sequencer_utils_end"
+ ;; VMM Begin tokens
+ "`vmm_data_member_begin"
+ "`vmm_env_member_begin"
+ "`vmm_scenario_member_begin"
+ "`vmm_subenv_member_begin"
+ "`vmm_xactor_member_begin"
+ ;; VMM End tokens
+ "`vmm_data_member_end"
+ "`vmm_env_member_end"
+ "`vmm_scenario_member_end"
+ "`vmm_subenv_member_end"
+ "`vmm_xactor_member_end"
+ ))))
+
+(defconst verilog-defun-level-not-generate-re
+ (eval-when-compile
+ (verilog-regexp-words
+ `( "module" "macromodule" "primitive" "class" "program"
+ "interface" "package" "config"))))
+
+(defconst verilog-defun-level-re
+ (eval-when-compile
+ (verilog-regexp-words
+ (append
+ `( "module" "macromodule" "primitive" "class" "program"
+ "interface" "package" "config")
+ `( "initial" "final" "always" "always_comb" "always_ff"
+ "always_latch" "endtask" "endfunction" )))))
+
+(defconst verilog-defun-level-generate-only-re
+ (eval-when-compile
+ (verilog-regexp-words
+ `( "initial" "final" "always" "always_comb" "always_ff"
+ "always_latch" "endtask" "endfunction" ))))
+
+(defconst verilog-cpp-level-re
+ (eval-when-compile
+ (verilog-regexp-words
+ `(
+ "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
+ ))))
+
+(defconst verilog-dpi-import-export-re
+ (eval-when-compile
+ "\\(\\<\\(import\\|export\\)\\>\\s-+\"DPI\\(-C\\)?\"\\s-+\\(\\<\\(context\\|pure\\)\\>\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_]*\\s-*=\\s-*\\)?\\<\\(function\\|task\\)\\>\\)"
+ ))
+
+(defconst verilog-default-clocking-re "\\<default\\s-+clocking\\>")
+(defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
+(defconst verilog-extended-case-re "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\|randcase\\)")
+(defconst verilog-extended-complete-re
+ ;; verilog-beg-of-statement also looks backward one token to extend this match
+ (concat "\\(\\(\\<extern\\s-+\\|\\<\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\|\\<static\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
+ "\\|\\(\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)\\)"
+ "\\|\\(\\(\\<\\(import\\|export\\)\\>\\s-+\\)?\\(\"DPI\\(-C\\)?\"\\s-+\\)?\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_]*\\s-*=\\s-*\\)?\\(function\\>\\|task\\>\\)\\)"
+ "\\|" verilog-extended-case-re ))
+(defconst verilog-basic-complete-re
+ (eval-when-compile
+ (verilog-regexp-words
+ `(
+ "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
+ "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
+ "if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert"
+ ))))
+(defconst verilog-complete-reg
+ (concat
+ verilog-extended-complete-re "\\|\\(" verilog-basic-complete-re "\\)"))
+
+(defconst verilog-end-statement-re
+ (concat "\\(" verilog-beg-block-re "\\)\\|\\("
+ verilog-end-block-re "\\)"))
+
+(defconst verilog-endcase-re
+ (concat verilog-extended-case-re "\\|"
+ "\\(endcase\\)\\|"
+ verilog-defun-re
+ ))
+
+(defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
+ "String used to mark beginning of excluded text.")
+(defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
+ "String used to mark end of excluded text.")
+(defconst verilog-preprocessor-re
+ (eval-when-compile
+ (concat
+ ;; single words
+ "\\(?:"
+ (verilog-regexp-words
+ `("`__FILE__"
+ "`__LINE__"
+ "`celldefine"
+ "`else"
+ "`end_keywords"
+ "`endcelldefine"
+ "`endif"
+ "`nounconnected_drive"
+ "`resetall"
+ "`unconnected_drive"
+ "`undefineall"))
+ "\\)\\|\\(?:"
+ ;; two words: i.e. `ifdef DEFINE
+ "\\<\\(`elsif\\|`ifn?def\\|`undef\\|`default_nettype\\|`begin_keywords\\)\\>\\s-"
+ "\\)\\|\\(?:"
+ ;; `line number "filename" level
+ "\\<\\(`line\\)\\>\\s-+[0-9]+\\s-+\"[^\"]+\"\\s-+[012]"
+ "\\)\\|\\(?:"
+ ;;`include "file" or `include <file>
+ "\\<\\(`include\\)\\>\\s-+\\(?:\"[^\"]+\"\\|<[^>]+>\\)"
+ "\\)\\|\\(?:"
+ ;; `pragma <stuff> (no mention in IEEE 1800-2012 that pragma can span multiple lines
+ "\\<\\(`pragma\\)\\>\\s-+.+$"
+ "\\)\\|\\(?:"
+ ;; `timescale time_unit / time_precision
+ "\\<\\(`timescale\\)\\>\\s-+10\\{0,2\\}\\s-*[munpf]?s\\s-*\\/\\s-*10\\{0,2\\}\\s-*[munpf]?s"
+ "\\)\\|\\(?:"
+ ;; `define and `if can span multiple lines if line ends in '\'. NOTE: `if is not IEEE 1800-2012
+ ;; from http://www.emacswiki.org/emacs/MultilineRegexp
+ (concat "\\<\\(`define\\|`if\\)\\>" ; directive
+ "\\s-+" ; separator
+ "\\(?:.*?\\(?:\n.*\\)*?\\)" ; definition: to end of line, then maybe more lines (excludes any trailing \n)
+ "\\(?:\n\\s-*\n\\|\\'\\)") ; blank line or EOF
+ "\\)\\|\\(?:"
+ ;; `<macro>() : i.e. `uvm_info(a,b,c) or any other pre-defined macro
+ ;; Since parameters inside the macro can have parentheses, and
+ ;; the macro can span multiple lines, just look for the opening
+ ;; parentheses and then continue to the end of the first
+ ;; non-escaped EOL
+ (concat "\\<`\\w+\\>\\s-*("
+ "\\(?:.*?\\(?:\n.*\\)*?\\)" ; definition: to end of line, then maybe more lines (excludes any trailing \n)
+ "\\(?:\n\\s-*\n\\|\\'\\)") ; blank line or EOF
+ "\\)"
+ )))
+
+(defconst verilog-keywords
+ (append verilog-compiler-directives
+ '(
+ "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
+ "assert" "assign" "assume" "automatic" "before" "begin" "bind"
+ "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
+ "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
+ "config" "const" "constraint" "context" "continue" "cover"
+ "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
+ "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
+ "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
+ "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
+ "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
+ "endtask" "enum" "event" "expect" "export" "extends" "extern"
+ "final" "first_match" "for" "force" "foreach" "forever" "fork"
+ "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
+ "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
+ "include" "initial" "inout" "input" "inside" "instance" "int"
+ "integer" "interface" "intersect" "join" "join_any" "join_none"
+ "large" "liblist" "library" "local" "localparam" "logic"
+ "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
+ "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
+ "notif0" "notif1" "null" "or" "output" "package" "packed"
+ "parameter" "pmos" "posedge" "primitive" "priority" "program"
+ "property" "protected" "pull0" "pull1" "pulldown" "pullup"
+ "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
+ "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
+ "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
+ "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
+ "showcancelled" "signed" "small" "solve" "specify" "specparam"
+ "static" "string" "strong0" "strong1" "struct" "super" "supply0"
+ "supply1" "table" "tagged" "task" "this" "throughout" "time"
+ "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
+ "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
+ "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
+ "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
+ "wire" "with" "within" "wor" "xnor" "xor"
+ ;; 1800-2009
+ "accept_on" "checker" "endchecker" "eventually" "global" "implies"
+ "let" "nexttime" "reject_on" "restrict" "s_always" "s_eventually"
+ "s_nexttime" "s_until" "s_until_with" "strong" "sync_accept_on"
+ "sync_reject_on" "unique0" "until" "until_with" "untyped" "weak"
+ ;; 1800-2012
+ "implements" "interconnect" "nettype" "soft"
+ ))
+ "List of Verilog keywords.")
+
+(defconst verilog-comment-start-regexp "//\\|/\\*"
+ "Dual comment value for `comment-start-regexp'.")
+
+(defvar verilog-mode-syntax-table
+ (let ((table (make-syntax-table)))
+ ;; Populate the syntax TABLE.
+ (modify-syntax-entry ?\\ "\\" table)
+ (modify-syntax-entry ?+ "." table)
+ (modify-syntax-entry ?- "." table)
+ (modify-syntax-entry ?= "." table)
+ (modify-syntax-entry ?% "." table)
+ (modify-syntax-entry ?< "." table)
+ (modify-syntax-entry ?> "." table)
+ (modify-syntax-entry ?& "." table)
+ (modify-syntax-entry ?| "." table)
+ (modify-syntax-entry ?` "w" table) ; ` is part of definition symbols in Verilog
+ (modify-syntax-entry ?_ "w" table)
+ (modify-syntax-entry ?\' "." table)
+
+ ;; Set up TABLE to handle block and line style comments.
+ (if (featurep 'xemacs)
+ (progn
+ ;; XEmacs (formerly Lucid) has the best implementation
+ (modify-syntax-entry ?/ ". 1456" table)
+ (modify-syntax-entry ?* ". 23" table)
+ (modify-syntax-entry ?\n "> b" table))
+ ;; Emacs does things differently, but we can work with it
+ (modify-syntax-entry ?/ ". 124b" table)
+ (modify-syntax-entry ?* ". 23" table)
+ (modify-syntax-entry ?\n "> b" table))
+ table)
+ "Syntax table used in Verilog mode buffers.")
+
+(defvar verilog-font-lock-keywords nil
+ "Default highlighting for Verilog mode.")
+
+(defvar verilog-font-lock-keywords-1 nil
+ "Subdued level highlighting for Verilog mode.")
+
+(defvar verilog-font-lock-keywords-2 nil
+ "Medium level highlighting for Verilog mode.
+See also `verilog-font-lock-extra-types'.")
+
+(defvar verilog-font-lock-keywords-3 nil
+ "Gaudy level highlighting for Verilog mode.
+See also `verilog-font-lock-extra-types'.")
+
+(defvar verilog-font-lock-translate-off-face
+ 'verilog-font-lock-translate-off-face
+ "Font to use for translated off regions.")
+(defface verilog-font-lock-translate-off-face
+ '((((class color)
+ (background light))
+ (:background "gray90" :italic t ))
+ (((class color)
+ (background dark))
+ (:background "gray10" :italic t ))
+ (((class grayscale) (background light))
+ (:foreground "DimGray" :italic t))
+ (((class grayscale) (background dark))
+ (:foreground "LightGray" :italic t))
+ (t (:italis t)))
+ "Font lock mode face used to background highlight translate-off regions."
+ :group 'font-lock-highlighting-faces)
+
+(defvar verilog-font-lock-p1800-face
+ 'verilog-font-lock-p1800-face
+ "Font to use for p1800 keywords.")
+(defface verilog-font-lock-p1800-face
+ '((((class color)
+ (background light))
+ (:foreground "DarkOrange3" :bold t ))
+ (((class color)
+ (background dark))
+ (:foreground "orange1" :bold t ))
+ (t (:italic t)))
+ "Font lock mode face used to highlight P1800 keywords."
+ :group 'font-lock-highlighting-faces)
+
+(defvar verilog-font-lock-ams-face
+ 'verilog-font-lock-ams-face
+ "Font to use for Analog/Mixed Signal keywords.")
+(defface verilog-font-lock-ams-face
+ '((((class color)
+ (background light))
+ (:foreground "Purple" :bold t ))
+ (((class color)
+ (background dark))
+ (:foreground "orange1" :bold t ))
+ (t (:italic t)))
+ "Font lock mode face used to highlight AMS keywords."
+ :group 'font-lock-highlighting-faces)
+
+(defvar verilog-font-lock-grouping-keywords-face
+ 'verilog-font-lock-grouping-keywords-face
+ "Font to use for Verilog Grouping Keywords (such as begin..end).")
+(defface verilog-font-lock-grouping-keywords-face
+ '((((class color)
+ (background light))
+ (:foreground "Purple" :bold t ))
+ (((class color)
+ (background dark))
+ (:foreground "orange1" :bold t ))
+ (t (:italic t)))
+ "Font lock mode face used to highlight verilog grouping keywords."
+ :group 'font-lock-highlighting-faces)
+
+(let* ((verilog-type-font-keywords
+ (eval-when-compile
+ (verilog-regexp-opt
+ '(
+ "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
+ "event" "genvar" "inout" "input" "integer" "localparam"
+ "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0" "notif1" "or"
+ "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
+ "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
+ "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
+ "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
+ "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
+ "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
+ ) nil )))
+
+ (verilog-pragma-keywords
+ (eval-when-compile
+ (verilog-regexp-opt
+ '("surefire" "auto" "synopsys" "rtl_synthesis" "verilint" "leda" "0in"
+ ) nil )))
+
+ (verilog-1800-2005-keywords
+ (eval-when-compile
+ (verilog-regexp-opt
+ '("alias" "assert" "assume" "automatic" "before" "bind"
+ "bins" "binsof" "break" "byte" "cell" "chandle" "class"
+ "clocking" "config" "const" "constraint" "context" "continue"
+ "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
+ "dist" "do" "edge" "endclass" "endclocking" "endconfig"
+ "endgroup" "endprogram" "endproperty" "endsequence" "enum"
+ "expect" "export" "extends" "extern" "first_match" "foreach"
+ "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
+ "illegal_bins" "import" "incdir" "include" "inside" "instance"
+ "int" "intersect" "large" "liblist" "library" "local" "longint"
+ "matches" "medium" "modport" "new" "noshowcancelled" "null"
+ "packed" "program" "property" "protected" "pull0" "pull1"
+ "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
+ "randcase" "randsequence" "ref" "release" "return" "scalared"
+ "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
+ "specparam" "static" "string" "strong0" "strong1" "struct"
+ "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
+ "type" "union" "unsigned" "use" "var" "virtual" "void"
+ "wait_order" "weak0" "weak1" "wildcard" "with" "within"
+ ) nil )))
+
+ (verilog-1800-2009-keywords
+ (eval-when-compile
+ (verilog-regexp-opt
+ '("accept_on" "checker" "endchecker" "eventually" "global"
+ "implies" "let" "nexttime" "reject_on" "restrict" "s_always"
+ "s_eventually" "s_nexttime" "s_until" "s_until_with" "strong"
+ "sync_accept_on" "sync_reject_on" "unique0" "until"
+ "until_with" "untyped" "weak" ) nil )))
+
+ (verilog-1800-2012-keywords
+ (eval-when-compile
+ (verilog-regexp-opt
+ '("implements" "interconnect" "nettype" "soft" ) nil )))
+
+ (verilog-ams-keywords
+ (eval-when-compile
+ (verilog-regexp-opt
+ '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
+ "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
+ "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
+ "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
+ "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
+ "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
+ "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
+ "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
+ "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
+ "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
+ "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
+
+ (verilog-font-keywords
+ (eval-when-compile
+ (verilog-regexp-opt
+ '(
+ "assign" "case" "casex" "casez" "randcase" "deassign"
+ "default" "disable" "else" "endcase" "endfunction"
+ "endgenerate" "endinterface" "endmodule" "endprimitive"
+ "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
+ "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
+ "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
+ "package" "endpackage" "always" "always_comb" "always_ff"
+ "always_latch" "posedge" "primitive" "priority" "release"
+ "repeat" "specify" "table" "task" "unique" "wait" "while"
+ "class" "program" "endclass" "endprogram"
+ ) nil )))
+
+ (verilog-font-grouping-keywords
+ (eval-when-compile
+ (verilog-regexp-opt
+ '( "begin" "end" ) nil ))))
+
+ (setq verilog-font-lock-keywords
+ (list
+ ;; Fontify all builtin keywords
+ (concat "\\<\\(" verilog-font-keywords "\\|"
+ ;; And user/system tasks and functions
+ "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
+ "\\)\\>")
+ ;; Fontify all types
+ (if verilog-highlight-grouping-keywords
+ (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
+ 'verilog-font-lock-grouping-keywords-face)
+ (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
+ 'font-lock-type-face))
+ (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
+ 'font-lock-type-face)
+ ;; Fontify IEEE-1800-2005 keywords appropriately
+ (if verilog-highlight-p1800-keywords
+ (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
+ 'verilog-font-lock-p1800-face)
+ (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
+ 'font-lock-type-face))
+ ;; Fontify IEEE-1800-2009 keywords appropriately
+ (if verilog-highlight-p1800-keywords
+ (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
+ 'verilog-font-lock-p1800-face)
+ (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
+ 'font-lock-type-face))
+ ;; Fontify IEEE-1800-2012 keywords appropriately
+ (if verilog-highlight-p1800-keywords
+ (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
+ 'verilog-font-lock-p1800-face)
+ (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
+ 'font-lock-type-face))
+ ;; Fontify Verilog-AMS keywords
+ (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
+ 'verilog-font-lock-ams-face)))
+
+ (setq verilog-font-lock-keywords-1
+ (append verilog-font-lock-keywords
+ (list
+ ;; Fontify module definitions
+ (list
+ "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
+ '(1 font-lock-keyword-face)
+ '(3 font-lock-function-name-face 'prepend))
+ ;; Fontify function definitions
+ (list
+ (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
+ '(1 font-lock-keyword-face)
+ '(3 font-lock-constant-face prepend))
+ '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
+ (1 font-lock-keyword-face)
+ (2 font-lock-constant-face append))
+ '("\\<function\\>\\s-+\\(\\sw+\\)"
+ 1 'font-lock-constant-face append))))
+
+ (setq verilog-font-lock-keywords-2
+ (append verilog-font-lock-keywords-1
+ (list
+ ;; Fontify pragmas
+ (concat "\\(//\\s-*\\(" verilog-pragma-keywords "\\)\\s-.*\\)")
+ ;; Fontify escaped names
+ '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
+ ;; Fontify macro definitions/ uses
+ '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
+ 'font-lock-preprocessor-face
+ 'font-lock-type-face))
+ ;; Fontify delays/numbers
+ '("\\(@\\)\\|\\([ \t\n\f\r]#\\s-*\\(\\([0-9_.]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
+ 0 font-lock-type-face append)
+ ;; Fontify property/sequence cycle delays - these start with '##'
+ '("\\(##\\(\\sw+\\|\\[[^]]+\\]\\)\\)"
+ 0 font-lock-type-face append)
+ ;; Fontify instantiation names
+ '("\\([A-Za-z][A-Za-z0-9_]*\\)\\s-*(" 1 font-lock-function-name-face)
+ )))
+
+ (setq verilog-font-lock-keywords-3
+ (append verilog-font-lock-keywords-2
+ (when verilog-highlight-translate-off
+ (list
+ ;; Fontify things in translate off regions
+ '(verilog-match-translate-off
+ (0 'verilog-font-lock-translate-off-face prepend))
+ )))))
+
+;;
+;; Buffer state preservation
+
+(defmacro verilog-save-buffer-state (&rest body)
+ "Execute BODY forms, saving state around insignificant change.
+Changes in text properties like `face' or `syntax-table' are
+considered insignificant. This macro allows text properties to
+be changed, even in a read-only buffer.
+
+A change is considered significant if it affects the buffer text
+in any way that isn't completely restored again. Any
+user-visible changes to the buffer must not be within a
+`verilog-save-buffer-state'."
+ `(let ((inhibit-point-motion-hooks t)
+ (verilog-no-change-functions t))
+ ,(if (fboundp 'with-silent-modifications)
+ `(with-silent-modifications ,@body)
+ ;; Backward compatible version of with-silent-modifications
+ `(let* ((modified (buffer-modified-p))
+ (buffer-undo-list t)
+ (inhibit-read-only t)
+ (inhibit-modification-hooks t)
+ ;; XEmacs ignores inhibit-modification-hooks.
+ before-change-functions after-change-functions
+ deactivate-mark
+ buffer-file-name ; Prevent primitives checking
+ buffer-file-truename) ; for file modification
+ (unwind-protect
+ (progn ,@body)
+ (and (not modified)
+ (buffer-modified-p)
+ (verilog-restore-buffer-modified-p nil)))))))
+
+
+(defvar verilog-save-font-mod-hooked nil
+ "Local variable when inside a `verilog-save-font-no-change-functions' block.")
+(make-variable-buffer-local 'verilog-save-font-mod-hooked)
+
+(defmacro verilog-save-font-no-change-functions (&rest body)
+ "Execute BODY forms, disabling all change hooks in BODY.
+Includes temporary disabling of `font-lock' to restore the buffer
+to full text form for parsing. Additional actions may be specified with
+`verilog-before-save-font-hook' and `verilog-after-save-font-hook'.
+For insignificant changes, see instead `verilog-save-buffer-state'."
+ `(if verilog-save-font-mod-hooked ; Short-circuit a recursive call
+ (progn ,@body)
+ ;; Before version 20, match-string with font-lock returns a
+ ;; vector that is not equal to the string. IE if on "input"
+ ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
+ ;; Therefore we must remove and restore font-lock mode
+ (verilog-run-hooks 'verilog-before-save-font-hook)
+ (let* ((verilog-save-font-mod-hooked (- (point-max) (point-min)))
+ ;; Significant speed savings with no font-lock properties
+ (fontlocked (when (and (boundp 'font-lock-mode) font-lock-mode)
+ (font-lock-mode 0)
+ t)))
+ (run-hook-with-args 'before-change-functions (point-min) (point-max))
+ (unwind-protect
+ ;; Must inhibit and restore hooks before restoring font-lock
+ (let* ((inhibit-point-motion-hooks t)
+ (inhibit-modification-hooks t)
+ (verilog-no-change-functions t)
+ ;; XEmacs and pre-Emacs 21 ignore inhibit-modification-hooks.
+ before-change-functions after-change-functions)
+ (progn ,@body))
+ ;; Unwind forms
+ (run-hook-with-args 'after-change-functions (point-min) (point-max)
+ verilog-save-font-mod-hooked) ; old length
+ (when fontlocked (font-lock-mode t))
+ (verilog-run-hooks 'verilog-after-save-font-hook)))))
+
+;;
+;; Comment detection and caching
+
+(defvar verilog-scan-cache-preserving nil
+ "If true, the specified buffer's comment properties are static.
+Buffer changes will be ignored. See `verilog-inside-comment-or-string-p'
+and `verilog-scan'.")
+
+(defvar verilog-scan-cache-tick nil
+ "Modification tick at which `verilog-scan' was last completed.")
+(make-variable-buffer-local 'verilog-scan-cache-tick)
+
+(defun verilog-scan-cache-flush ()
+ "Flush the `verilog-scan' cache."
+ (setq verilog-scan-cache-tick nil))
+
+(defun verilog-scan-cache-ok-p ()
+ "Return t if the scan cache is up to date."
+ (or (and verilog-scan-cache-preserving
+ (eq verilog-scan-cache-preserving (current-buffer))
+ verilog-scan-cache-tick)
+ (equal verilog-scan-cache-tick (buffer-chars-modified-tick))))
+
+(defmacro verilog-save-scan-cache (&rest body)
+ "Execute the BODY forms, allowing scan cache preservation within BODY.
+This requires that insertions must use `verilog-insert'."
+ ;; If the buffer is out of date, trash it, as we'll not check later the tick
+ ;; Note this must work properly if there's multiple layers of calls
+ ;; to verilog-save-scan-cache even with differing ticks.
+ `(progn
+ (unless (verilog-scan-cache-ok-p) ; Must be before let
+ (setq verilog-scan-cache-tick nil))
+ (let* ((verilog-scan-cache-preserving (current-buffer)))
+ (progn ,@body))))
+
+(defun verilog-scan-region (beg end)
+ "Parse between BEG and END for `verilog-inside-comment-or-string-p'.
+This creates v-cmts properties where comments are in force."
+ ;; Why properties and not overlays? Overlays have much slower non O(1)
+ ;; lookup times.
+ ;; This function is warm - called on every verilog-insert
+ (save-excursion
+ (save-match-data
+ (verilog-save-buffer-state
+ (let (pt)
+ (goto-char beg)
+ (while (< (point) end)
+ (cond ((looking-at "//")
+ (setq pt (point))
+ (or (search-forward "\n" end t)
+ (goto-char end))
+ ;; "1+": The leading // or /* itself isn't considered as
+ ;; being "inside" the comment, so that a (search-backward)
+ ;; that lands at the start of the // won't mis-indicate
+ ;; it's inside a comment. Also otherwise it would be
+ ;; hard to find a commented out /*AS*/ vs one that isn't
+ (put-text-property (1+ pt) (point) 'v-cmts t))
+ ((looking-at "/\\*")
+ (setq pt (point))
+ (or (search-forward "*/" end t)
+ ;; No error - let later code indicate it so we can
+ ;; use inside functions on-the-fly
+ ;;(error "%s: Unmatched /* */, at char %d"
+ ;; (verilog-point-text) (point))
+ (goto-char end))
+ (put-text-property (1+ pt) (point) 'v-cmts t))
+ ((looking-at "\"")
+ (setq pt (point))
+ (or (re-search-forward "[^\\]\"" end t) ; don't forward-char first, since we look for a non backslash first
+ ;; No error - let later code indicate it so we can
+ (goto-char end))
+ (put-text-property (1+ pt) (point) 'v-cmts t))
+ (t
+ (forward-char 1)
+ (if (re-search-forward "[/\"]" end t)
+ (backward-char 1)
+ (goto-char end))))))))))
+
+(defun verilog-scan ()
+ "Parse the buffer, marking all comments with properties.
+Also assumes any text inserted since `verilog-scan-cache-tick'
+either is ok to parse as a non-comment, or `verilog-insert' was used."
+ ;; See also `verilog-scan-debug' and `verilog-scan-and-debug'
+ (unless (verilog-scan-cache-ok-p)
+ (save-excursion
+ (verilog-save-buffer-state
+ (when verilog-debug
+ (message "Scanning %s cache=%s cachetick=%S tick=%S" (current-buffer)
+ verilog-scan-cache-preserving verilog-scan-cache-tick
+ (buffer-chars-modified-tick)))
+ (remove-text-properties (point-min) (point-max) '(v-cmts nil))
+ (verilog-scan-region (point-min) (point-max))
+ (setq verilog-scan-cache-tick (buffer-chars-modified-tick))
+ (when verilog-debug (message "Scanning... done"))))))
+
+(defun verilog-scan-debug ()
+ "For debugging, show with display face results of `verilog-scan'."
+ (font-lock-mode 0)
+ ;;(if dbg (setq dbg (concat dbg (format "verilog-scan-debug\n"))))
+ (save-excursion
+ (goto-char (point-min))
+ (remove-text-properties (point-min) (point-max) '(face nil))
+ (while (not (eobp))
+ (cond ((get-text-property (point) 'v-cmts)
+ (put-text-property (point) (1+ (point)) `face 'underline)
+ ;;(if dbg (setq dbg (concat dbg (format " v-cmts at %S\n" (point)))))
+ (forward-char 1))
+ (t
+ (goto-char (or (next-property-change (point)) (point-max))))))))
+
+(defun verilog-scan-and-debug ()
+ "For debugging, run `verilog-scan' and `verilog-scan-debug'."
+ (let (verilog-scan-cache-preserving
+ verilog-scan-cache-tick)
+ (goto-char (point-min))
+ (verilog-scan)
+ (verilog-scan-debug)))
+
+(defun verilog-inside-comment-or-string-p (&optional pos)
+ "Check if optional point POS is inside a comment.
+This may require a slow pre-parse of the buffer with `verilog-scan'
+to establish comment properties on all text."
+ ;; This function is very hot
+ (verilog-scan)
+ (if pos
+ (and (>= pos (point-min))
+ (get-text-property pos 'v-cmts))
+ (get-text-property (point) 'v-cmts)))
+
+(defun verilog-insert (&rest stuff)
+ "Insert STUFF arguments, tracking for `verilog-inside-comment-or-string-p'.
+Any insert that includes a comment must have the entire comment
+inserted using a single call to `verilog-insert'."
+ (let ((pt (point)))
+ (while stuff
+ (insert (car stuff))
+ (setq stuff (cdr stuff)))
+ (verilog-scan-region pt (point))))
+
+;; More searching
+
+(defun verilog-declaration-end ()
+ (search-forward ";"))
+
+(defun verilog-point-text (&optional pointnum)
+ "Return text describing where POINTNUM or current point is (for errors).
+Use filename, if current buffer being edited shorten to just buffer name."
+ (concat (or (and (equal (window-buffer) (current-buffer))
+ (buffer-name))
+ buffer-file-name
+ (buffer-name))
+ ":" (int-to-string (1+ (count-lines (point-min) (or pointnum (point)))))))
+
+(defun electric-verilog-backward-sexp ()
+ "Move backward over one balanced expression."
+ (interactive)
+ ;; before that see if we are in a comment
+ (verilog-backward-sexp))
+
+(defun electric-verilog-forward-sexp ()
+ "Move forward over one balanced expression."
+ (interactive)
+ ;; before that see if we are in a comment
+ (verilog-forward-sexp))
+
+(defun verilog-forward-sexp-function (arg)
+ "Move forward ARG sexps."
+ ;; Used by hs-minor-mode
+ (if (< arg 0)
+ (verilog-backward-sexp)
+ (verilog-forward-sexp)))
+
+(defun verilog-backward-sexp ()
+ (let ((reg)
+ (elsec 1)
+ (found nil)
+ (st (point)))
+ (if (not (looking-at "\\<"))
+ (forward-word-strictly -1))
+ (cond
+ ((verilog-skip-backward-comment-or-string))
+ ((looking-at "\\<else\\>")
+ (setq reg (concat
+ verilog-end-block-re
+ "\\|\\(\\<else\\>\\)"
+ "\\|\\(\\<if\\>\\)"))
+ (while (and (not found)
+ (verilog-re-search-backward reg nil 'move))
+ (cond
+ ((match-end 1) ; matched verilog-end-block-re
+ ;; try to leap back to matching outward block by striding across
+ ;; indent level changing tokens then immediately
+ ;; previous line governs indentation.
+ (verilog-leap-to-head))
+ ((match-end 2) ; else, we're in deep
+ (setq elsec (1+ elsec)))
+ ((match-end 3) ; found it
+ (setq elsec (1- elsec))
+ (if (= 0 elsec)
+ ;; Now previous line describes syntax
+ (setq found 't))))))
+ ((looking-at verilog-end-block-re)
+ (verilog-leap-to-head))
+ ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
+ (cond
+ ((match-end 1)
+ (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
+ ((match-end 2)
+ (verilog-re-search-backward "\\<primitive\\>" nil 'move))
+ ((match-end 3)
+ (verilog-re-search-backward "\\<class\\>" nil 'move))
+ ((match-end 4)
+ (verilog-re-search-backward "\\<program\\>" nil 'move))
+ ((match-end 5)
+ (verilog-re-search-backward "\\<interface\\>" nil 'move))
+ ((match-end 6)
+ (verilog-re-search-backward "\\<package\\>" nil 'move))
+ (t
+ (goto-char st)
+ (backward-sexp 1))))
+ (t
+ (goto-char st)
+ (backward-sexp)))))
+
+(defun verilog-forward-sexp ()
+ (let ((reg)
+ (md 2)
+ (st (point))
+ (nest 'yes))
+ (if (not (looking-at "\\<"))
+ (forward-word-strictly -1))
+ (cond
+ ((verilog-skip-forward-comment-or-string)
+ (verilog-forward-syntactic-ws))
+ ((looking-at verilog-beg-block-re-ordered)
+ (cond
+ ((match-end 1);
+ ;; Search forward for matching end
+ (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
+ ((match-end 2)
+ ;; Search forward for matching endcase
+ (setq reg "\\(\\<randcase\\>\\|\\(\\<unique0?\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
+ (setq md 3) ; ender is third item in regexp
+ )
+ ((match-end 4)
+ ;; might be "disable fork" or "wait fork"
+ (let
+ (here)
+ (if (or
+ (looking-at verilog-disable-fork-re)
+ (and (looking-at "fork")
+ (progn
+ (setq here (point)) ; sometimes a fork is just a fork
+ (forward-word-strictly -1)
+ (looking-at verilog-disable-fork-re))))
+ (progn ; it is a disable fork; ignore it
+ (goto-char (match-end 0))
+ (forward-word-strictly 1)
+ (setq reg nil))
+ (progn ; it is a nice simple fork
+ (goto-char here) ; return from looking for "disable fork"
+ ;; Search forward for matching join
+ (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))))
+ ((match-end 6)
+ ;; Search forward for matching endclass
+ (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
+
+ ((match-end 7)
+ ;; Search forward for matching endtable
+ (setq reg "\\<endtable\\>" )
+ (setq nest 'no))
+ ((match-end 8)
+ ;; Search forward for matching endspecify
+ (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
+ ((match-end 9)
+ ;; Search forward for matching endfunction
+ (setq reg "\\<endfunction\\>" )
+ (setq nest 'no))
+ ((match-end 10)
+ ;; Search forward for matching endfunction
+ (setq reg "\\<endfunction\\>" )
+ (setq nest 'no))
+ ((match-end 11)
+ ;; Search forward for matching endtask
+ (setq reg "\\<endtask\\>" )
+ (setq nest 'no))
+ ((match-end 12)
+ ;; Search forward for matching endtask
+ (setq reg "\\<endtask\\>" )
+ (setq nest 'no))
+ ((match-end 12)
+ ;; Search forward for matching endgenerate
+ (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
+ ((match-end 13)
+ ;; Search forward for matching endgroup
+ (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
+ ((match-end 14)
+ ;; Search forward for matching endproperty
+ (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
+ ((match-end 15)
+ ;; Search forward for matching endsequence
+ (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
+ (setq md 3)) ; 3 to get to endsequence in the reg above
+ ((match-end 17)
+ ;; Search forward for matching endclocking
+ (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
+ (if (and reg
+ (forward-word-strictly 1))
+ (catch 'skip
+ (if (eq nest 'yes)
+ (let ((depth 1)
+ here)
+ (while (verilog-re-search-forward reg nil 'move)
+ (cond
+ ((match-end md) ; a closer in regular expression, so we are climbing out
+ (setq depth (1- depth))
+ (if (= 0 depth) ; we are out!
+ (throw 'skip 1)))
+ ((match-end 1) ; an opener in the r-e, so we are in deeper now
+ (setq here (point)) ; remember where we started
+ (goto-char (match-beginning 1))
+ (cond
+ ((if (or
+ (looking-at verilog-disable-fork-re)
+ (and (looking-at "fork")
+ (progn
+ (forward-word-strictly -1)
+ (looking-at verilog-disable-fork-re))))
+ (progn ; it is a disable fork; another false alarm
+ (goto-char (match-end 0)))
+ (progn ; it is a simple fork (or has nothing to do with fork)
+ (goto-char here)
+ (setq depth (1+ depth))))))))))
+ (if (verilog-re-search-forward reg nil 'move)
+ (throw 'skip 1))))))
+
+ ((looking-at (concat
+ "\\(\\<\\(macro\\)?module\\>\\)\\|"
+ "\\(\\<primitive\\>\\)\\|"
+ "\\(\\<class\\>\\)\\|"
+ "\\(\\<program\\>\\)\\|"
+ "\\(\\<interface\\>\\)\\|"
+ "\\(\\<package\\>\\)"))
+ (cond
+ ((match-end 1)
+ (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
+ ((match-end 2)
+ (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
+ ((match-end 3)
+ (verilog-re-search-forward "\\<endclass\\>" nil 'move))
+ ((match-end 4)
+ (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
+ ((match-end 5)
+ (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
+ ((match-end 6)
+ (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
+ (t
+ (goto-char st)
+ (if (= (following-char) ?\) )
+ (forward-char 1)
+ (forward-sexp 1)))))
+ (t
+ (goto-char st)
+ (if (= (following-char) ?\) )
+ (forward-char 1)
+ (forward-sexp 1))))))
+
+(defun verilog-declaration-beg ()
+ (verilog-re-search-backward verilog-declaration-re (bobp) t))
+
+;;
+;;
+;; Mode
+;;
+(defvar verilog-which-tool 1)
+;;;###autoload
+(define-derived-mode verilog-mode prog-mode "Verilog"
+ "Major mode for editing Verilog code.
+\\<verilog-mode-map>
+See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
+AUTOs can improve coding efficiency.
+
+Use \\[verilog-faq] for a pointer to frequently asked questions.
+
+NEWLINE, TAB indents for Verilog code.
+Delete converts tabs to spaces as it moves back.
+
+Supports highlighting.
+
+Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
+with no args, if that value is non-nil.
+
+Variables controlling indentation/edit style:
+
+ variable `verilog-indent-level' (default 3)
+ Indentation of Verilog statements with respect to containing block.
+ `verilog-indent-level-module' (default 3)
+ Absolute indentation of Module level Verilog statements.
+ Set to 0 to get initial and always statements lined up
+ on the left side of your screen.
+ `verilog-indent-level-declaration' (default 3)
+ Indentation of declarations with respect to containing block.
+ Set to 0 to get them list right under containing block.
+ `verilog-indent-level-behavioral' (default 3)
+ Indentation of first begin in a task or function block
+ Set to 0 to get such code to lined up underneath the task or
+ function keyword.
+ `verilog-indent-level-directive' (default 1)
+ Indentation of \\=`ifdef/\\=`endif blocks.
+ `verilog-cexp-indent' (default 1)
+ Indentation of Verilog statements broken across lines i.e.:
+ if (a)
+ begin
+ `verilog-case-indent' (default 2)
+ Indentation for case statements.
+ `verilog-auto-newline' (default nil)
+ Non-nil means automatically newline after semicolons and the punctuation
+ mark after an end.
+ `verilog-auto-indent-on-newline' (default t)
+ Non-nil means automatically indent line after newline.
+ `verilog-tab-always-indent' (default t)
+ Non-nil means TAB in Verilog mode should always reindent the current line,
+ regardless of where in the line point is when the TAB command is used.
+ `verilog-indent-begin-after-if' (default t)
+ Non-nil means to indent begin statements following a preceding
+ if, else, while, for and repeat statements, if any. Otherwise,
+ the begin is lined up with the preceding token. If t, you get:
+ if (a)
+ begin // amount of indent based on `verilog-cexp-indent'
+ otherwise you get:
+ if (a)
+ begin
+ `verilog-auto-endcomments' (default t)
+ Non-nil means a comment /* ... */ is set after the ends which ends
+ cases, tasks, functions and modules.
+ The type and name of the object will be set between the braces.
+ `verilog-minimum-comment-distance' (default 10)
+ Minimum distance (in lines) between begin and end required before a comment
+ will be inserted. Setting this variable to zero results in every
+ end acquiring a comment; the default avoids too many redundant
+ comments in tight quarters.
+ `verilog-auto-lineup' (default `declarations')
+ List of contexts where auto lineup of code should be done.
+
+Variables controlling other actions:
+
+ `verilog-linter' (default `surelint')
+ Unix program to call to run the lint checker. This is the default
+ command for \\[compile-command] and \\[verilog-auto-save-compile].
+
+See \\[customize] for the complete list of variables.
+
+AUTO expansion functions are, in part:
+
+ \\[verilog-auto] Expand AUTO statements.
+ \\[verilog-delete-auto] Remove the AUTOs.
+ \\[verilog-inject-auto] Insert AUTOs for the first time.
+
+Some other functions are:
+
+ \\[verilog-complete-word] Complete word with appropriate possibilities.
+ \\[verilog-mark-defun] Mark function.
+ \\[verilog-beg-of-defun] Move to beginning of current function.
+ \\[verilog-end-of-defun] Move to end of current function.
+ \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
+
+ \\[verilog-comment-region] Put marked area in a comment.
+ \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
+ \\[verilog-insert-block] Insert begin ... end.
+ \\[verilog-star-comment] Insert /* ... */.
+
+ \\[verilog-sk-always] Insert an always @(AS) begin .. end block.
+ \\[verilog-sk-begin] Insert a begin .. end block.
+ \\[verilog-sk-case] Insert a case block, prompting for details.
+ \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
+ \\[verilog-sk-generate] Insert a generate .. endgenerate block.
+ \\[verilog-sk-header] Insert a header block at the top of file.
+ \\[verilog-sk-initial] Insert an initial begin .. end block.
+ \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
+ \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
+ \\[verilog-sk-ovm-class] Insert an OVM Class block.
+ \\[verilog-sk-uvm-object] Insert an UVM Object block.
+ \\[verilog-sk-uvm-component] Insert an UVM Component block.
+ \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
+ \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
+ \\[verilog-sk-specify] Insert a specify .. endspecify block.
+ \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
+ \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
+ \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
+ \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
+ \\[verilog-sk-if] Insert an if (..) begin .. end block.
+ \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
+ \\[verilog-sk-comment] Insert a comment block.
+ \\[verilog-sk-assign] Insert an assign .. = ..; statement.
+ \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
+ \\[verilog-sk-input] Insert an input declaration, prompting for details.
+ \\[verilog-sk-output] Insert an output declaration, prompting for details.
+ \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
+ \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
+ \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
+ \\[verilog-sk-reg] Insert a register declaration, prompting for details.
+ \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
+
+All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
+Key bindings specific to `verilog-mode-map' are:
+
+\\{verilog-mode-map}"
+ :abbrev-table verilog-mode-abbrev-table
+ (set (make-local-variable 'beginning-of-defun-function)
+ 'verilog-beg-of-defun)
+ (set (make-local-variable 'end-of-defun-function)
+ 'verilog-end-of-defun)
+ (set-syntax-table verilog-mode-syntax-table)
+ (set (make-local-variable 'indent-line-function)
+ #'verilog-indent-line-relative)
+ (set (make-local-variable 'comment-indent-function) 'verilog-comment-indent)
+ (set (make-local-variable 'parse-sexp-ignore-comments) nil)
+ (set (make-local-variable 'comment-start) "// ")
+ (set (make-local-variable 'comment-end) "")
+ (set (make-local-variable 'comment-start-skip) "/\\*+ *\\|// *")
+ (set (make-local-variable 'comment-multi-line) nil)
+ ;; Set up for compilation
+ (setq verilog-which-tool 1)
+ (setq verilog-tool 'verilog-linter)
+ (verilog-set-compile-command)
+ (when (boundp 'hack-local-variables-hook) ; Also modify any file-local-variables
+ (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
+
+ ;; Setting up menus
+ (when (featurep 'xemacs)
+ (easy-menu-add verilog-stmt-menu)
+ (easy-menu-add verilog-menu)
+ (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))
+
+ ;; Stuff for GNU Emacs
+ (set (make-local-variable 'font-lock-defaults)
+ `((verilog-font-lock-keywords
+ verilog-font-lock-keywords-1
+ verilog-font-lock-keywords-2
+ verilog-font-lock-keywords-3)
+ nil nil nil
+ ,(if (functionp 'syntax-ppss)
+ ;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses
+ ;; font-lock-beginning-of-syntax-function, so
+ ;; font-lock-beginning-of-syntax-function, can't use
+ ;; verilog-beg-of-defun.
+ nil
+ 'verilog-beg-of-defun)))
+ ;;------------------------------------------------------------
+ ;; now hook in 'verilog-highlight-include-files (eldo-mode.el&spice-mode.el)
+ ;; all buffer local:
+ (unless noninteractive ; Else can't see the result, and change hooks are slow
+ (when (featurep 'xemacs)
+ (make-local-hook 'font-lock-mode-hook)
+ (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in Emacs
+ (make-local-hook 'after-change-functions))
+ (add-hook 'font-lock-mode-hook 'verilog-highlight-buffer t t)
+ (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-highlight-buffer t t) ; not in Emacs
+ (add-hook 'after-change-functions 'verilog-highlight-region t t))
+
+ ;; Tell imenu how to handle Verilog.
+ (set (make-local-variable 'imenu-generic-expression)
+ verilog-imenu-generic-expression)
+ ;; Tell which-func-modes that imenu knows about verilog
+ (when (and (boundp 'which-func-modes) (listp which-func-modes))
+ (add-to-list 'which-func-modes 'verilog-mode))
+ ;; hideshow support
+ (when (boundp 'hs-special-modes-alist)
+ (unless (assq 'verilog-mode hs-special-modes-alist)
+ (setq hs-special-modes-alist
+ (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
+ verilog-forward-sexp-function)
+ hs-special-modes-alist))))
+
+ ;; Stuff for autos
+ (add-hook 'write-contents-hooks 'verilog-auto-save-check nil 'local)
+ ;; verilog-mode-hook call added by define-derived-mode
+ )
+
+;;; Integration with the speedbar
+;;
+
+;; Avoid problems with XEmacs byte-compiles.
+;; For GNU Emacs, the eval-after-load will handle if it isn't loaded yet.
+(when (eval-when-compile (fboundp 'declare-function))
+ (declare-function speedbar-add-supported-extension "speedbar" (extension)))
+
+(defun verilog-speedbar-initialize ()
+ "Initialize speedbar to understand `verilog-mode'."
+ ;; Set Verilog file extensions (extracted from `auto-mode-alist')
+ (let ((mode-alist auto-mode-alist))
+ (while mode-alist
+ (when (eq (cdar mode-alist) 'verilog-mode)
+ (speedbar-add-supported-extension (caar mode-alist)))
+ (setq mode-alist (cdr mode-alist)))))
+
+;; If the speedbar is loaded, execute initialization instructions right away,
+;; otherwise add the initialization instructions to the speedbar loader.
+(eval-after-load "speedbar" '(verilog-speedbar-initialize))
+
+
+;;; Electric functions:
+;;
+
+(defun electric-verilog-terminate-line (&optional arg)
+ "Terminate line and indent next line.
+With optional ARG, remove existing end of line comments."
+ (interactive)
+ ;; before that see if we are in a comment
+ (let ((state (save-excursion (verilog-syntax-ppss))))
+ (cond
+ ((nth 7 state) ; Inside // comment
+ (if (eolp)
+ (progn
+ (delete-horizontal-space)
+ (newline))
+ (progn
+ (newline)
+ (insert "// ")
+ (beginning-of-line)))
+ (verilog-indent-line))
+ ((nth 4 state) ; Inside any comment (hence /**/)
+ (newline)
+ (verilog-more-comment))
+ ((eolp)
+ ;; First, check if current line should be indented
+ (if (save-excursion
+ (delete-horizontal-space)
+ (beginning-of-line)
+ (skip-chars-forward " \t")
+ (if (looking-at verilog-auto-end-comment-lines-re)
+ (let ((indent-str (verilog-indent-line)))
+ ;; Maybe we should set some endcomments
+ (if verilog-auto-endcomments
+ (verilog-set-auto-endcomments indent-str arg))
+ (end-of-line)
+ (delete-horizontal-space)
+ (if arg
+ ()
+ (newline))
+ nil)
+ (progn
+ (end-of-line)
+ (delete-horizontal-space)
+ 't)))
+ ;; see if we should line up assignments
+ (progn
+ (if (or (eq 'all verilog-auto-lineup)
+ (eq 'assignments verilog-auto-lineup))
+ (verilog-pretty-expr t "\\(<\\|:\\)?=" ))
+ (newline))
+ (forward-line 1))
+ ;; Indent next line
+ (if verilog-auto-indent-on-newline
+ (verilog-indent-line)))
+ (t
+ (newline)))))
+
+(defun electric-verilog-terminate-and-indent ()
+ "Insert a newline and indent for the next statement."
+ (interactive)
+ (electric-verilog-terminate-line 1))
+
+(defun electric-verilog-semi ()
+ "Insert `;' character and reindent the line."
+ (interactive)
+ (verilog-insert-last-command-event)
+
+ (if (or (verilog-in-comment-or-string-p)
+ (verilog-in-escaped-name-p))
+ ()
+ (save-excursion
+ (beginning-of-line)
+ (verilog-forward-ws&directives)
+ (verilog-indent-line))
+ (if (and verilog-auto-newline
+ (not (verilog-parenthesis-depth)))
+ (electric-verilog-terminate-line))))
+
+(defun electric-verilog-semi-with-comment ()
+ "Insert `;' character, reindent the line and indent for comment."
+ (interactive)
+ (insert ";")
+ (save-excursion
+ (beginning-of-line)
+ (verilog-indent-line))
+ (indent-for-comment))
+
+(defun electric-verilog-colon ()
+ "Insert `:' and do all indentations except line indent on this line."
+ (interactive)
+ (verilog-insert-last-command-event)
+ ;; Do nothing if within string.
+ (if (or
+ (verilog-within-string)
+ (not (verilog-in-case-region-p)))
+ ()
+ (save-excursion
+ (let ((p (point))
+ (lim (progn (verilog-beg-of-statement) (point))))
+ (goto-char p)
+ (verilog-backward-case-item lim)
+ (verilog-indent-line)))
+ ;; (let ((verilog-tab-always-indent nil))
+ ;; (verilog-indent-line))
+ ))
+
+;;(defun electric-verilog-equal ()
+;; "Insert `=', and do indentation if within block."
+;; (interactive)
+;; (verilog-insert-last-command-event)
+;; Could auto line up expressions, but not yet
+;; (if (eq (car (verilog-calculate-indent)) 'block)
+;; (let ((verilog-tab-always-indent nil))
+;; (verilog-indent-command)))
+;; )
+
+(defun electric-verilog-tick ()
+ "Insert back-tick, and indent to column 0 if this is a CPP directive."
+ (interactive)
+ (verilog-insert-last-command-event)
+ (save-excursion
+ (if (verilog-in-directive-p)
+ (verilog-indent-line))))
+
+(defun electric-verilog-tab ()
+ "Function called when TAB is pressed in Verilog mode."
+ (interactive)
+ ;; If verilog-tab-always-indent, indent the beginning of the line.
+ (cond
+ ;; The region is active, indent it.
+ ((and (region-active-p)
+ (not (eq (region-beginning) (region-end))))
+ (indent-region (region-beginning) (region-end) nil))
+ ((or verilog-tab-always-indent
+ (save-excursion
+ (skip-chars-backward " \t")
+ (bolp)))
+ (let* ((oldpnt (point))
+ (boi-point
+ (save-excursion
+ (beginning-of-line)
+ (skip-chars-forward " \t")
+ (verilog-indent-line)
+ (back-to-indentation)
+ (point))))
+ (if (< (point) boi-point)
+ (back-to-indentation)
+ (cond ((not verilog-tab-to-comment))
+ ((not (eolp))
+ (end-of-line))
+ (t
+ (indent-for-comment)
+ (when (and (eolp) (= oldpnt (point)))
+ ;; kill existing comment
+ (beginning-of-line)
+ (re-search-forward comment-start-skip oldpnt 'move)
+ (goto-char (match-beginning 0))
+ (skip-chars-backward " \t")
+ (kill-region (point) oldpnt)))))))
+ (t (progn (insert "\t")))))
+
+
+;;; Interactive functions:
+;;
+
+(defun verilog-indent-buffer ()
+ "Indent-region the entire buffer as Verilog code.
+To call this from the command line, see \\[verilog-batch-indent]."
+ (interactive)
+ (verilog-mode)
+ (indent-region (point-min) (point-max) nil))
+
+(defun verilog-insert-block ()
+ "Insert Verilog begin ... end; block in the code with right indentation."
+ (interactive)
+ (verilog-indent-line)
+ (insert "begin")
+ (electric-verilog-terminate-line)
+ (save-excursion
+ (electric-verilog-terminate-line)
+ (insert "end")
+ (beginning-of-line)
+ (verilog-indent-line)))
+
+(defun verilog-star-comment ()
+ "Insert Verilog star comment at point."
+ (interactive)
+ (verilog-indent-line)
+ (insert "/*")
+ (save-excursion
+ (newline)
+ (insert " */"))
+ (newline)
+ (insert " * "))
+
+(defun verilog-insert-1 (fmt max)
+ "Use format string FMT to insert integers 0 to MAX - 1.
+Inserts one integer per line, at the current column. Stops early
+if it reaches the end of the buffer."
+ (let ((col (current-column))
+ (n 0))
+ (save-excursion
+ (while (< n max)
+ (insert (format fmt n))
+ (forward-line 1)
+ ;; Note that this function does not bother to check for lines
+ ;; shorter than col.
+ (if (eobp)
+ (setq n max)
+ (setq n (1+ n))
+ (move-to-column col))))))
+
+(defun verilog-insert-indices (max)
+ "Insert a set of indices into a rectangle.
+The upper left corner is defined by point. Indices begin with 0
+and extend to the MAX - 1. If no prefix arg is given, the user
+is prompted for a value. The indices are surrounded by square
+brackets []. For example, the following code with the point
+located after the first `a' gives:
+
+ a = b a[ 0] = b
+ a = b a[ 1] = b
+ a = b a[ 2] = b
+ a = b a[ 3] = b
+ a = b ==> insert-indices ==> a[ 4] = b
+ a = b a[ 5] = b
+ a = b a[ 6] = b
+ a = b a[ 7] = b
+ a = b a[ 8] = b"
+
+ (interactive "NMAX: ")
+ (verilog-insert-1 "[%3d]" max))
+
+(defun verilog-generate-numbers (max)
+ "Insert a set of generated numbers into a rectangle.
+The upper left corner is defined by point. The numbers are padded to three
+digits, starting with 000 and extending to (MAX - 1). If no prefix argument
+is supplied, then the user is prompted for the MAX number. Consider the
+following code fragment:
+
+ buf buf buf buf000
+ buf buf buf buf001
+ buf buf buf buf002
+ buf buf buf buf003
+ buf buf ==> generate-numbers ==> buf buf004
+ buf buf buf buf005
+ buf buf buf buf006
+ buf buf buf buf007
+ buf buf buf buf008"
+
+ (interactive "NMAX: ")
+ (verilog-insert-1 "%3.3d" max))
+
+(defun verilog-mark-defun ()
+ "Mark the current Verilog function (or procedure).
+This puts the mark at the end, and point at the beginning."
+ (interactive)
+ (if (featurep 'xemacs)
+ (progn
+ (push-mark (point))
+ (verilog-end-of-defun)
+ (push-mark (point))
+ (verilog-beg-of-defun)
+ (if (fboundp 'zmacs-activate-region)
+ (zmacs-activate-region)))
+ (mark-defun)))
+
+(defun verilog-comment-region (start end)
+ ;; checkdoc-params: (start end)
+ "Put the region into a Verilog comment.
+The comments that are in this area are \"deformed\":
+`*)' becomes `!(*' and `}' becomes `!{'.
+These deformed comments are returned to normal if you use
+\\[verilog-uncomment-region] to undo the commenting.
+
+The commented area starts with `verilog-exclude-str-start', and ends with
+`verilog-exclude-str-end'. But if you change these variables,
+\\[verilog-uncomment-region] won't recognize the comments."
+ (interactive "r")
+ (save-excursion
+ ;; Insert start and endcomments
+ (goto-char end)
+ (if (and (save-excursion (skip-chars-forward " \t") (eolp))
+ (not (save-excursion (skip-chars-backward " \t") (bolp))))
+ (forward-line 1)
+ (beginning-of-line))
+ (insert verilog-exclude-str-end)
+ (setq end (point))
+ (newline)
+ (goto-char start)
+ (beginning-of-line)
+ (insert verilog-exclude-str-start)
+ (newline)
+ ;; Replace end-comments within commented area
+ (goto-char end)
+ (save-excursion
+ (while (re-search-backward "\\*/" start t)
+ (replace-match "*-/" t t)))
+ (save-excursion
+ (let ((s+1 (1+ start)))
+ (while (re-search-backward "/\\*" s+1 t)
+ (replace-match "/-*" t t))))))
+
+(defun verilog-uncomment-region ()
+ "Uncomment a commented area; change deformed comments back to normal.
+This command does nothing if the pointer is not in a commented
+area. See also `verilog-comment-region'."
+ (interactive)
+ (save-excursion
+ (let ((start (point))
+ (end (point)))
+ ;; Find the boundaries of the comment
+ (save-excursion
+ (setq start (progn (search-backward verilog-exclude-str-start nil t)
+ (point)))
+ (setq end (progn (search-forward verilog-exclude-str-end nil t)
+ (point))))
+ ;; Check if we're really inside a comment
+ (if (or (equal start (point)) (<= end (point)))
+ (message "Not standing within commented area.")
+ (progn
+ ;; Remove endcomment
+ (goto-char end)
+ (beginning-of-line)
+ (let ((pos (point)))
+ (end-of-line)
+ (delete-region pos (1+ (point))))
+ ;; Change comments back to normal
+ (save-excursion
+ (while (re-search-backward "\\*-/" start t)
+ (replace-match "*/" t t)))
+ (save-excursion
+ (while (re-search-backward "/-\\*" start t)
+ (replace-match "/*" t t)))
+ ;; Remove start comment
+ (goto-char start)
+ (beginning-of-line)
+ (let ((pos (point)))
+ (end-of-line)
+ (delete-region pos (1+ (point)))))))))
+
+(defun verilog-beg-of-defun ()
+ "Move backward to the beginning of the current function or procedure."
+ (interactive)
+ (verilog-re-search-backward verilog-defun-re nil 'move))
+
+(defun verilog-beg-of-defun-quick ()
+ "Move backward to the beginning of the current function or procedure.
+Uses `verilog-scan' cache."
+ (interactive)
+ (verilog-re-search-backward-quick verilog-defun-re nil 'move))
+
+(defun verilog-end-of-defun ()
+ "Move forward to the end of the current function or procedure."
+ (interactive)
+ (verilog-re-search-forward verilog-end-defun-re nil 'move))
+
+(defun verilog-get-end-of-defun ()
+ (save-excursion
+ (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
+ (point))
+ (t
+ (error "%s: Can't find endmodule" (verilog-point-text))
+ (point-max)))))
+
+(defun verilog-label-be ()
+ "Label matching begin ... end, fork ... join and case ... endcase statements."
+ (interactive)
+ (let ((cnt 0)
+ (case-fold-search nil)
+ (oldpos (point))
+ (b (progn
+ (verilog-beg-of-defun)
+ (point-marker)))
+ (e (progn
+ (verilog-end-of-defun)
+ (point-marker))))
+ (goto-char (marker-position b))
+ (if (> (- e b) 200)
+ (message "Relabeling module..."))
+ (while (and
+ (> (marker-position e) (point))
+ (verilog-re-search-forward
+ verilog-auto-end-comment-lines-re
+ nil 'move))
+ (goto-char (match-beginning 0))
+ (let ((indent-str (verilog-indent-line)))
+ (verilog-set-auto-endcomments indent-str 't)
+ (end-of-line)
+ (delete-horizontal-space))
+ (setq cnt (1+ cnt))
+ (if (= 9 (% cnt 10))
+ (message "%d..." cnt)))
+ (goto-char oldpos)
+ (if (or
+ (> (- e b) 200)
+ (> cnt 20))
+ (message "%d lines auto commented" cnt))))
+
+(defun verilog-beg-of-statement ()
+ "Move backward to beginning of statement."
+ (interactive)
+ ;; Move back token by token until we see the end
+ ;; of some earlier line.
+ (let (h)
+ (while
+ ;; If the current point does not begin a new
+ ;; statement, as in the character ahead of us is a ';', or SOF
+ ;; or the string after us unambiguously starts a statement,
+ ;; or the token before us unambiguously ends a statement,
+ ;; then move back a token and test again.
+ (not (or
+ ;; stop if beginning of buffer
+ (bobp)
+ ;; stop if looking at a pre-processor directive
+ (looking-at "`\\w+")
+ ;; stop if we find a ;
+ (= (preceding-char) ?\;)
+ ;; stop if we see a named coverpoint
+ (looking-at "\\w+\\W*:\\W*\\(coverpoint\\|cross\\|constraint\\)")
+ ;; keep going if we are in the middle of a word
+ (not (or (looking-at "\\<") (forward-word-strictly -1)))
+ ;; stop if we see an assertion (perhaps labeled)
+ (and
+ (looking-at "\\(\\w+\\W*:\\W*\\)?\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
+ (progn
+ (setq h (point))
+ (save-excursion
+ (verilog-backward-token)
+ (if (and (looking-at verilog-label-re)
+ (not (looking-at verilog-end-block-re)))
+ (setq h (point))))
+ (goto-char h)))
+ ;; stop if we see an extended complete reg, perhaps a complete one
+ (and
+ (looking-at verilog-complete-reg)
+ (let* ((p (point)))
+ (while (and (looking-at verilog-extended-complete-re)
+ (progn (setq p (point))
+ (verilog-backward-token)
+ (/= p (point)))))
+ (goto-char p)))
+ ;; stop if we see a complete reg (previous found extended ones)
+ (looking-at verilog-basic-complete-re)
+ ;; stop if previous token is an ender
+ (save-excursion
+ (verilog-backward-token)
+ (looking-at verilog-end-block-re))))
+ (verilog-backward-syntactic-ws)
+ (verilog-backward-token))
+ ;; Now point is where the previous line ended.
+ (verilog-forward-syntactic-ws)
+ ;; Skip forward over any preprocessor directives, as they have wacky indentation
+ (if (looking-at verilog-preprocessor-re)
+ (progn (goto-char (match-end 0))
+ (verilog-forward-syntactic-ws)))))
+
+(defun verilog-beg-of-statement-1 ()
+ "Move backward to beginning of statement."
+ (interactive)
+ (if (verilog-in-comment-p)
+ (verilog-backward-syntactic-ws))
+ (let ((pt (point)))
+ (catch 'done
+ (while (not (looking-at verilog-complete-reg))
+ (setq pt (point))
+ (verilog-backward-syntactic-ws)
+ (if (or (bolp)
+ (= (preceding-char) ?\;)
+ (progn
+ (verilog-backward-token)
+ (looking-at verilog-ends-re)))
+ (progn
+ (goto-char pt)
+ (throw 'done t)))))
+ (verilog-forward-syntactic-ws)))
+;;
+;; (while (and
+;; (not (looking-at verilog-complete-reg))
+;; (not (bolp))
+;; (not (= (preceding-char) ?\;)))
+;; (verilog-backward-token)
+;; (verilog-backward-syntactic-ws)
+;; (setq pt (point)))
+;; (goto-char pt)
+;; ;(verilog-forward-syntactic-ws)
+
+(defun verilog-end-of-statement ()
+ "Move forward to end of current statement."
+ (interactive)
+ (let ((nest 0) pos)
+ (cond
+ ((verilog-in-directive-p)
+ (forward-line 1)
+ (backward-char 1))
+
+ ((looking-at verilog-beg-block-re)
+ (verilog-forward-sexp))
+
+ ((equal (char-after) ?\})
+ (forward-char))
+
+ ;; Skip to end of statement
+ ((condition-case nil
+ (setq pos
+ (catch 'found
+ (while t
+ (forward-sexp 1)
+ (verilog-skip-forward-comment-or-string)
+ (if (eolp)
+ (forward-line 1))
+ (cond ((looking-at "[ \t]*;")
+ (skip-chars-forward "^;")
+ (forward-char 1)
+ (throw 'found (point)))
+ ((save-excursion
+ (forward-sexp -1)
+ (looking-at verilog-beg-block-re))
+ (goto-char (match-beginning 0))
+ (throw 'found nil))
+ ((looking-at "[ \t]*)")
+ (throw 'found (point)))
+ ((eobp)
+ (throw 'found (point)))
+ )))
+
+ )
+ (error nil))
+ (if (not pos)
+ ;; Skip a whole block
+ (catch 'found
+ (while t
+ (verilog-re-search-forward verilog-end-statement-re nil 'move)
+ (setq nest (if (match-end 1)
+ (1+ nest)
+ (1- nest)))
+ (cond ((eobp)
+ (throw 'found (point)))
+ ((= 0 nest)
+ (throw 'found (verilog-end-of-statement))))))
+ pos)))))
+
+(defun verilog-in-case-region-p ()
+ "Return true if in a case region.
+More specifically, point @ in the line foo : @ begin"
+ (interactive)
+ (save-excursion
+ (if (and
+ (progn (verilog-forward-syntactic-ws)
+ (looking-at "\\<begin\\>"))
+ (progn (verilog-backward-syntactic-ws)
+ (= (preceding-char) ?\:)))
+ (catch 'found
+ (let ((nest 1))
+ (while t
+ (verilog-re-search-backward
+ (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
+ "\\(\\<endcase\\>\\)\\>")
+ nil 'move)
+ (cond
+ ((match-end 3)
+ (setq nest (1+ nest)))
+ ((match-end 2)
+ (if (= nest 1)
+ (throw 'found 1))
+ (setq nest (1- nest)))
+ (t
+ (throw 'found (= nest 0)))))))
+ nil)))
+
+(defun verilog-backward-up-list (arg)
+ "Call `backward-up-list' ARG, ignoring comments."
+ (let ((parse-sexp-ignore-comments t))
+ (backward-up-list arg)))
+
+(defun verilog-forward-sexp-cmt (arg)
+ "Call `forward-sexp' ARG, inside comments."
+ (let ((parse-sexp-ignore-comments nil))
+ (forward-sexp arg)))
+
+(defun verilog-forward-sexp-ign-cmt (arg)
+ "Call `forward-sexp' ARG, ignoring comments."
+ (let ((parse-sexp-ignore-comments t))
+ (forward-sexp arg)))
+
+(defun verilog-in-generate-region-p ()
+ "Return true if in a generate region.
+More specifically, after a generate and before an endgenerate."
+ (interactive)
+ (let ((nest 1))
+ (save-excursion
+ (catch 'done
+ (while (and
+ (/= nest 0)
+ (verilog-re-search-backward
+ "\\<\\(module\\)\\|\\(generate\\)\\|\\(endgenerate\\)\\>" nil 'move)
+ (cond
+ ((match-end 1) ; module - we have crawled out
+ (throw 'done 1))
+ ((match-end 2) ; generate
+ (setq nest (1- nest)))
+ ((match-end 3) ; endgenerate
+ (setq nest (1+ nest))))))))
+ (= nest 0) )) ; return nest
+
+(defun verilog-in-fork-region-p ()
+ "Return true if between a fork and join."
+ (interactive)
+ (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
+ (nest 1))
+ (save-excursion
+ (while (and
+ (/= nest 0)
+ (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
+ (cond
+ ((match-end 1) ; fork
+ (setq nest (1- nest)))
+ ((match-end 2) ; join
+ (setq nest (1+ nest)))))))
+ (= nest 0) )) ; return nest
+
+(defun verilog-in-deferred-immediate-final-p ()
+ "Return true if inside an `assert/assume/cover final' statement."
+ (interactive)
+ (and (looking-at "final")
+ (verilog-looking-back "\\<\\(?:assert\\|assume\\|cover\\)\\>\\s-+" nil))
+ )
+
+(defun verilog-backward-case-item (lim)
+ "Skip backward to nearest enclosing case item.
+Limit search to point LIM."
+ (interactive)
+ (let ((str 'nil)
+ (lim1
+ (progn
+ (save-excursion
+ (verilog-re-search-backward verilog-endcomment-reason-re
+ lim 'move)
+ (point)))))
+ ;; Try to find the real :
+ (if (save-excursion (search-backward ":" lim1 t))
+ (let ((colon 0)
+ b e )
+ (while
+ (and
+ (< colon 1)
+ (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
+ lim1 'move))
+ (cond
+ ((match-end 1) ; [
+ (setq colon (1+ colon))
+ (if (>= colon 0)
+ (error "%s: unbalanced [" (verilog-point-text))))
+ ((match-end 2) ; ]
+ (setq colon (1- colon)))
+
+ ((match-end 3) ; :
+ (setq colon (1+ colon)))))
+ ;; Skip back to beginning of case item
+ (skip-chars-backward "\t ")
+ (verilog-skip-backward-comment-or-string)
+ (setq e (point))
+ (setq b
+ (progn
+ (if
+ (verilog-re-search-backward
+ "\\<\\(randcase\\|case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
+ (progn
+ (cond
+ ((match-end 1)
+ (goto-char (match-end 1))
+ (verilog-forward-ws&directives)
+ (if (looking-at "(")
+ (progn
+ (forward-sexp)
+ (verilog-forward-ws&directives)))
+ (point))
+ (t
+ (goto-char (match-end 0))
+ (verilog-forward-ws&directives)
+ (point))))
+ (error "Malformed case item"))))
+ (setq str (buffer-substring b e))
+ (if
+ (setq e
+ (string-match
+ "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
+ (setq str (concat (substring str 0 e) "...")))
+ str)
+ 'nil)))
+
+;;; Other functions:
+;;
+
+(defun verilog-kill-existing-comment ()
+ "Kill auto comment on this line."
+ (save-excursion
+ (let* (
+ (e (progn
+ (end-of-line)
+ (point)))
+ (b (progn
+ (beginning-of-line)
+ (search-forward "//" e t))))
+ (if b
+ (delete-region (- b 2) e)))))
+
+(defconst verilog-directive-nest-re
+ (concat "\\(`else\\>\\)\\|"
+ "\\(`endif\\>\\)\\|"
+ "\\(`if\\>\\)\\|"
+ "\\(`ifdef\\>\\)\\|"
+ "\\(`ifndef\\>\\)\\|"
+ "\\(`elsif\\>\\)"))
+
+(defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
+ "Add ending comment with given INDENT-STR.
+With KILL-EXISTING-COMMENT, remove what was there before.
+Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
+Insert `// case expr ' if this line ends a case block.
+Insert `// ifdef FOO ' if this line ends code conditional on FOO.
+Insert `// NAME ' if this line ends a function, task, module,
+primitive or interface named NAME."
+ (save-excursion
+ (cond
+ (; Comment close preprocessor directives
+ (and
+ (looking-at "\\(`endif\\)\\|\\(`else\\)")
+ (or kill-existing-comment
+ (not (save-excursion
+ (end-of-line)
+ (search-backward "//" (point-at-bol) t)))))
+ (let ((nest 1) b e
+ m
+ (else (if (match-end 2) "!" " ")))
+ (end-of-line)
+ (if kill-existing-comment
+ (verilog-kill-existing-comment))
+ (delete-horizontal-space)
+ (save-excursion
+ (backward-sexp 1)
+ (while (and (/= nest 0)
+ (verilog-re-search-backward verilog-directive-nest-re nil 'move))
+ (cond
+ ((match-end 1) ; `else
+ (if (= nest 1)
+ (setq else "!")))
+ ((match-end 2) ; `endif
+ (setq nest (1+ nest)))
+ ((match-end 3) ; `if
+ (setq nest (1- nest)))
+ ((match-end 4) ; `ifdef
+ (setq nest (1- nest)))
+ ((match-end 5) ; `ifndef
+ (setq nest (1- nest)))
+ ((match-end 6) ; `elsif
+ (if (= nest 1)
+ (progn
+ (setq else "!")
+ (setq nest 0))))))
+ (if (match-end 0)
+ (setq
+ m (buffer-substring
+ (match-beginning 0)
+ (match-end 0))
+ b (progn
+ (skip-chars-forward "^ \t")
+ (verilog-forward-syntactic-ws)
+ (point))
+ e (progn
+ (skip-chars-forward "a-zA-Z0-9_")
+ (point)))))
+ (if b
+ (if (> (count-lines (point) b) verilog-minimum-comment-distance)
+ (insert (concat " // " else m " " (buffer-substring b e))))
+ (progn
+ (insert " // unmatched `else, `elsif or `endif")
+ (ding 't)))))
+
+ (; Comment close case/class/function/task/module and named block
+ (and (looking-at "\\<end")
+ (or kill-existing-comment
+ (not (save-excursion
+ (end-of-line)
+ (search-backward "//" (point-at-bol) t)))))
+ (let ((type (car indent-str)))
+ (unless (eq type 'declaration)
+ (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ; ignore named ends
+ (if (looking-at verilog-end-block-ordered-re)
+ (cond
+ (;- This is a case block; search back for the start of this case
+ (match-end 1) ; of verilog-end-block-ordered-re
+
+ (let ((err 't)
+ (str "UNMATCHED!!"))
+ (save-excursion
+ (verilog-leap-to-head)
+ (cond
+ ((looking-at "\\<randcase\\>")
+ (setq str "randcase")
+ (setq err nil))
+ ((looking-at "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
+ (goto-char (match-end 0))
+ (setq str (concat (match-string 0) " " (verilog-get-expr)))
+ (setq err nil))
+ ))
+ (end-of-line)
+ (if kill-existing-comment
+ (verilog-kill-existing-comment))
+ (delete-horizontal-space)
+ (insert (concat " // " str ))
+ (if err (ding 't))))
+
+ (;- This is a begin..end block
+ (match-end 2) ; of verilog-end-block-ordered-re
+ (let ((str " // UNMATCHED !!")
+ (err 't)
+ (here (point))
+ there
+ cntx)
+ (save-excursion
+ (verilog-leap-to-head)
+ (setq there (point))
+ (if (not (match-end 0))
+ (progn
+ (goto-char here)
+ (end-of-line)
+ (if kill-existing-comment
+ (verilog-kill-existing-comment))
+ (delete-horizontal-space)
+ (insert str)
+ (ding 't))
+ (let ((lim
+ (save-excursion (verilog-beg-of-defun) (point)))
+ (here (point)))
+ (cond
+ (;-- handle named block differently
+ (looking-at verilog-named-block-re)
+ (search-forward ":")
+ (setq there (point))
+ (setq str (verilog-get-expr))
+ (setq err nil)
+ (setq str (concat " // block: " str )))
+
+ ((verilog-in-case-region-p) ;-- handle case item differently
+ (goto-char here)
+ (setq str (verilog-backward-case-item lim))
+ (setq there (point))
+ (setq err nil)
+ (setq str (concat " // case: " str )))
+
+ (;- try to find "reason" for this begin
+ (cond
+ (;
+ (eq here (progn
+ ;; (verilog-backward-token)
+ (verilog-beg-of-statement)
+ (point)))
+ (setq err nil)
+ (setq str ""))
+ ((looking-at verilog-endcomment-reason-re)
+ (setq there (match-end 0))
+ (setq cntx (concat (match-string 0) " "))
+ (cond
+ (;- begin
+ (match-end 1)
+ (setq err nil)
+ (save-excursion
+ (if (and (verilog-continued-line)
+ (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
+ (progn
+ (goto-char (match-end 0))
+ (setq there (point))
+ (setq str
+ (concat " // " (match-string 0) " " (verilog-get-expr))))
+ (setq str ""))))
+
+ (;- else
+ (match-end 2)
+ (let ((nest 0)
+ ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
+ (catch 'skip
+ (while (verilog-re-search-backward reg nil 'move)
+ (cond
+ ((match-end 1) ; begin
+ (setq nest (1- nest)))
+ ((match-end 2) ; end
+ (setq nest (1+ nest)))
+ ((match-end 3)
+ (if (= 0 nest)
+ (progn
+ (goto-char (match-end 0))
+ (setq there (point))
+ (setq err nil)
+ (setq str (verilog-get-expr))
+ (setq str (concat " // else: !if" str ))
+ (throw 'skip 1))))
+ ((match-end 4)
+ (if (= 0 nest)
+ (progn
+ (goto-char (match-end 0))
+ (setq there (point))
+ (setq err nil)
+ (setq str (verilog-get-expr))
+ (setq str (concat " // else: !assert " str ))
+ (throw 'skip 1)))))))))
+ (;- end else
+ (match-end 3)
+ (goto-char there)
+ (let ((nest 0)
+ (reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
+ (catch 'skip
+ (while (verilog-re-search-backward reg nil 'move)
+ (cond
+ ((match-end 1) ; begin
+ (setq nest (1- nest)))
+ ((match-end 2) ; end
+ (setq nest (1+ nest)))
+ ((match-end 3)
+ (if (= 0 nest)
+ (progn
+ (goto-char (match-end 0))
+ (setq there (point))
+ (setq err nil)
+ (setq str (verilog-get-expr))
+ (setq str (concat " // else: !if" str ))
+ (throw 'skip 1))))
+ ((match-end 4)
+ (if (= 0 nest)
+ (progn
+ (goto-char (match-end 0))
+ (setq there (point))
+ (setq err nil)
+ (setq str (verilog-get-expr))
+ (setq str (concat " // else: !assert " str ))
+ (throw 'skip 1)))))))))
+
+ (; always, always_comb, always_latch w/o @...
+ (match-end 5)
+ (goto-char (match-end 0))
+ (setq there (point))
+ (setq err nil)
+ (setq str (concat " // " cntx )))
+
+ (;- task/function/initial et cetera
+ t
+ (match-end 0)
+ (goto-char (match-end 0))
+ (setq there (point))
+ (setq err nil)
+ (setq str (concat " // " cntx (verilog-get-expr))))
+
+ (;-- otherwise...
+ (setq str " // auto-endcomment confused "))))
+
+ ((and
+ (verilog-in-case-region-p) ;-- handle case item differently
+ (progn
+ (setq there (point))
+ (goto-char here)
+ (setq str (verilog-backward-case-item lim))))
+ (setq err nil)
+ (setq str (concat " // case: " str )))
+
+ ((verilog-in-fork-region-p)
+ (setq err nil)
+ (setq str " // fork branch" ))
+
+ ((looking-at "\\<end\\>")
+ ;; HERE
+ (forward-word-strictly 1)
+ (verilog-forward-syntactic-ws)
+ (setq err nil)
+ (setq str (verilog-get-expr))
+ (setq str (concat " // " cntx str )))
+
+ ))))
+ (goto-char here)
+ (end-of-line)
+ (if kill-existing-comment
+ (verilog-kill-existing-comment))
+ (delete-horizontal-space)
+ (if (or err
+ (> (count-lines here there) verilog-minimum-comment-distance))
+ (insert str))
+ (if err (ding 't))
+ ))))
+ (;- this is endclass, which can be nested
+ (match-end 11) ; of verilog-end-block-ordered-re
+ ;;(goto-char there)
+ (let ((nest 0)
+ (reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
+ string)
+ (save-excursion
+ (catch 'skip
+ (while (verilog-re-search-backward reg nil 'move)
+ (cond
+ ((match-end 3) ; endclass
+ (ding 't)
+ (setq string "unmatched endclass")
+ (throw 'skip 1))
+
+ ((match-end 2) ; endclass
+ (setq nest (1+ nest)))
+
+ ((match-end 1) ; class
+ (setq nest (1- nest))
+ (if (< nest 0)
+ (progn
+ (goto-char (match-end 0))
+ (let (b e)
+ (setq b (progn
+ (skip-chars-forward "^ \t")
+ (verilog-forward-ws&directives)
+ (point))
+ e (progn
+ (skip-chars-forward "a-zA-Z0-9_")
+ (point)))
+ (setq string (buffer-substring b e)))
+ (throw 'skip 1))))
+ ))))
+ (end-of-line)
+ (if kill-existing-comment
+ (verilog-kill-existing-comment))
+ (delete-horizontal-space)
+ (insert (concat " // " string ))))
+
+ (; - this is end{function,generate,task,module,primitive,table,generate}
+ ;; - which can not be nested.
+ t
+ (let (string reg (name-re nil))
+ (end-of-line)
+ (if kill-existing-comment
+ (save-match-data
+ (verilog-kill-existing-comment)))
+ (delete-horizontal-space)
+ (backward-sexp)
+ (cond
+ ((match-end 5) ; of verilog-end-block-ordered-re
+ (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
+ (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
+ ((match-end 6) ; of verilog-end-block-ordered-re
+ (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
+ (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
+ ((match-end 7) ; of verilog-end-block-ordered-re
+ (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
+ ((match-end 8) ; of verilog-end-block-ordered-re
+ (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
+ ((match-end 9) ; of verilog-end-block-ordered-re
+ (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
+ ((match-end 10) ; of verilog-end-block-ordered-re
+ (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
+ ((match-end 11) ; of verilog-end-block-ordered-re
+ (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
+ ((match-end 12) ; of verilog-end-block-ordered-re
+ (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
+ ((match-end 13) ; of verilog-end-block-ordered-re
+ (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
+ ((match-end 14) ; of verilog-end-block-ordered-re
+ (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
+ ((match-end 15) ; of verilog-end-block-ordered-re
+ (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
+ ((match-end 16) ; of verilog-end-block-ordered-re
+ (setq reg "\\(\\<property\\>\\)\\|\\<endproperty\\>"))
+
+ (t (error "Problem in verilog-set-auto-endcomments")))
+ (let (b e)
+ (save-excursion
+ (verilog-re-search-backward reg nil 'move)
+ (cond
+ ((match-end 1)
+ (setq b (progn
+ (skip-chars-forward "^ \t")
+ (verilog-forward-ws&directives)
+ (if (looking-at "static\\|automatic")
+ (progn
+ (goto-char (match-end 0))
+ (verilog-forward-ws&directives)))
+ (if (and name-re (verilog-re-search-forward name-re nil 'move))
+ (progn
+ (goto-char (match-beginning 0))
+ (verilog-forward-ws&directives)))
+ (point))
+ e (progn
+ (skip-chars-forward "a-zA-Z0-9_")
+ (point)))
+ (setq string (buffer-substring b e)))
+ (t
+ (ding 't)
+ (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
+ (end-of-line)
+ (insert (concat " // " string )))
+ ))))))))))
+
+(defun verilog-get-expr()
+ "Grab expression at point, e.g., case ( a | b & (c ^d))."
+ (let* ((b (progn
+ (verilog-forward-syntactic-ws)
+ (skip-chars-forward " \t")
+ (point)))
+ (e (let ((par 1))
+ (cond
+ ((looking-at "@")
+ (forward-char 1)
+ (verilog-forward-syntactic-ws)
+ (if (looking-at "(")
+ (progn
+ (forward-char 1)
+ (while (and (/= par 0)
+ (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
+ (cond
+ ((match-end 1)
+ (setq par (1+ par)))
+ ((match-end 2)
+ (setq par (1- par)))))))
+ (point))
+ ((looking-at "(")
+ (forward-char 1)
+ (while (and (/= par 0)
+ (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
+ (cond
+ ((match-end 1)
+ (setq par (1+ par)))
+ ((match-end 2)
+ (setq par (1- par)))))
+ (point))
+ ((looking-at "\\[")
+ (forward-char 1)
+ (while (and (/= par 0)
+ (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
+ (cond
+ ((match-end 1)
+ (setq par (1+ par)))
+ ((match-end 2)
+ (setq par (1- par)))))
+ (verilog-forward-syntactic-ws)
+ (skip-chars-forward "^ \t\n\f")
+ (point))
+ ((looking-at "/[/\\*]")
+ b)
+ ('t
+ (skip-chars-forward "^: \t\n\f")
+ (point)))))
+ (str (buffer-substring b e)))
+ (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
+ (setq str (concat (substring str 0 e) "...")))
+ str))
+
+(defun verilog-expand-vector ()
+ "Take a signal vector on the current line and expand it to multiple lines.
+Useful for creating tri's and other expanded fields."
+ (interactive)
+ (verilog-expand-vector-internal "[" "]"))
+
+(defun verilog-expand-vector-internal (bra ket)
+ "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
+ (save-excursion
+ (forward-line 0)
+ (let ((signal-string (buffer-substring (point)
+ (progn
+ (end-of-line) (point)))))
+ (if (string-match
+ (concat "\\(.*\\)"
+ (regexp-quote bra)
+ "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
+ (regexp-quote ket)
+ "\\(.*\\)$") signal-string)
+ (let* ((sig-head (match-string 1 signal-string))
+ (vec-start (string-to-number (match-string 2 signal-string)))
+ (vec-end (if (= (match-beginning 3) (match-end 3))
+ vec-start
+ (string-to-number
+ (substring signal-string (1+ (match-beginning 3))
+ (match-end 3)))))
+ (vec-range
+ (if (= (match-beginning 4) (match-end 4))
+ 1
+ (string-to-number
+ (substring signal-string (+ 2 (match-beginning 4))
+ (match-end 4)))))
+ (sig-tail (match-string 5 signal-string))
+ vec)
+ ;; Decode vectors
+ (setq vec nil)
+ (if (< vec-range 0)
+ (let ((tmp vec-start))
+ (setq vec-start vec-end
+ vec-end tmp
+ vec-range (- vec-range))))
+ (if (< vec-end vec-start)
+ (while (<= vec-end vec-start)
+ (setq vec (append vec (list vec-start)))
+ (setq vec-start (- vec-start vec-range)))
+ (while (<= vec-start vec-end)
+ (setq vec (append vec (list vec-start)))
+ (setq vec-start (+ vec-start vec-range))))
+ ;;
+ ;; Delete current line
+ (delete-region (point) (progn (forward-line 0) (point)))
+ ;;
+ ;; Expand vector
+ (while vec
+ (insert (concat sig-head bra
+ (int-to-string (car vec)) ket sig-tail "\n"))
+ (setq vec (cdr vec)))
+ (delete-char -1)
+ ;;
+ )))))
+
+(defun verilog-strip-comments ()
+ "Strip all comments from the Verilog code."
+ (interactive)
+ (goto-char (point-min))
+ (while (re-search-forward "//" nil t)
+ (if (verilog-within-string)
+ (re-search-forward "\"" nil t)
+ (if (verilog-in-star-comment-p)
+ (re-search-forward "\\*/" nil t)
+ (let ((bpt (- (point) 2)))
+ (end-of-line)
+ (delete-region bpt (point))))))
+ ;;
+ (goto-char (point-min))
+ (while (re-search-forward "/\\*" nil t)
+ (if (verilog-within-string)
+ (re-search-forward "\"" nil t)
+ (let ((bpt (- (point) 2)))
+ (re-search-forward "\\*/")
+ (delete-region bpt (point))))))
+
+(defun verilog-one-line ()
+ "Convert structural Verilog instances to occupy one line."
+ (interactive)
+ (goto-char (point-min))
+ (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
+ (replace-match "\\1 " nil nil)))
+
+(defun verilog-linter-name ()
+ "Return name of linter, either surelint or verilint."
+ (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
+ compile-command))
+ (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
+ verilog-linter)))
+ (cond ((equal compile-word1 "surelint") `surelint)
+ ((equal compile-word1 "verilint") `verilint)
+ ((equal lint-word1 "surelint") `surelint)
+ ((equal lint-word1 "verilint") `verilint)
+ (t `surelint)))) ; back compatibility
+
+(defun verilog-lint-off ()
+ "Convert a Verilog linter warning line into a disable statement.
+For example:
+ pci_bfm_null.v, line 46: Unused input: pci_rst_
+becomes a comment for the appropriate tool.
+
+The first word of the `compile-command' or `verilog-linter'
+variables is used to determine which product is being used.
+
+See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
+ (interactive)
+ (let ((linter (verilog-linter-name)))
+ (cond ((equal linter `surelint)
+ (verilog-surelint-off))
+ ((equal linter `verilint)
+ (verilog-verilint-off))
+ (t (error "Linter name not set")))))
+
+(defvar compilation-last-buffer)
+(defvar next-error-last-buffer)
+
+(defun verilog-surelint-off ()
+ "Convert a SureLint warning line into a disable statement.
+Run from Verilog source window; assumes there is a *compile* buffer
+with point set appropriately.
+
+For example:
+ WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
+becomes:
+ // surefire lint_line_off UDDONX"
+ (interactive)
+ (let ((buff (if (boundp 'next-error-last-buffer)
+ next-error-last-buffer
+ compilation-last-buffer)))
+ (when (buffer-live-p buff)
+ (save-excursion
+ (switch-to-buffer buff)
+ (beginning-of-line)
+ (when
+ (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
+ (let* ((code (match-string 2))
+ (file (match-string 3))
+ (line (match-string 4))
+ (buffer (get-file-buffer file))
+ dir filename)
+ (unless buffer
+ (progn
+ (setq buffer
+ (and (file-exists-p file)
+ (find-file-noselect file)))
+ (or buffer
+ (let* ((pop-up-windows t))
+ (let ((name (expand-file-name
+ (read-file-name
+ (format "Find this error in: (default %s) "
+ file)
+ dir file t))))
+ (if (file-directory-p name)
+ (setq name (expand-file-name filename name)))
+ (setq buffer
+ (and (file-exists-p name)
+ (find-file-noselect name))))))))
+ (switch-to-buffer buffer)
+ (goto-char (point-min))
+ (forward-line (- (string-to-number line)))
+ (end-of-line)
+ (catch 'already
+ (cond
+ ((verilog-in-slash-comment-p)
+ (re-search-backward "//")
+ (cond
+ ((looking-at "// surefire lint_off_line ")
+ (goto-char (match-end 0))
+ (let ((lim (point-at-eol)))
+ (if (re-search-forward code lim 'move)
+ (throw 'already t)
+ (insert (concat " " code)))))
+ (t
+ )))
+ ((verilog-in-star-comment-p)
+ (re-search-backward "/\\*")
+ (insert (format " // surefire lint_off_line %6s" code )))
+ (t
+ (insert (format " // surefire lint_off_line %6s" code ))
+ )))))))))
+
+(defun verilog-verilint-off ()
+ "Convert a Verilint warning line into a disable statement.
+
+For example:
+ (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
+becomes:
+ //Verilint 240 off // WARNING: Unused input"
+ (interactive)
+ (save-excursion
+ (beginning-of-line)
+ (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
+ (replace-match (format
+ ;; %3s makes numbers 1-999 line up nicely
+ "\\1//Verilint %3s off // WARNING: \\3"
+ (match-string 2)))
+ (beginning-of-line)
+ (verilog-indent-line))))
+
+(defun verilog-auto-save-compile ()
+ "Update automatics with \\[verilog-auto], save the buffer, and compile."
+ (interactive)
+ (verilog-auto) ; Always do it for safety
+ (save-buffer)
+ (compile compile-command))
+
+(defun verilog-preprocess (&optional command filename)
+ "Preprocess the buffer, similar to `compile', but put output in Verilog-Mode.
+Takes optional COMMAND or defaults to `verilog-preprocessor', and
+FILENAME to find directory to run in, or defaults to `buffer-file-name'."
+ (interactive
+ (list
+ (let ((default (verilog-expand-command verilog-preprocessor)))
+ (set (make-local-variable `verilog-preprocessor)
+ (read-from-minibuffer "Run Preprocessor (like this): "
+ default nil nil
+ 'verilog-preprocess-history default)))))
+ (unless command (setq command (verilog-expand-command verilog-preprocessor)))
+ (let* ((fontlocked (and (boundp 'font-lock-mode) font-lock-mode))
+ (dir (file-name-directory (or filename buffer-file-name)))
+ (cmd (concat "cd " dir "; " command)))
+ (with-output-to-temp-buffer "*Verilog-Preprocessed*"
+ (with-current-buffer (get-buffer "*Verilog-Preprocessed*")
+ (insert (concat "// " cmd "\n"))
+ (call-process shell-file-name nil t nil shell-command-switch cmd)
+ (verilog-mode)
+ ;; Without this force, it takes a few idle seconds
+ ;; to get the color, which is very jarring
+ (unless (fboundp 'font-lock-ensure)
+ ;; We should use font-lock-ensure in preference to
+ ;; font-lock-fontify-buffer, but IIUC the problem this is supposed to
+ ;; solve only appears in Emacsen older than font-lock-ensure anyway.
+ ;; So avoid bytecomp's interactive-only by going through intern.
+ (when fontlocked (funcall (intern "font-lock-fontify-buffer"))))))))
+
+;;; Batch:
+;;
+
+(defun verilog-warn (string &rest args)
+ "Print a warning with `format' using STRING and optional ARGS."
+ (apply 'message (concat "%%Warning: " string) args))
+
+(defun verilog-warn-error (string &rest args)
+ "Call `error' using STRING and optional ARGS.
+If `verilog-warn-fatal' is non-nil, call `verilog-warn' instead."
+ (if verilog-warn-fatal
+ (apply 'error string args)
+ (apply 'verilog-warn string args)))
+
+(defmacro verilog-batch-error-wrapper (&rest body)
+ "Execute BODY and add error prefix to any errors found.
+This lets programs calling batch mode to easily extract error messages."
+ `(let ((verilog-warn-fatal nil))
+ (condition-case err
+ (progn ,@body)
+ (error
+ (error "%%Error: %s%s" (error-message-string err)
+ (if (featurep 'xemacs) "\n" "")))))) ; XEmacs forgets to add a newline
+
+(defun verilog-batch-execute-func (funref &optional no-save)
+ "Internal processing of a batch command.
+Runs FUNREF on all command arguments.
+Save the result unless optional NO-SAVE is t."
+ (verilog-batch-error-wrapper
+ ;; Setting global variables like that is *VERY NASTY* !!! --Stef
+ ;; However, this function is called only when Emacs is being used as
+ ;; a standalone language instead of as an editor, so we'll live.
+ ;;
+ ;; General globals needed
+ (setq make-backup-files nil)
+ (setq-default make-backup-files nil)
+ (setq enable-local-variables t)
+ (setq enable-local-eval t)
+ (setq create-lockfiles nil)
+ ;; Make sure any sub-files we read get proper mode
+ (setq-default major-mode 'verilog-mode)
+ ;; Ditto files already read in
+ ;; Remember buffer list, so don't later pickup any verilog-getopt files
+ (let ((orig-buffer-list (buffer-list)))
+ (mapc (lambda (buf)
+ (when (buffer-file-name buf)
+ (with-current-buffer buf
+ (verilog-mode)
+ (verilog-auto-reeval-locals)
+ (verilog-getopt-flags))))
+ orig-buffer-list)
+ ;; Process the files
+ (mapcar (lambda (buf)
+ (when (buffer-file-name buf)
+ (save-excursion
+ (if (not (file-exists-p (buffer-file-name buf)))
+ (error
+ "File not found: %s" (buffer-file-name buf)))
+ (message "Processing %s" (buffer-file-name buf))
+ (set-buffer buf)
+ (funcall funref)
+ (when (and (not no-save)
+ (buffer-modified-p)) ; Avoid "no changes to be saved"
+ (save-buffer)))))
+ orig-buffer-list))))
+
+(defun verilog-batch-auto ()
+ "For use with --batch, perform automatic expansions as a stand-alone tool.
+This sets up the appropriate Verilog mode environment, updates automatics
+with \\[verilog-auto] on all command-line files, and saves the buffers.
+For proper results, multiple filenames need to be passed on the command
+line in bottom-up order."
+ (unless noninteractive
+ (error "Use verilog-batch-auto only with --batch")) ; Otherwise we'd mess up buffer modes
+ (verilog-batch-execute-func `verilog-auto))
+
+(defun verilog-batch-delete-auto ()
+ "For use with --batch, perform automatic deletion as a stand-alone tool.
+This sets up the appropriate Verilog mode environment, deletes automatics
+with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
+ (unless noninteractive
+ (error "Use verilog-batch-delete-auto only with --batch")) ; Otherwise we'd mess up buffer modes
+ (verilog-batch-execute-func `verilog-delete-auto))
+
+(defun verilog-batch-delete-trailing-whitespace ()
+ "For use with --batch, perform whitespace deletion as a stand-alone tool.
+This sets up the appropriate Verilog mode environment, removes
+whitespace with \\[verilog-delete-trailing-whitespace] on all
+command-line files, and saves the buffers."
+ (unless noninteractive
+ (error "Use verilog-batch-delete-trailing-whitespace only with --batch")) ; Otherwise we'd mess up buffer modes
+ (verilog-batch-execute-func `verilog-delete-trailing-whitespace))
+
+(defun verilog-batch-diff-auto ()
+ "For use with --batch, perform automatic differences as a stand-alone tool.
+This sets up the appropriate Verilog mode environment, expand automatics
+with \\[verilog-diff-auto] on all command-line files, and reports an error
+if any differences are observed. This is appropriate for adding to regressions
+to insure automatics are always properly maintained."
+ (unless noninteractive
+ (error "Use verilog-batch-diff-auto only with --batch")) ; Otherwise we'd mess up buffer modes
+ (verilog-batch-execute-func `verilog-diff-auto t))
+
+(defun verilog-batch-inject-auto ()
+ "For use with --batch, perform automatic injection as a stand-alone tool.
+This sets up the appropriate Verilog mode environment, injects new automatics
+with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
+For proper results, multiple filenames need to be passed on the command
+line in bottom-up order."
+ (unless noninteractive
+ (error "Use verilog-batch-inject-auto only with --batch")) ; Otherwise we'd mess up buffer modes
+ (verilog-batch-execute-func `verilog-inject-auto))
+
+(defun verilog-batch-indent ()
+ "For use with --batch, reindent an entire file as a stand-alone tool.
+This sets up the appropriate Verilog mode environment, calls
+\\[verilog-indent-buffer] on all command-line files, and saves the buffers."
+ (unless noninteractive
+ (error "Use verilog-batch-indent only with --batch")) ; Otherwise we'd mess up buffer modes
+ (verilog-batch-execute-func `verilog-indent-buffer))
+
+;;; Indentation:
+;;
+(defconst verilog-indent-alist
+ '((block . (+ ind verilog-indent-level))
+ (case . (+ ind verilog-case-indent))
+ (cparenexp . (+ ind verilog-indent-level))
+ (cexp . (+ ind verilog-cexp-indent))
+ (defun . verilog-indent-level-module)
+ (declaration . verilog-indent-level-declaration)
+ (directive . (verilog-calculate-indent-directive))
+ (tf . verilog-indent-level)
+ (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
+ (statement . ind)
+ (cpp . 0)
+ (comment . (verilog-comment-indent))
+ (unknown . 3)
+ (string . 0)))
+
+(defun verilog-continued-line-1 (lim)
+ "Return true if this is a continued line.
+Set point to where line starts. Limit search to point LIM."
+ (let ((continued 't))
+ (if (eq 0 (forward-line -1))
+ (progn
+ (end-of-line)
+ (verilog-backward-ws&directives lim)
+ (if (bobp)
+ (setq continued nil)
+ (setq continued (verilog-backward-token))))
+ (setq continued nil))
+ continued))
+
+(defun verilog-calculate-indent ()
+ "Calculate the indent of the current Verilog line.
+Examine previous lines. Once a line is found that is definitive as to the
+type of the current line, return that lines' indent level and its type.
+Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
+ (save-excursion
+ (let* ((starting_position (point))
+ (case-fold-search nil)
+ (par 0)
+ (begin (looking-at "[ \t]*begin\\>"))
+ (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
+ (structres nil)
+ (type (catch 'nesting
+ ;; Keep working backwards until we can figure out
+ ;; what type of statement this is.
+ ;; Basically we need to figure out
+ ;; 1) if this is a continuation of the previous line;
+ ;; 2) are we in a block scope (begin..end)
+
+ ;; if we are in a comment, done.
+ (if (verilog-in-star-comment-p)
+ (throw 'nesting 'comment))
+
+ ;; if we have a directive, done.
+ (if (save-excursion (beginning-of-line)
+ (and (looking-at verilog-directive-re-1)
+ (not (or (looking-at "[ \t]*`[ou]vm_")
+ (looking-at "[ \t]*`vmm_")))))
+ (throw 'nesting 'directive))
+ ;; indent structs as if there were module level
+ (setq structres (verilog-in-struct-nested-p))
+ (cond ((not structres) nil)
+ ;;((and structres (equal (char-after) ?\})) (throw 'nesting 'struct-close))
+ ((> structres 0) (throw 'nesting 'nested-struct))
+ ((= structres 0) (throw 'nesting 'block))
+ (t nil))
+
+ ;; if we are in a parenthesized list, and the user likes to indent these, return.
+ ;; unless we are in the newfangled coverpoint or constraint blocks
+ (if (and
+ verilog-indent-lists
+ (verilog-in-paren)
+ (not (verilog-in-coverage-p))
+ )
+ (progn (setq par 1)
+ (throw 'nesting 'block)))
+
+ ;; See if we are continuing a previous line
+ (while t
+ ;; trap out if we crawl off the top of the buffer
+ (if (bobp) (throw 'nesting 'cpp))
+
+ (if (and (verilog-continued-line-1 lim)
+ (or (not (verilog-in-coverage-p))
+ (looking-at verilog-in-constraint-re) )) ; may still get hosed if concat in constraint
+ (let ((sp (point)))
+ (if (and
+ (not (looking-at verilog-complete-reg))
+ (verilog-continued-line-1 lim))
+ (progn (goto-char sp)
+ (throw 'nesting 'cexp))
+
+ (goto-char sp))
+ (if (and (verilog-in-coverage-p)
+ (looking-at verilog-in-constraint-re))
+ (progn
+ (beginning-of-line)
+ (skip-chars-forward " \t")
+ (throw 'nesting 'constraint)))
+ (if (and begin
+ (not verilog-indent-begin-after-if)
+ (looking-at verilog-no-indent-begin-re))
+ (progn
+ (beginning-of-line)
+ (skip-chars-forward " \t")
+ (throw 'nesting 'statement))
+ (progn
+ (throw 'nesting 'cexp))))
+ ;; not a continued line
+ (goto-char starting_position))
+
+ (if (looking-at "\\<else\\>")
+ ;; search back for governing if, striding across begin..end pairs
+ ;; appropriately
+ (let ((elsec 1))
+ (while (verilog-re-search-backward verilog-ends-re nil 'move)
+ (cond
+ ((match-end 1) ; else, we're in deep
+ (setq elsec (1+ elsec)))
+ ((match-end 2) ; if
+ (setq elsec (1- elsec))
+ (if (= 0 elsec)
+ (if verilog-align-ifelse
+ (throw 'nesting 'statement)
+ (progn ; back up to first word on this line
+ (beginning-of-line)
+ (verilog-forward-syntactic-ws)
+ (throw 'nesting 'statement)))))
+ ((match-end 3) ; assert block
+ (setq elsec (1- elsec))
+ (verilog-beg-of-statement) ; doesn't get to beginning
+ (if (looking-at verilog-property-re)
+ (throw 'nesting 'statement) ; We don't need an endproperty for these
+ (throw 'nesting 'block) ; We still need an endproperty
+ ))
+ (t ; endblock
+ ;; try to leap back to matching outward block by striding across
+ ;; indent level changing tokens then immediately
+ ;; previous line governs indentation.
+ (let (( reg) (nest 1))
+ ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
+ (cond
+ ((match-end 4) ; end
+ ;; Search back for matching begin
+ (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
+ ((match-end 5) ; endcase
+ ;; Search back for matching case
+ (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
+ ((match-end 6) ; endfunction
+ ;; Search back for matching function
+ (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
+ ((match-end 7) ; endtask
+ ;; Search back for matching task
+ (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
+ ((match-end 8) ; endspecify
+ ;; Search back for matching specify
+ (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
+ ((match-end 9) ; endtable
+ ;; Search back for matching table
+ (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
+ ((match-end 10) ; endgenerate
+ ;; Search back for matching generate
+ (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
+ ((match-end 11) ; joins
+ ;; Search back for matching fork
+ (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
+ ((match-end 12) ; class
+ ;; Search back for matching class
+ (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
+ ((match-end 13) ; covergroup
+ ;; Search back for matching covergroup
+ (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
+ (catch 'skip
+ (while (verilog-re-search-backward reg nil 'move)
+ (cond
+ ((match-end 1) ; begin
+ (setq nest (1- nest))
+ (if (= 0 nest)
+ (throw 'skip 1)))
+ ((match-end 2) ; end
+ (setq nest (1+ nest)))))
+ )))))))
+ (throw 'nesting (verilog-calc-1)))
+ ) ; catch nesting
+ ) ; type
+ )
+ ;; Return type of block and indent level.
+ (if (not type)
+ (setq type 'cpp))
+ (if (> par 0) ; Unclosed Parenthesis
+ (list 'cparenexp par)
+ (cond
+ ((eq type 'case)
+ (list type (verilog-case-indent-level)))
+ ((eq type 'statement)
+ (list type (current-column)))
+ ((eq type 'defun)
+ (list type 0))
+ ((eq type 'constraint)
+ (list 'block (current-column)))
+ ((eq type 'nested-struct)
+ (list 'block structres))
+ (t
+ (list type (verilog-current-indent-level))))))))
+
+(defun verilog-wai ()
+ "Show matching nesting block for debugging."
+ (interactive)
+ (save-excursion
+ (let* ((type (verilog-calc-1))
+ depth)
+ ;; Return type of block and indent level.
+ (if (not type)
+ (setq type 'cpp))
+ (if (and
+ verilog-indent-lists
+ (not(or (verilog-in-coverage-p)
+ (verilog-in-struct-p)))
+ (verilog-in-paren))
+ (setq depth 1)
+ (cond
+ ((eq type 'case)
+ (setq depth (verilog-case-indent-level)))
+ ((eq type 'statement)
+ (setq depth (current-column)))
+ ((eq type 'defun)
+ (setq depth 0))
+ (t
+ (setq depth (verilog-current-indent-level)))))
+ (message "You are at nesting %s depth %d" type depth))))
+
+(defun verilog-calc-1 ()
+ (catch 'nesting
+ (let ((re (concat "\\({\\|}\\|" verilog-indent-re "\\)"))
+ (inconstraint (verilog-in-coverage-p)))
+ (while (verilog-re-search-backward re nil 'move)
+ (catch 'continue
+ (cond
+ ((equal (char-after) ?\{)
+ ;; block type returned based on outer constraint { or inner
+ (if (verilog-at-constraint-p)
+ (cond (inconstraint
+ (beginning-of-line nil)
+ (skip-chars-forward " \t")
+ (throw 'nesting 'constraint))
+ (t
+ (throw 'nesting 'statement)))))
+ ((equal (char-after) ?\})
+ (let (par-pos
+ (there (verilog-at-close-constraint-p)))
+ (if there ; we are at the } that closes a constraint. Find the { that opens it
+ (progn
+ (if (> (verilog-in-paren-count) 0)
+ (forward-char 1))
+ (setq par-pos (verilog-parenthesis-depth))
+ (cond (par-pos
+ (goto-char par-pos)
+ (forward-char 1))
+ (t
+ (backward-char 1)))))))
+
+ ((looking-at verilog-beg-block-re-ordered)
+ (cond
+ ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
+ (let ((here (point)))
+ (verilog-beg-of-statement)
+ (if (looking-at verilog-extended-case-re)
+ (throw 'nesting 'case)
+ (goto-char here)))
+ (throw 'nesting 'case))
+
+ ((match-end 4) ; *sigh* could be "disable fork"
+ (let ((here (point)))
+ (verilog-beg-of-statement)
+ (if (looking-at verilog-disable-fork-re)
+ t ; this is a normal statement
+ (progn ; or is fork, starts a new block
+ (goto-char here)
+ (throw 'nesting 'block)))))
+
+ ((match-end 17) ; *sigh* might be a clocking declaration
+ (let ((here (point)))
+ (cond ((verilog-in-paren)
+ t) ; this is a normal statement
+ ((save-excursion
+ (verilog-beg-of-statement)
+ (looking-at verilog-default-clocking-re))
+ t) ; default clocking, normal statement
+ (t
+ (goto-char here) ; or is clocking, starts a new block
+ (throw 'nesting 'block)))))
+
+ ;; need to consider typedef struct here...
+ ((looking-at "\\<class\\|struct\\|function\\|task\\>")
+ ;; *sigh* These words have an optional prefix:
+ ;; extern {virtual|protected}? function a();
+ ;; typedef class foo;
+ ;; and we don't want to confuse this with
+ ;; function a();
+ ;; property
+ ;; ...
+ ;; endfunction
+ (verilog-beg-of-statement)
+ (cond
+ ((looking-at verilog-dpi-import-export-re)
+ (throw 'continue 'foo))
+ ((looking-at "\\<pure\\>\\s-+\\<virtual\\>\\s-+\\(?:\\<\\(local\\|protected\\|static\\)\\>\\s-+\\)?\\<\\(function\\|task\\)\\>\\s-+")
+ (throw 'nesting 'statement))
+ ((looking-at verilog-beg-block-re-ordered)
+ (throw 'nesting 'block))
+ (t
+ (throw 'nesting 'defun))))
+
+ ;;
+ ((looking-at "\\<property\\>")
+ ;; *sigh*
+ ;; {assert|assume|cover} property (); are complete
+ ;; and could also be labeled: - foo: assert property
+ ;; but
+ ;; property ID () ... needs end_property
+ (verilog-beg-of-statement)
+ (if (looking-at verilog-property-re)
+ (throw 'continue 'statement) ; We don't need an endproperty for these
+ (throw 'nesting 'block) ;We still need an endproperty
+ ))
+
+ (t (throw 'nesting 'block))))
+
+ ((looking-at verilog-end-block-re)
+ (verilog-leap-to-head)
+ (if (verilog-in-case-region-p)
+ (progn
+ (verilog-leap-to-case-head)
+ (if (looking-at verilog-extended-case-re)
+ (throw 'nesting 'case)))))
+
+ ((looking-at verilog-defun-level-re)
+ (if (looking-at verilog-defun-level-generate-only-re)
+ (if (or (verilog-in-generate-region-p)
+ (verilog-in-deferred-immediate-final-p))
+ (throw 'continue 'foo) ; always block in a generate - keep looking
+ (throw 'nesting 'defun))
+ (throw 'nesting 'defun)))
+
+ ((looking-at verilog-cpp-level-re)
+ (throw 'nesting 'cpp))
+
+ ((bobp)
+ (throw 'nesting 'cpp)))))
+
+ (throw 'nesting 'cpp))))
+
+(defun verilog-calculate-indent-directive ()
+ "Return indentation level for directive.
+For speed, the searcher looks at the last directive, not the indent
+of the appropriate enclosing block."
+ (let ((base -1) ; Indent of the line that determines our indentation
+ (ind 0)) ; Relative offset caused by other directives (like `endif on same line as `else)
+ ;; Start at current location, scan back for another directive
+
+ (save-excursion
+ (beginning-of-line)
+ (while (and (< base 0)
+ (verilog-re-search-backward verilog-directive-re nil t))
+ (cond ((save-excursion (skip-chars-backward " \t") (bolp))
+ (setq base (current-indentation))))
+ (cond ((and (looking-at verilog-directive-end) (< base 0)) ; Only matters when not at BOL
+ (setq ind (- ind verilog-indent-level-directive)))
+ ((and (looking-at verilog-directive-middle) (>= base 0)) ; Only matters when at BOL
+ (setq ind (+ ind verilog-indent-level-directive)))
+ ((looking-at verilog-directive-begin)
+ (setq ind (+ ind verilog-indent-level-directive)))))
+ ;; Adjust indent to starting indent of critical line
+ (setq ind (max 0 (+ ind base))))
+
+ (save-excursion
+ (beginning-of-line)
+ (skip-chars-forward " \t")
+ (cond ((or (looking-at verilog-directive-middle)
+ (looking-at verilog-directive-end))
+ (setq ind (max 0 (- ind verilog-indent-level-directive))))))
+ ind))
+
+(defun verilog-leap-to-case-head ()
+ (let ((nest 1))
+ (while (/= 0 nest)
+ (verilog-re-search-backward
+ (concat
+ "\\(\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\\)?\\<case[xz]?\\>\\)"
+ "\\|\\(\\<endcase\\>\\)" )
+ nil 'move)
+ (cond
+ ((match-end 1)
+ (let ((here (point)))
+ (verilog-beg-of-statement)
+ (unless (looking-at verilog-extended-case-re)
+ (goto-char here)))
+ (setq nest (1- nest)))
+ ((match-end 3)
+ (setq nest (1+ nest)))
+ ((bobp)
+ (ding 't)
+ (setq nest 0))))))
+
+(defun verilog-leap-to-head ()
+ "Move point to the head of this block.
+Jump from end to matching begin, from endcase to matching case, and so on."
+ (let ((reg nil)
+ snest
+ (nesting 'yes)
+ (nest 1))
+ (cond
+ ((looking-at "\\<end\\>")
+ ;; 1: Search back for matching begin
+ (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
+ "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
+ ((looking-at "\\<endtask\\>")
+ ;; 2: Search back for matching task
+ (setq reg "\\(\\<task\\>\\)\\|\\(\\(\\<\\(virtual\\|protected\\|static\\)\\>\\s-+\\)+\\<task\\>\\)")
+ (setq nesting 'no))
+ ((looking-at "\\<endcase\\>")
+ (catch 'nesting
+ (verilog-leap-to-case-head) )
+ (setq reg nil) ; to force skip
+ )
+
+ ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
+ ;; 4: Search back for matching fork
+ (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
+ ((looking-at "\\<endclass\\>")
+ ;; 5: Search back for matching class
+ (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
+ ((looking-at "\\<endtable\\>")
+ ;; 6: Search back for matching table
+ (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
+ ((looking-at "\\<endspecify\\>")
+ ;; 7: Search back for matching specify
+ (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
+ ((looking-at "\\<endfunction\\>")
+ ;; 8: Search back for matching function
+ (setq reg "\\(\\<function\\>\\)\\|\\(\\(\\<\\(virtual\\|protected\\|static\\)\\>\\s-+\\)+\\<function\\>\\)")
+ (setq nesting 'no))
+ ;;(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
+ ((looking-at "\\<endgenerate\\>")
+ ;; 8: Search back for matching generate
+ (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
+ ((looking-at "\\<endgroup\\>")
+ ;; 10: Search back for matching covergroup
+ (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
+ ((looking-at "\\<endproperty\\>")
+ ;; 11: Search back for matching property
+ (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
+ ((looking-at verilog-uvm-end-re)
+ ;; 12: Search back for matching sequence
+ (setq reg (concat "\\(" verilog-uvm-begin-re "\\|" verilog-uvm-end-re "\\)")))
+ ((looking-at verilog-ovm-end-re)
+ ;; 12: Search back for matching sequence
+ (setq reg (concat "\\(" verilog-ovm-begin-re "\\|" verilog-ovm-end-re "\\)")))
+ ((looking-at verilog-vmm-end-re)
+ ;; 12: Search back for matching sequence
+ (setq reg (concat "\\(" verilog-vmm-begin-re "\\|" verilog-vmm-end-re "\\)")))
+ ((looking-at "\\<endinterface\\>")
+ ;; 12: Search back for matching interface
+ (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
+ ((looking-at "\\<endsequence\\>")
+ ;; 12: Search back for matching sequence
+ (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
+ ((looking-at "\\<endclocking\\>")
+ ;; 12: Search back for matching clocking
+ (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" )))
+ (if reg
+ (catch 'skip
+ (if (eq nesting 'yes)
+ (let (sreg)
+ (while (verilog-re-search-backward reg nil 'move)
+ (cond
+ ((match-end 1) ; begin
+ (if (looking-at "fork")
+ (let ((here (point)))
+ (verilog-beg-of-statement)
+ (unless (looking-at verilog-disable-fork-re)
+ (goto-char here)
+ (setq nest (1- nest))))
+ (setq nest (1- nest)))
+ (if (= 0 nest)
+ ;; Now previous line describes syntax
+ (throw 'skip 1))
+ (if (and snest
+ (= snest nest))
+ (setq reg sreg)))
+ ((match-end 2) ; end
+ (setq nest (1+ nest)))
+ ((match-end 3)
+ ;; endcase, jump to case
+ (setq snest nest)
+ (setq nest (1+ nest))
+ (setq sreg reg)
+ (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
+ ((match-end 4)
+ ;; join, jump to fork
+ (setq snest nest)
+ (setq nest (1+ nest))
+ (setq sreg reg)
+ (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
+ )))
+ ;; no nesting
+ (if (and
+ (verilog-re-search-backward reg nil 'move)
+ (match-end 1)) ; task -> could be virtual and/or protected
+ (progn
+ (verilog-beg-of-statement)
+ (throw 'skip 1))
+ (throw 'skip 1)))))))
+
+(defun verilog-continued-line ()
+ "Return true if this is a continued line.
+Set point to where line starts."
+ (let ((continued 't))
+ (if (eq 0 (forward-line -1))
+ (progn
+ (end-of-line)
+ (verilog-backward-ws&directives)
+ (if (bobp)
+ (setq continued nil)
+ (while (and continued
+ (save-excursion
+ (skip-chars-backward " \t")
+ (not (bolp))))
+ (setq continued (verilog-backward-token)))))
+ (setq continued nil))
+ continued))
+
+(defun verilog-backward-token ()
+ "Step backward token, returning true if this is a continued line."
+ (interactive)
+ (verilog-backward-syntactic-ws)
+ (cond
+ ((bolp)
+ nil)
+ (;-- Anything ending in a ; is complete
+ (= (preceding-char) ?\;)
+ nil)
+ (; If a "}" is prefixed by a ";", then this is a complete statement
+ ;; i.e.: constraint foo { a = b; }
+ (= (preceding-char) ?\})
+ (progn
+ (backward-char)
+ (not(verilog-at-close-constraint-p))))
+ (;-- constraint foo { a = b }
+ ;; is a complete statement. *sigh*
+ (= (preceding-char) ?\{)
+ (progn
+ (backward-char)
+ (not (verilog-at-constraint-p))))
+ (;" string "
+ (= (preceding-char) ?\")
+ (backward-char)
+ (verilog-skip-backward-comment-or-string)
+ nil)
+
+ (; [3:4]
+ (= (preceding-char) ?\])
+ (backward-char)
+ (verilog-backward-open-bracket)
+ t)
+
+ (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
+ ;; also could be simply '@(foo)'
+ ;; or foo u1 #(a=8)
+ ;; (b, ... which ISN'T complete
+ ;; Do we need this???
+ (= (preceding-char) ?\))
+ (progn
+ (backward-char)
+ (verilog-backward-up-list 1)
+ (verilog-backward-syntactic-ws)
+ (let ((back (point)))
+ (forward-word-strictly -1)
+ (cond
+ ;;XX
+ ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
+ (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
+ ((looking-at verilog-uvm-statement-re)
+ nil)
+ ((looking-at verilog-uvm-begin-re)
+ t)
+ ((looking-at verilog-uvm-end-re)
+ t)
+ ((looking-at verilog-ovm-statement-re)
+ nil)
+ ((looking-at verilog-ovm-begin-re)
+ t)
+ ((looking-at verilog-ovm-end-re)
+ t)
+ ;; JBA find VMM macros
+ ((looking-at verilog-vmm-statement-re)
+ nil )
+ ((looking-at verilog-vmm-begin-re)
+ t)
+ ((looking-at verilog-vmm-end-re)
+ nil)
+ ;; JBA trying to catch macro lines with no ; at end
+ ((looking-at "\\<`")
+ nil)
+ (t
+ (goto-char back)
+ (cond
+ ((= (preceding-char) ?\@)
+ (backward-char)
+ (save-excursion
+ (verilog-backward-token)
+ (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
+ ((= (preceding-char) ?\#)
+ (backward-char))
+ (t t)))))))
+
+ (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
+ t
+ (forward-word-strictly -1)
+ (while (or (= (preceding-char) ?\_)
+ (= (preceding-char) ?\@)
+ (= (preceding-char) ?\.))
+ (forward-word-strictly -1))
+ (cond
+ ((looking-at "\\<else\\>")
+ t)
+ ((looking-at verilog-behavioral-block-beg-re)
+ t)
+ ((looking-at verilog-indent-re)
+ nil)
+ (t
+ (let
+ ((back (point)))
+ (verilog-backward-syntactic-ws)
+ (cond
+ ((= (preceding-char) ?\:)
+ (backward-char)
+ (verilog-backward-syntactic-ws)
+ (backward-sexp)
+ (if (looking-at verilog-nameable-item-re )
+ nil
+ t))
+ ((= (preceding-char) ?\#)
+ (backward-char)
+ t)
+ ((= (preceding-char) ?\`)
+ (backward-char)
+ t)
+
+ (t
+ (goto-char back)
+ t))))))))
+
+(defun verilog-backward-syntactic-ws ()
+ "Move backwards putting point after first non-whitespace non-comment."
+ (verilog-skip-backward-comments)
+ (forward-comment (- (buffer-size))))
+
+(defun verilog-backward-syntactic-ws-quick ()
+ "As with `verilog-backward-syntactic-ws' but use `verilog-scan' cache."
+ (while (cond ((bobp)
+ nil) ; Done
+ ((< (skip-syntax-backward " ") 0)
+ t)
+ ((eq (preceding-char) ?\n) ; \n's terminate // so aren't space syntax
+ (forward-char -1)
+ t)
+ ((or (verilog-inside-comment-or-string-p (1- (point)))
+ (verilog-inside-comment-or-string-p (point)))
+ (re-search-backward "[/\"]" nil t) ; Only way a comment or quote can begin
+ t))))
+
+(defun verilog-forward-syntactic-ws ()
+ (verilog-skip-forward-comment-p)
+ (forward-comment (buffer-size)))
+
+(defun verilog-backward-ws&directives (&optional bound)
+ "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
+Optional BOUND limits search."
+ (save-restriction
+ (let* ((bound (or bound (point-min)))
+ (here bound)
+ (p nil) )
+ (if (< bound (point))
+ (progn
+ (let ((state (save-excursion (verilog-syntax-ppss))))
+ (cond
+ ((nth 7 state) ; in // comment
+ (verilog-re-search-backward "//" nil 'move)
+ (skip-chars-backward "/"))
+ ((nth 4 state) ; in /* */ comment
+ (verilog-re-search-backward "/\\*" nil 'move))))
+ (narrow-to-region bound (point))
+ (while (/= here (point))
+ (setq here (point))
+ (verilog-skip-backward-comments)
+ (setq p
+ (save-excursion
+ (beginning-of-line)
+ ;; for as long as we're right after a continued line, keep moving up
+ (while (and (verilog-looking-back "\\\\[\n\r\f]" nil)
+ (forward-line -1)))
+ (cond
+ ((and verilog-highlight-translate-off
+ (verilog-within-translate-off))
+ (verilog-back-to-start-translate-off (point-min)))
+ ((looking-at verilog-directive-re-1)
+ (point))
+ (t
+ nil))))
+ (if p (goto-char p))))))))
+
+(defun verilog-forward-ws&directives (&optional bound)
+ "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
+Optional BOUND limits search."
+ (save-restriction
+ (let* ((bound (or bound (point-max)))
+ (here bound)
+ jump)
+ (if (> bound (point))
+ (progn
+ (let ((state (save-excursion (verilog-syntax-ppss))))
+ (cond
+ ((nth 7 state) ; in // comment
+ (end-of-line)
+ (forward-char 1)
+ (skip-chars-forward " \t\n\f")
+ )
+ ((nth 4 state) ; in /* */ comment
+ (verilog-re-search-forward "\\*/\\s-*" nil 'move))))
+ (narrow-to-region (point) bound)
+ (while (/= here (point))
+ (setq here (point)
+ jump nil)
+ (forward-comment (buffer-size))
+ (and (looking-at "\\s-*(\\*.*\\*)\\s-*") ; Attribute
+ (goto-char (match-end 0)))
+ (save-excursion
+ (beginning-of-line)
+ (if (looking-at verilog-directive-re-1)
+ (setq jump t)))
+ (if jump
+ (beginning-of-line 2))))))))
+
+(defun verilog-in-comment-p ()
+ "Return true if in a star or // comment."
+ (let ((state (save-excursion (verilog-syntax-ppss))))
+ (or (nth 4 state) (nth 7 state))))
+
+(defun verilog-in-star-comment-p ()
+ "Return true if in a star comment."
+ (let ((state (save-excursion (verilog-syntax-ppss))))
+ (and
+ (nth 4 state) ; t if in a comment of style a // or b /**/
+ (not
+ (nth 7 state) ; t if in a comment of style b /**/
+ ))))
+
+(defun verilog-in-slash-comment-p ()
+ "Return true if in a slash comment."
+ (let ((state (save-excursion (verilog-syntax-ppss))))
+ (nth 7 state)))
+
+(defun verilog-in-comment-or-string-p ()
+ "Return true if in a string or comment."
+ (let ((state (save-excursion (verilog-syntax-ppss))))
+ (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
+
+(defun verilog-in-attribute-p ()
+ "Return true if point is in an attribute (* [] attribute *)."
+ (save-match-data
+ (save-excursion
+ (verilog-re-search-backward "\\((\\*\\)\\|\\(\\*)\\)" nil 'move)
+ (cond
+ ((match-end 1)
+ (progn (goto-char (match-end 1))
+ (not (looking-at "\\s-*)")))
+ nil)
+ ((match-end 2)
+ (progn (goto-char (match-beginning 2))
+ (not (looking-at "(\\s-*")))
+ nil)
+ (t nil)))))
+
+(defun verilog-in-parameter-p ()
+ "Return true if point is in a parameter assignment #( p1=1, p2=5)."
+ (save-match-data
+ (save-excursion
+ (verilog-re-search-backward "\\(#(\\)\\|\\()\\)" nil 'move)
+ (numberp (match-beginning 1)))))
+
+(defun verilog-in-escaped-name-p ()
+ "Return true if in an escaped name."
+ (save-excursion
+ (backward-char)
+ (skip-chars-backward "^ \t\n\f")
+ (if (equal (char-after (point) ) ?\\ )
+ t
+ nil)))
+
+(defun verilog-in-directive-p ()
+ "Return true if in a directive."
+ (save-excursion
+ (beginning-of-line)
+ (looking-at verilog-directive-re-1)))
+
+(defun verilog-in-parenthesis-p ()
+ "Return true if in a ( ) expression (but not { } or [ ])."
+ (save-match-data
+ (save-excursion
+ (verilog-re-search-backward "\\((\\)\\|\\()\\)" nil 'move)
+ (numberp (match-beginning 1)))))
+
+(defun verilog-in-paren ()
+ "Return true if in a parenthetical expression.
+May cache result using `verilog-syntax-ppss'."
+ (let ((state (save-excursion (verilog-syntax-ppss))))
+ (> (nth 0 state) 0 )))
+
+(defun verilog-in-paren-count ()
+ "Return paren depth, floor to 0.
+May cache result using `verilog-syntax-ppss'."
+ (let ((state (save-excursion (verilog-syntax-ppss))))
+ (if (> (nth 0 state) 0)
+ (nth 0 state)
+ 0 )))
+
+(defun verilog-in-paren-quick ()
+ "Return true if in a parenthetical expression.
+Always starts from `point-min', to allow inserts with hooks disabled."
+ ;; The -quick refers to its use alongside the other -quick functions,
+ ;; not that it's likely to be faster than verilog-in-paren.
+ (let ((state (save-excursion (parse-partial-sexp (point-min) (point)))))
+ (> (nth 0 state) 0 )))
+
+(defun verilog-in-struct-p ()
+ "Return true if in a struct declaration."
+ (interactive)
+ (save-excursion
+ (if (verilog-in-paren)
+ (progn
+ (verilog-backward-up-list 1)
+ (verilog-at-struct-p)
+ )
+ nil)))
+
+(defun verilog-in-struct-nested-p ()
+ "Return nil for not in struct.
+Return 0 for in non-nested struct.
+Return >0 for nested struct."
+ (interactive)
+ (let (col)
+ (save-excursion
+ (if (verilog-in-paren)
+ (progn
+ (verilog-backward-up-list 1)
+ (setq col (verilog-at-struct-mv-p))
+ (if col
+ (if (verilog-in-struct-p) (current-column) 0)))
+ nil))))
+
+(defun verilog-in-coverage-p ()
+ "Return true if in a constraint or coverpoint expression."
+ (interactive)
+ (save-excursion
+ (if (verilog-in-paren)
+ (progn
+ (verilog-backward-up-list 1)
+ (verilog-at-constraint-p)
+ )
+ nil)))
+
+(defun verilog-at-close-constraint-p ()
+ "If at the } that closes a constraint or covergroup, return true."
+ (if (and
+ (equal (char-after) ?\})
+ (verilog-in-coverage-p))
+
+ (save-excursion
+ (verilog-backward-ws&directives)
+ (if (or (equal (char-before) ?\;)
+ (equal (char-before) ?\}) ; can end with inner constraint { } block or ;
+ (equal (char-before) ?\{)) ; empty constraint block
+ (point)
+ nil))))
+
+(defun verilog-at-constraint-p ()
+ "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
+ (if (save-excursion
+ (let ((p (point)))
+ (and
+ (equal (char-after) ?\{)
+ (ignore-errors (forward-list))
+ (progn (backward-char 1)
+ (verilog-backward-ws&directives)
+ (and
+ (or (equal (char-before) ?\{) ; empty case
+ (equal (char-before) ?\;)
+ (equal (char-before) ?\}))
+ ;; skip what looks like bus repetition operator {#{
+ (not (string-match "^{\\s-*[0-9]+\\s-*{" (buffer-substring p (point)))))))))
+ (progn
+ (let ( (pt (point)) (pass 0))
+ (verilog-backward-ws&directives)
+ (verilog-backward-token)
+ (if (looking-at (concat "\\<constraint\\|coverpoint\\|cross\\|with\\>\\|" verilog-in-constraint-re))
+ (progn (setq pass 1)
+ (if (looking-at "\\<with\\>")
+ (progn (verilog-backward-ws&directives)
+ (beginning-of-line) ; 1
+ (verilog-forward-ws&directives)
+ 1 )
+ (verilog-beg-of-statement)
+ ))
+ ;; if first word token not keyword, it maybe the instance name
+ ;; check next word token
+ (if (looking-at "\\<\\w+\\>\\|\\s-*(\\s-*\\S-+")
+ (progn (verilog-beg-of-statement)
+ (if (looking-at (concat "\\<\\(constraint\\|"
+ "\\(?:\\w+\\s-*:\\s-*\\)?\\(coverpoint\\|cross\\)"
+ "\\|with\\)\\>\\|" verilog-in-constraint-re))
+ (setq pass 1)))))
+ (if (eq pass 0)
+ (progn (goto-char pt) nil) 1)))
+ ;; not
+ nil))
+
+(defun verilog-at-struct-p ()
+ "If at the { of a struct, return true, not moving point."
+ (save-excursion
+ (if (and (equal (char-after) ?\{)
+ (verilog-backward-token))
+ (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
+ nil)))
+
+(defun verilog-at-struct-mv-p ()
+ "If at the { of a struct, return true, moving point to struct."
+ (let ((pt (point)))
+ (if (and (equal (char-after) ?\{)
+ (verilog-backward-token))
+ (if (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
+ (progn (verilog-beg-of-statement) (point))
+ (progn (goto-char pt) nil))
+ (progn (goto-char pt) nil))))
+
+(defun verilog-at-close-struct-p ()
+ "If at the } that closes a struct, return true."
+ (if (and
+ (equal (char-after) ?\})
+ (verilog-in-struct-p))
+ ;; true
+ (save-excursion
+ (if (looking-at "}\\(?:\\s-*\\w+\\s-*\\)?;") 1))
+ ;; false
+ nil))
+
+(defun verilog-parenthesis-depth ()
+ "Return non zero if in parenthetical-expression."
+ (save-excursion (nth 1 (verilog-syntax-ppss))))
+
+
+(defun verilog-skip-forward-comment-or-string ()
+ "Return true if in a string or comment."
+ (let ((state (save-excursion (verilog-syntax-ppss))))
+ (cond
+ ((nth 3 state) ;Inside string
+ (search-forward "\"")
+ t)
+ ((nth 7 state) ;Inside // comment
+ (forward-line 1)
+ t)
+ ((nth 4 state) ;Inside any comment (hence /**/)
+ (search-forward "*/"))
+ (t
+ nil))))
+
+(defun verilog-skip-backward-comment-or-string ()
+ "Return true if in a string or comment."
+ (let ((state (save-excursion (verilog-syntax-ppss))))
+ (cond
+ ((nth 3 state) ;Inside string
+ (search-backward "\"")
+ t)
+ ((nth 7 state) ;Inside // comment
+ (search-backward "//")
+ (skip-chars-backward "/")
+ t)
+ ((nth 4 state) ;Inside /* */ comment
+ (search-backward "/*")
+ t)
+ (t
+ nil))))
+
+(defun verilog-skip-backward-comments ()
+ "Return true if a comment was skipped."
+ (let ((more t))
+ (while more
+ (setq more
+ (let ((state (save-excursion (verilog-syntax-ppss))))
+ (cond
+ ((nth 7 state) ;Inside // comment
+ (search-backward "//")
+ (skip-chars-backward "/")
+ (skip-chars-backward " \t\n\f")
+ t)
+ ((nth 4 state) ;Inside /* */ comment
+ (search-backward "/*")
+ (skip-chars-backward " \t\n\f")
+ t)
+ ((and (not (bobp))
+ (= (char-before) ?\/)
+ (= (char-before (1- (point))) ?\*))
+ (goto-char (- (point) 2))
+ t) ; Let nth 4 state handle the rest
+ ((and (not (bobp))
+ ;;(verilog-looking-back "\\*)" nil) ;; super slow, use two char-before instead
+ (= (char-before) ?\))
+ (= (char-before (1- (point))) ?\*)
+ (not (verilog-looking-back "(\\s-*\\*)" nil))) ;; slow but unlikely to be called
+ (goto-char (- (point) 2))
+ (if (search-backward "(*" nil t)
+ (progn
+ (skip-chars-backward " \t\n\f")
+ t)
+ (progn
+ (goto-char (+ (point) 2))
+ nil)))
+ (t
+ (/= (skip-chars-backward " \t\n\f") 0))))))))
+
+(defun verilog-skip-forward-comment-p ()
+ "If in comment, move to end and return true."
+ (let* (h
+ (state (save-excursion (verilog-syntax-ppss)))
+ (skip (cond
+ ((nth 3 state) ;Inside string
+ t)
+ ((nth 7 state) ;Inside // comment
+ (end-of-line)
+ (forward-char 1)
+ t)
+ ((nth 4 state) ;Inside /* comment
+ (search-forward "*/")
+ t)
+ ((verilog-in-attribute-p) ;Inside (* attribute
+ (search-forward "*)" nil t)
+ t)
+ (t nil))))
+ (skip-chars-forward " \t\n\f")
+ (while
+ (cond
+ ((looking-at "\\/\\*")
+ (progn
+ (setq h (point))
+ (goto-char (match-end 0))
+ (if (search-forward "*/" nil t)
+ (progn
+ (skip-chars-forward " \t\n\f")
+ (setq skip 't))
+ (progn
+ (goto-char h)
+ nil))))
+ ((and (looking-at "(\\*") ; attribute start, but not an event (*) or (* )
+ (not (looking-at "(\\*\\s-*)")))
+ (progn
+ (setq h (point))
+ (goto-char (match-end 0))
+ (if (search-forward "*)" nil t)
+ (progn
+ (skip-chars-forward " \t\n\f")
+ (setq skip 't))
+ (progn
+ (goto-char h)
+ nil))))
+ (t nil)))
+ skip))
+
+(defun verilog-indent-line-relative ()
+ "Cheap version of indent line.
+Only look at a few lines to determine indent level."
+ (interactive)
+ (let ((indent-str)
+ (sp (point)))
+ (if (looking-at "^[ \t]*$")
+ (cond ;- A blank line; No need to be too smart.
+ ((bobp)
+ (setq indent-str (list 'cpp 0)))
+ ((verilog-continued-line)
+ (let ((sp1 (point)))
+ (if (verilog-continued-line)
+ (progn
+ (goto-char sp)
+ (setq indent-str
+ (list 'statement (verilog-current-indent-level))))
+ (goto-char sp1)
+ (setq indent-str (list 'block (verilog-current-indent-level)))))
+ (goto-char sp))
+ ((goto-char sp)
+ (setq indent-str (verilog-calculate-indent))))
+ (progn (skip-chars-forward " \t")
+ (setq indent-str (verilog-calculate-indent))))
+ (verilog-do-indent indent-str)))
+
+(defun verilog-indent-line ()
+ "Indent for special part of code."
+ (verilog-do-indent (verilog-calculate-indent)))
+
+(defun verilog-do-indent (indent-str)
+ (let ((type (car indent-str))
+ (ind (car (cdr indent-str))))
+ (cond
+ (; handle continued exp
+ (eq type 'cexp)
+ (let ((here (point)))
+ (verilog-backward-syntactic-ws)
+ (cond
+ ((or
+ (= (preceding-char) ?\,)
+ (save-excursion
+ (verilog-beg-of-statement-1)
+ (looking-at verilog-declaration-re)))
+ (let* ( fst
+ (val
+ (save-excursion
+ (backward-char 1)
+ (verilog-beg-of-statement-1)
+ (setq fst (point))
+ (if (looking-at verilog-declaration-re)
+ (progn ; we have multiple words
+ (goto-char (match-end 0))
+ (skip-chars-forward " \t")
+ (cond
+ ((and verilog-indent-declaration-macros
+ (= (following-char) ?\`))
+ (progn
+ (forward-char 1)
+ (forward-word-strictly 1)
+ (skip-chars-forward " \t")))
+ ((= (following-char) ?\[)
+ (progn
+ (forward-char 1)
+ (verilog-backward-up-list -1)
+ (skip-chars-forward " \t"))))
+ (current-column))
+ (progn
+ (goto-char fst)
+ (+ (current-column) verilog-cexp-indent))))))
+ (goto-char here)
+ (indent-line-to val)
+ (if (and (not verilog-indent-lists)
+ (verilog-in-paren))
+ (verilog-pretty-declarations-auto))
+ ))
+ ((= (preceding-char) ?\) )
+ (goto-char here)
+ (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
+ (indent-line-to val)))
+ (t
+ (goto-char here)
+ (let ((val))
+ (verilog-beg-of-statement-1)
+ (if (and (< (point) here)
+ (verilog-re-search-forward "=[ \\t]*" here 'move)
+ ;; not at a |=>, #=#, or [=n] operator
+ (not (string-match "\\[=.\\|#=#\\||=>"
+ (or (buffer-substring (- (point) 2) (1+ (point)))
+ "")))) ; don't let buffer over/under-run spoil the party
+ (setq val (current-column))
+ (setq val (eval (cdr (assoc type verilog-indent-alist)))))
+ (goto-char here)
+ (indent-line-to val))))))
+
+ (; handle inside parenthetical expressions
+ (eq type 'cparenexp)
+ (let* ( here
+ (val (save-excursion
+ (verilog-backward-up-list 1)
+ (forward-char 1)
+ (if verilog-indent-lists
+ (skip-chars-forward " \t")
+ (verilog-forward-syntactic-ws))
+ (setq here (point))
+ (current-column)))
+
+ (decl (save-excursion
+ (goto-char here)
+ (verilog-forward-syntactic-ws)
+ (setq here (point))
+ (looking-at verilog-declaration-re))))
+ (indent-line-to val)
+ (if decl
+ (verilog-pretty-declarations-auto))))
+
+ (;-- Handle the ends
+ (or
+ (looking-at verilog-end-block-re)
+ (verilog-at-close-constraint-p)
+ (verilog-at-close-struct-p))
+ (let ((val (if (eq type 'statement)
+ (- ind verilog-indent-level)
+ ind)))
+ (indent-line-to val)))
+
+ (;-- Case -- maybe line 'em up
+ (and (eq type 'case) (not (looking-at "^[ \t]*$")))
+ (progn
+ (cond
+ ((looking-at "\\<endcase\\>")
+ (indent-line-to ind))
+ (t
+ (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
+ (indent-line-to val))))))
+
+ (;-- defun
+ (and (eq type 'defun)
+ (looking-at verilog-zero-indent-re))
+ (indent-line-to 0))
+
+ (;-- declaration
+ (and (or
+ (eq type 'defun)
+ (eq type 'block))
+ (looking-at verilog-declaration-re)
+ ;; Do not consider "virtual function", "virtual task", "virtual class"
+ ;; as declarations
+ (not (looking-at (concat verilog-declaration-re
+ "\\s-+\\(function\\|task\\|class\\)\\b"))))
+ (verilog-indent-declaration ind))
+
+ (;-- form feeds - ignored as bug in indent-line-to in < 24.5
+ (looking-at "\f"))
+
+ (;-- Everything else
+ t
+ (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
+ (indent-line-to val))))
+
+ (if (looking-at "[ \t]+$")
+ (skip-chars-forward " \t"))
+ indent-str ; Return indent data
+ ))
+
+(defun verilog-current-indent-level ()
+ "Return the indent-level of the current statement."
+ (save-excursion
+ (let (par-pos)
+ (beginning-of-line)
+ (setq par-pos (verilog-parenthesis-depth))
+ (while par-pos
+ (goto-char par-pos)
+ (beginning-of-line)
+ (setq par-pos (verilog-parenthesis-depth)))
+ (skip-chars-forward " \t")
+ (current-column))))
+
+(defun verilog-case-indent-level ()
+ "Return the indent-level of the current statement.
+Do not count named blocks or case-statements."
+ (save-excursion
+ (skip-chars-forward " \t")
+ (cond
+ ((looking-at verilog-named-block-re)
+ (current-column))
+ ((and (not (looking-at verilog-extended-case-re))
+ (looking-at "^[^:;]+[ \t]*:"))
+ (verilog-re-search-forward ":" nil t)
+ (skip-chars-forward " \t")
+ (current-column))
+ (t
+ (current-column)))))
+
+(defun verilog-indent-comment ()
+ "Indent current line as comment."
+ (let* ((stcol
+ (cond
+ ((verilog-in-star-comment-p)
+ (save-excursion
+ (re-search-backward "/\\*" nil t)
+ (1+(current-column))))
+ (comment-column
+ comment-column )
+ (t
+ (save-excursion
+ (re-search-backward "//" nil t)
+ (current-column))))))
+ (indent-line-to stcol)
+ stcol))
+
+(defun verilog-more-comment ()
+ "Make more comment lines like the previous."
+ (let* ((star 0)
+ (stcol
+ (cond
+ ((verilog-in-star-comment-p)
+ (save-excursion
+ (setq star 1)
+ (re-search-backward "/\\*" nil t)
+ (1+(current-column))))
+ (comment-column
+ comment-column )
+ (t
+ (save-excursion
+ (re-search-backward "//" nil t)
+ (current-column))))))
+ (progn
+ (indent-to stcol)
+ (if (and star
+ (save-excursion
+ (forward-line -1)
+ (skip-chars-forward " \t")
+ (looking-at "\\*")))
+ (insert "* ")))))
+
+(defun verilog-comment-indent (&optional _arg)
+ "Return the column number the line should be indented to.
+_ARG is ignored, for `comment-indent-function' compatibility."
+ (cond
+ ((verilog-in-star-comment-p)
+ (save-excursion
+ (re-search-backward "/\\*" nil t)
+ (1+(current-column))))
+ ( comment-column
+ comment-column )
+ (t
+ (save-excursion
+ (re-search-backward "//" nil t)
+ (current-column)))))
+
+;;
+
+(defun verilog-pretty-declarations-auto (&optional quiet)
+ "Call `verilog-pretty-declarations' QUIET based on `verilog-auto-lineup'."
+ (when (or (eq 'all verilog-auto-lineup)
+ (eq 'declarations verilog-auto-lineup))
+ (verilog-pretty-declarations quiet)))
+
+(defun verilog-pretty-declarations (&optional quiet)
+ "Line up declarations around point.
+Be verbose about progress unless optional QUIET set."
+ (interactive)
+ (let* ((m1 (make-marker))
+ (e (point))
+ el
+ r
+ (here (point))
+ ind
+ start
+ startpos
+ end
+ endpos
+ base-ind
+ )
+ (save-excursion
+ (if (progn
+ ;; (verilog-beg-of-statement-1)
+ (beginning-of-line)
+ (verilog-forward-syntactic-ws)
+ (and (not (verilog-in-directive-p)) ; could have `define input foo
+ (looking-at verilog-declaration-re)))
+ (progn
+ (if (verilog-parenthesis-depth)
+ ;; in an argument list or parameter block
+ (setq el (verilog-backward-up-list -1)
+ start (progn
+ (goto-char e)
+ (verilog-backward-up-list 1)
+ (forward-line) ; ignore ( input foo,
+ (verilog-re-search-forward verilog-declaration-re el 'move)
+ (goto-char (match-beginning 0))
+ (skip-chars-backward " \t")
+ (point))
+ startpos (set-marker (make-marker) start)
+ end (progn
+ (goto-char start)
+ (verilog-backward-up-list -1)
+ (forward-char -1)
+ (verilog-backward-syntactic-ws)
+ (point))
+ endpos (set-marker (make-marker) end)
+ base-ind (progn
+ (goto-char start)
+ (forward-char 1)
+ (skip-chars-forward " \t")
+ (current-column)))
+ ;; in a declaration block (not in argument list)
+ (setq
+ start (progn
+ (verilog-beg-of-statement-1)
+ (while (and (looking-at verilog-declaration-re)
+ (not (bobp)))
+ (skip-chars-backward " \t")
+ (setq e (point))
+ (beginning-of-line)
+ (verilog-backward-syntactic-ws)
+ (backward-char)
+ (verilog-beg-of-statement-1))
+ e)
+ startpos (set-marker (make-marker) start)
+ end (progn
+ (goto-char here)
+ (verilog-end-of-statement)
+ (setq e (point)) ;Might be on last line
+ (verilog-forward-syntactic-ws)
+ (while (looking-at verilog-declaration-re)
+ (verilog-end-of-statement)
+ (setq e (point))
+ (verilog-forward-syntactic-ws))
+ e)
+ endpos (set-marker (make-marker) end)
+ base-ind (progn
+ (goto-char start)
+ (verilog-do-indent (verilog-calculate-indent))
+ (verilog-forward-ws&directives)
+ (current-column))))
+ ;; OK, start and end are set
+ (goto-char (marker-position startpos))
+ (if (and (not quiet)
+ (> (- end start) 100))
+ (message "Lining up declarations..(please stand by)"))
+ ;; Get the beginning of line indent first
+ (while (progn (setq e (marker-position endpos))
+ (< (point) e))
+ (cond
+ ((save-excursion (skip-chars-backward " \t")
+ (bolp))
+ (verilog-forward-ws&directives)
+ (indent-line-to base-ind)
+ (verilog-forward-ws&directives)
+ (if (< (point) e)
+ (verilog-re-search-forward "[ \t\n\f]" e 'move)))
+ (t
+ (just-one-space)
+ (verilog-re-search-forward "[ \t\n\f]" e 'move)))
+ ;;(forward-line)
+ )
+ ;; Now find biggest prefix
+ (setq ind (verilog-get-lineup-indent (marker-position startpos) endpos))
+ ;; Now indent each line.
+ (goto-char (marker-position startpos))
+ (while (progn (setq e (marker-position endpos))
+ (setq r (- e (point)))
+ (> r 0))
+ (setq e (point))
+ (unless quiet (message "%d" r))
+ ;; (verilog-do-indent (verilog-calculate-indent)))
+ (verilog-forward-ws&directives)
+ (cond
+ ((or (and verilog-indent-declaration-macros
+ (looking-at verilog-declaration-re-2-macro))
+ (looking-at verilog-declaration-re-2-no-macro))
+ (let ((p (match-end 0)))
+ (set-marker m1 p)
+ (if (verilog-re-search-forward "[[#`]" p 'move)
+ (progn
+ (forward-char -1)
+ (just-one-space)
+ (goto-char (marker-position m1))
+ (just-one-space)
+ (indent-to ind))
+ (progn
+ (just-one-space)
+ (indent-to ind)))))
+ ((verilog-continued-line-1 (marker-position startpos))
+ (goto-char e)
+ (indent-line-to ind))
+ ((verilog-in-struct-p)
+ ;; could have a declaration of a user defined item
+ (goto-char e)
+ (verilog-end-of-statement))
+ (t ; Must be comment or white space
+ (goto-char e)
+ (verilog-forward-ws&directives)
+ (forward-line -1)))
+ (forward-line 1))
+ (unless quiet (message "")))))))
+
+(defun verilog-pretty-expr (&optional quiet _myre)
+ "Line up expressions around point, optionally QUIET with regexp _MYRE ignored."
+ (interactive)
+ (if (not (verilog-in-comment-or-string-p))
+ (save-excursion
+ (let ( (rexp (concat "^\\s-*" verilog-complete-reg))
+ (rexp1 (concat "^\\s-*" verilog-basic-complete-re)))
+ (beginning-of-line)
+ (if (and (not (looking-at rexp ))
+ (looking-at verilog-assignment-operation-re)
+ (save-excursion
+ (goto-char (match-end 2))
+ (and (not (verilog-in-attribute-p))
+ (not (verilog-in-parameter-p))
+ (not (verilog-in-comment-or-string-p)))))
+ (let* ((here (point))
+ (e) (r)
+ (start
+ (progn
+ (beginning-of-line)
+ (setq e (point))
+ (verilog-backward-syntactic-ws)
+ (beginning-of-line)
+ (while (and (not (looking-at rexp1))
+ (looking-at verilog-assignment-operation-re)
+ (not (bobp))
+ )
+ (setq e (point))
+ (verilog-backward-syntactic-ws)
+ (beginning-of-line)
+ ) ;Ack, need to grok `define
+ e))
+ (end
+ (progn
+ (goto-char here)
+ (end-of-line)
+ (setq e (point)) ;Might be on last line
+ (verilog-forward-syntactic-ws)
+ (beginning-of-line)
+ (while (and
+ (not (looking-at rexp1 ))
+ (looking-at verilog-assignment-operation-re)
+ (progn
+ (end-of-line)
+ (not (eq e (point)))))
+ (setq e (point))
+ (verilog-forward-syntactic-ws)
+ (beginning-of-line)
+ )
+ e))
+ (endpos (set-marker (make-marker) end))
+ (ind)
+ )
+ (goto-char start)
+ (verilog-do-indent (verilog-calculate-indent))
+ (if (and (not quiet)
+ (> (- end start) 100))
+ (message "Lining up expressions..(please stand by)"))
+
+ ;; Set indent to minimum throughout region
+ (while (< (point) (marker-position endpos))
+ (beginning-of-line)
+ (verilog-just-one-space verilog-assignment-operation-re)
+ (beginning-of-line)
+ (verilog-do-indent (verilog-calculate-indent))
+ (end-of-line)
+ (verilog-forward-syntactic-ws)
+ )
+
+ ;; Now find biggest prefix
+ (setq ind (verilog-get-lineup-indent-2 verilog-assignment-operation-re start endpos))
+
+ ;; Now indent each line.
+ (goto-char start)
+ (while (progn (setq e (marker-position endpos))
+ (setq r (- e (point)))
+ (> r 0))
+ (setq e (point))
+ (if (not quiet) (message "%d" r))
+ (cond
+ ((looking-at verilog-assignment-operation-re)
+ (goto-char (match-beginning 2))
+ (if (not (or (verilog-in-parenthesis-p) ; leave attributes and comparisons alone
+ (verilog-in-coverage-p)))
+ (if (eq (char-after) ?=)
+ (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
+ (indent-to ind)
+ ))
+ )
+ ((verilog-continued-line-1 start)
+ (goto-char e)
+ (indent-line-to ind))
+ (t ; Must be comment or white space
+ (goto-char e)
+ (verilog-forward-ws&directives)
+ (forward-line -1))
+ )
+ (forward-line 1))
+ (unless quiet (message ""))
+ ))))))
+
+(defun verilog-just-one-space (myre)
+ "Remove extra spaces around regular expression MYRE."
+ (interactive)
+ (if (and (not(looking-at verilog-complete-reg))
+ (looking-at myre))
+ (let ((p1 (match-end 1))
+ (p2 (match-end 2)))
+ (progn
+ (goto-char p2)
+ (just-one-space)
+ (goto-char p1)
+ (just-one-space)))))
+
+(defun verilog-indent-declaration (baseind)
+ "Indent current lines as declaration.
+Line up the variable names based on previous declaration's indentation.
+BASEIND is the base indent to offset everything."
+ (interactive)
+ (let ((pos (point-marker))
+ (lim (save-excursion
+ ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
+ (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
+ (point)))
+ (ind)
+ (val)
+ (m1 (make-marker)))
+ (setq val
+ (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
+ (indent-line-to val)
+
+ ;; Use previous declaration (in this module) as template.
+ (if (or (eq 'all verilog-auto-lineup)
+ (eq 'declarations verilog-auto-lineup))
+ (if (verilog-re-search-backward
+ (or (and verilog-indent-declaration-macros
+ verilog-declaration-re-1-macro)
+ verilog-declaration-re-1-no-macro) lim t)
+ (progn
+ (goto-char (match-end 0))
+ (skip-chars-forward " \t")
+ (setq ind (current-column))
+ (goto-char pos)
+ (setq val
+ (+ baseind
+ (eval (cdr (assoc 'declaration verilog-indent-alist)))))
+ (indent-line-to val)
+ (if (and verilog-indent-declaration-macros
+ (looking-at verilog-declaration-re-2-macro))
+ (let ((p (match-end 0)))
+ (set-marker m1 p)
+ (if (verilog-re-search-forward "[[#`]" p 'move)
+ (progn
+ (forward-char -1)
+ (just-one-space)
+ (goto-char (marker-position m1))
+ (just-one-space)
+ (indent-to ind))
+ (if (/= (current-column) ind)
+ (progn
+ (just-one-space)
+ (indent-to ind)))))
+ (if (looking-at verilog-declaration-re-2-no-macro)
+ (let ((p (match-end 0)))
+ (set-marker m1 p)
+ (if (verilog-re-search-forward "[[`#]" p 'move)
+ (progn
+ (forward-char -1)
+ (just-one-space)
+ (goto-char (marker-position m1))
+ (just-one-space)
+ (indent-to ind))
+ (if (/= (current-column) ind)
+ (progn
+ (just-one-space)
+ (indent-to ind))))))))))
+ (goto-char pos)))
+
+(defun verilog-get-lineup-indent (b edpos)
+ "Return the indent level that will line up several lines within the region.
+Region is defined by B and EDPOS."
+ (save-excursion
+ (let ((ind 0) e)
+ (goto-char b)
+ ;; Get rightmost position
+ (while (progn (setq e (marker-position edpos))
+ (< (point) e))
+ (if (verilog-re-search-forward
+ (or (and verilog-indent-declaration-macros
+ verilog-declaration-re-1-macro)
+ verilog-declaration-re-1-no-macro) e 'move)
+ (progn
+ (goto-char (match-end 0))
+ (verilog-backward-syntactic-ws)
+ (if (> (current-column) ind)
+ (setq ind (current-column)))
+ (goto-char (match-end 0)))))
+ (if (> ind 0)
+ (1+ ind)
+ ;; No lineup-string found
+ (goto-char b)
+ (end-of-line)
+ (verilog-backward-syntactic-ws)
+ ;;(skip-chars-backward " \t")
+ (1+ (current-column))))))
+
+(defun verilog-get-lineup-indent-2 (myre b edpos)
+ "Return the indent level that will line up several lines within the region."
+ (save-excursion
+ (let ((ind 0) e)
+ (goto-char b)
+ ;; Get rightmost position
+ (while (progn (setq e (marker-position edpos))
+ (< (point) e))
+ (if (and (verilog-re-search-forward myre e 'move)
+ (not (verilog-in-attribute-p))) ; skip attribute exprs
+ (progn
+ (goto-char (match-beginning 2))
+ (verilog-backward-syntactic-ws)
+ (if (> (current-column) ind)
+ (setq ind (current-column)))
+ (goto-char (match-end 0)))
+ ))
+ (if (> ind 0)
+ (1+ ind)
+ ;; No lineup-string found
+ (goto-char b)
+ (end-of-line)
+ (skip-chars-backward " \t")
+ (1+ (current-column))))))
+
+(defun verilog-comment-depth (type val)
+ "A useful mode debugging aide. TYPE and VAL are comments for insertion."
+ (save-excursion
+ (let
+ ((b (prog2
+ (beginning-of-line)
+ (point-marker)
+ (end-of-line))))
+ (if (re-search-backward " /\\* [#-]# [a-zA-Z]+ [0-9]+ ## \\*/" b t)
+ (progn
+ (replace-match " /* -# ## */")
+ (end-of-line))
+ (progn
+ (end-of-line)
+ (insert " /* ## ## */"))))
+ (backward-char 6)
+ (insert
+ (format "%s %d" type val))))
+
+
+;;; Completion:
+;;
+(defvar verilog-str nil)
+(defvar verilog-all nil)
+(defvar verilog-pred nil)
+(defvar verilog-buffer-to-use nil)
+(defvar verilog-flag nil)
+(defvar verilog-toggle-completions nil
+ "True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
+Repeated use of \\[verilog-complete-word] will show you all of them.
+Normally, when there is more than one possible completion,
+it displays a list of all possible completions.")
+
+
+(defvar verilog-type-keywords
+ '(
+ "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
+ "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
+ "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
+ "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
+ "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
+ "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
+ )
+ "Keywords for types used when completing a word in a declaration or parmlist.
+\(integer, real, reg...)")
+
+(defvar verilog-cpp-keywords
+ '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
+ "endif")
+ "Keywords to complete when at first word of a line in declarative scope.
+\(initial, always, begin, assign...)
+The procedures and variables defined within the Verilog program
+will be completed at runtime and should not be added to this list.")
+
+(defvar verilog-defun-keywords
+ (append
+ '(
+ "always" "always_comb" "always_ff" "always_latch" "assign"
+ "begin" "end" "generate" "endgenerate" "module" "endmodule"
+ "specify" "endspecify" "function" "endfunction" "initial" "final"
+ "task" "endtask" "primitive" "endprimitive"
+ )
+ verilog-type-keywords)
+ "Keywords to complete when at first word of a line in declarative scope.
+\(initial, always, begin, assign...)
+The procedures and variables defined within the Verilog program
+will be completed at runtime and should not be added to this list.")
+
+(defvar verilog-block-keywords
+ '(
+ "begin" "break" "case" "continue" "else" "end" "endfunction"
+ "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
+ "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
+ "while")
+ "Keywords to complete when at first word of a line in behavioral scope.
+\(begin, if, then, else, for, fork...)
+The procedures and variables defined within the Verilog program
+will be completed at runtime and should not be added to this list.")
+
+(defvar verilog-tf-keywords
+ '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
+ "Keywords to complete when at first word of a line in a task or function.
+\(begin, if, then, else, for, fork.)
+The procedures and variables defined within the Verilog program
+will be completed at runtime and should not be added to this list.")
+
+(defvar verilog-case-keywords
+ '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
+ "Keywords to complete when at first word of a line in case scope.
+\(begin, if, then, else, for, fork...)
+The procedures and variables defined within the Verilog program
+will be completed at runtime and should not be added to this list.")
+
+(defvar verilog-separator-keywords
+ '("else" "then" "begin")
+ "Keywords to complete when NOT standing at the first word of a statement.
+\(else, then, begin...)
+Variables and function names defined within the Verilog program
+will be completed at runtime and should not be added to this list.")
+
+(defvar verilog-gate-ios
+ ;; All these have an implied {"input"...} at the end
+ '(("and" "output")
+ ("buf" "output")
+ ("bufif0" "output")
+ ("bufif1" "output")
+ ("cmos" "output")
+ ("nand" "output")
+ ("nmos" "output")
+ ("nor" "output")
+ ("not" "output")
+ ("notif0" "output")
+ ("notif1" "output")
+ ("or" "output")
+ ("pmos" "output")
+ ("pulldown" "output")
+ ("pullup" "output")
+ ("rcmos" "output")
+ ("rnmos" "output")
+ ("rpmos" "output")
+ ("rtran" "inout" "inout")
+ ("rtranif0" "inout" "inout")
+ ("rtranif1" "inout" "inout")
+ ("tran" "inout" "inout")
+ ("tranif0" "inout" "inout")
+ ("tranif1" "inout" "inout")
+ ("xnor" "output")
+ ("xor" "output"))
+ "Map of direction for each positional argument to each gate primitive.")
+
+(defvar verilog-gate-keywords (mapcar `car verilog-gate-ios)
+ "Keywords for gate primitives.")
+
+(defun verilog-string-diff (str1 str2)
+ "Return index of first letter where STR1 and STR2 differs."
+ (catch 'done
+ (let ((diff 0))
+ (while t
+ (if (or (> (1+ diff) (length str1))
+ (> (1+ diff) (length str2)))
+ (throw 'done diff))
+ (or (equal (aref str1 diff) (aref str2 diff))
+ (throw 'done diff))
+ (setq diff (1+ diff))))))
+
+;; Calculate all possible completions for functions if argument is `function',
+;; completions for procedures if argument is `procedure' or both functions and
+;; procedures otherwise.
+
+(defun verilog-func-completion (type)
+ "Build regular expression for module/task/function names.
+TYPE is `module', `tf' for task or function, or t if unknown."
+ (if (string= verilog-str "")
+ (setq verilog-str "[a-zA-Z_]"))
+ (let ((verilog-str (concat (cond
+ ((eq type 'module) "\\<\\(module\\)\\s +")
+ ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
+ (t "\\<\\(task\\|function\\|module\\)\\s +"))
+ "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
+ match)
+
+ (if (not (looking-at verilog-defun-re))
+ (verilog-re-search-backward verilog-defun-re nil t))
+ (forward-char 1)
+
+ ;; Search through all reachable functions
+ (goto-char (point-min))
+ (while (verilog-re-search-forward verilog-str (point-max) t)
+ (progn (setq match (buffer-substring (match-beginning 2)
+ (match-end 2)))
+ (if (or (null verilog-pred)
+ (funcall verilog-pred match))
+ (setq verilog-all (cons match verilog-all)))))
+ (if (match-beginning 0)
+ (goto-char (match-beginning 0)))))
+
+(defun verilog-get-completion-decl (end)
+ "Macro for searching through current declaration (var, type or const)
+for matches of `str' and adding the occurrence tp `all' through point END."
+ (let ((re (or (and verilog-indent-declaration-macros
+ verilog-declaration-re-2-macro)
+ verilog-declaration-re-2-no-macro))
+ decl-end match)
+ ;; Traverse lines
+ (while (and (< (point) end)
+ (verilog-re-search-forward re end t))
+ ;; Traverse current line
+ (setq decl-end (save-excursion (verilog-declaration-end)))
+ (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
+ (not (match-end 1)))
+ (setq match (buffer-substring (match-beginning 0) (match-end 0)))
+ (if (string-match (concat "\\<" verilog-str) match)
+ (if (or (null verilog-pred)
+ (funcall verilog-pred match))
+ (setq verilog-all (cons match verilog-all)))))
+ (forward-line 1)))
+ verilog-all)
+
+(defun verilog-var-completion ()
+ "Calculate all possible completions for variables (or constants)."
+ (let ((start (point)))
+ ;; Search for all reachable var declarations
+ (verilog-beg-of-defun)
+ (save-excursion
+ ;; Check var declarations
+ (verilog-get-completion-decl start))))
+
+(defun verilog-keyword-completion (keyword-list)
+ "Give list of all possible completions of keywords in KEYWORD-LIST."
+ (mapcar (lambda (s)
+ (if (string-match (concat "\\<" verilog-str) s)
+ (if (or (null verilog-pred)
+ (funcall verilog-pred s))
+ (setq verilog-all (cons s verilog-all)))))
+ keyword-list))
+
+
+(defun verilog-completion (verilog-str verilog-pred verilog-flag)
+ "Function passed to `completing-read', `try-completion' or `all-completions'.
+Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
+must be a function to be called for every match to check if this should
+really be a match. If VERILOG-FLAG is t, the function returns a list of
+all possible completions. If VERILOG-FLAG is nil it returns a string,
+the longest possible completion, or t if VERILOG-STR is an exact match.
+If VERILOG-FLAG is `lambda', the function returns t if VERILOG-STR is an
+exact match, nil otherwise."
+ (save-excursion
+ (let ((verilog-all nil))
+ ;; Set buffer to use for searching labels. This should be set
+ ;; within functions which use verilog-completions
+ (set-buffer verilog-buffer-to-use)
+
+ ;; Determine what should be completed
+ (let ((state (car (verilog-calculate-indent))))
+ (cond ((eq state 'defun)
+ (save-excursion (verilog-var-completion))
+ (verilog-func-completion 'module)
+ (verilog-keyword-completion verilog-defun-keywords))
+
+ ((eq state 'behavioral)
+ (save-excursion (verilog-var-completion))
+ (verilog-func-completion 'module)
+ (verilog-keyword-completion verilog-defun-keywords))
+
+ ((eq state 'block)
+ (save-excursion (verilog-var-completion))
+ (verilog-func-completion 'tf)
+ (verilog-keyword-completion verilog-block-keywords))
+
+ ((eq state 'case)
+ (save-excursion (verilog-var-completion))
+ (verilog-func-completion 'tf)
+ (verilog-keyword-completion verilog-case-keywords))
+
+ ((eq state 'tf)
+ (save-excursion (verilog-var-completion))
+ (verilog-func-completion 'tf)
+ (verilog-keyword-completion verilog-tf-keywords))
+
+ ((eq state 'cpp)
+ (save-excursion (verilog-var-completion))
+ (verilog-keyword-completion verilog-cpp-keywords))
+
+ ((eq state 'cparenexp)
+ (save-excursion (verilog-var-completion)))
+
+ (t;--Anywhere else
+ (save-excursion (verilog-var-completion))
+ (verilog-func-completion 'both)
+ (verilog-keyword-completion verilog-separator-keywords))))
+
+ ;; Now we have built a list of all matches. Give response to caller
+ (verilog-completion-response))))
+
+(defun verilog-completion-response ()
+ (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
+ ;; This was not called by all-completions
+ (if (null verilog-all)
+ ;; Return nil if there was no matching label
+ nil
+ ;; Get longest string common in the labels
+ ;; FIXME: Why not use `try-completion'?
+ (let* ((elm (cdr verilog-all))
+ (match (car verilog-all))
+ (min (length match))
+ tmp)
+ (if (string= match verilog-str)
+ ;; Return t if first match was an exact match
+ (setq match t)
+ (while (not (null elm))
+ ;; Find longest common string
+ (if (< (setq tmp (verilog-string-diff match (car elm))) min)
+ (progn
+ (setq min tmp)
+ (setq match (substring match 0 min))))
+ ;; Terminate with match=t if this is an exact match
+ (if (string= (car elm) verilog-str)
+ (progn
+ (setq match t)
+ (setq elm nil))
+ (setq elm (cdr elm)))))
+ ;; If this is a test just for exact match, return nil ot t
+ (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
+ nil
+ match))))
+ ;; If flag is t, this was called by all-completions. Return
+ ;; list of all possible completions
+ (verilog-flag
+ verilog-all)))
+
+(defvar verilog-last-word-numb 0)
+(defvar verilog-last-word-shown nil)
+(defvar verilog-last-completions nil)
+
+(defun verilog-complete-word ()
+ "Complete word at current point.
+\(See also `verilog-toggle-completions', `verilog-type-keywords',
+and `verilog-separator-keywords'.)"
+ ;; FIXME: Provide completion-at-point-function.
+ (interactive)
+ (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
+ (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
+ (verilog-str (buffer-substring b e))
+ ;; The following variable is used in verilog-completion
+ (verilog-buffer-to-use (current-buffer))
+ (allcomp (if (and verilog-toggle-completions
+ (string= verilog-last-word-shown verilog-str))
+ verilog-last-completions
+ (all-completions verilog-str 'verilog-completion)))
+ (match (if verilog-toggle-completions
+ "" (try-completion
+ verilog-str (mapcar (lambda (elm)
+ (cons elm 0)) allcomp)))))
+ ;; Delete old string
+ (delete-region b e)
+
+ ;; Toggle-completions inserts whole labels
+ (if verilog-toggle-completions
+ (progn
+ ;; Update entry number in list
+ (setq verilog-last-completions allcomp
+ verilog-last-word-numb
+ (if (>= verilog-last-word-numb (1- (length allcomp)))
+ 0
+ (1+ verilog-last-word-numb)))
+ (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
+ ;; Display next match or same string if no match was found
+ (if (not (null allcomp))
+ (insert "" verilog-last-word-shown)
+ (insert "" verilog-str)
+ (message "(No match)")))
+ ;; The other form of completion does not necessarily do that.
+
+ ;; Insert match if found, or the original string if no match
+ (if (or (null match) (equal match 't))
+ (progn (insert "" verilog-str)
+ (message "(No match)"))
+ (insert "" match))
+ ;; Give message about current status of completion
+ (cond ((equal match 't)
+ (if (not (null (cdr allcomp)))
+ (message "(Complete but not unique)")
+ (message "(Sole completion)")))
+ ;; Display buffer if the current completion didn't help
+ ;; on completing the label.
+ ((and (not (null (cdr allcomp))) (= (length verilog-str)
+ (length match)))
+ (with-output-to-temp-buffer "*Completions*"
+ (display-completion-list allcomp))
+ ;; Wait for a key press. Then delete *Completion* window
+ (momentary-string-display "" (point))
+ (delete-window (get-buffer-window (get-buffer "*Completions*")))
+ )))))
+
+(defun verilog-show-completions ()
+ "Show all possible completions at current point."
+ (interactive)
+ (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
+ (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
+ (verilog-str (buffer-substring b e))
+ ;; The following variable is used in verilog-completion
+ (verilog-buffer-to-use (current-buffer))
+ (allcomp (if (and verilog-toggle-completions
+ (string= verilog-last-word-shown verilog-str))
+ verilog-last-completions
+ (all-completions verilog-str 'verilog-completion))))
+ ;; Show possible completions in a temporary buffer.
+ (with-output-to-temp-buffer "*Completions*"
+ (display-completion-list allcomp))
+ ;; Wait for a key press. Then delete *Completion* window
+ (momentary-string-display "" (point))
+ (delete-window (get-buffer-window (get-buffer "*Completions*")))))
+
+
+(defun verilog-get-default-symbol ()
+ "Return symbol around current point as a string."
+ (save-excursion
+ (buffer-substring (progn
+ (skip-chars-backward " \t")
+ (skip-chars-backward "a-zA-Z0-9_")
+ (point))
+ (progn
+ (skip-chars-forward "a-zA-Z0-9_")
+ (point)))))
+
+(defun verilog-build-defun-re (str &optional arg)
+ "Return function/task/module starting with STR as regular expression.
+With optional second ARG non-nil, STR is the complete name of the instruction."
+ (if arg
+ (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
+ (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
+
+(defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
+ "Function passed to `completing-read', `try-completion' or `all-completions'.
+Returns a completion on any function name based on VERILOG-STR prefix. If
+VERILOG-PRED is non-nil, it must be a function to be called for every match
+to check if this should really be a match. If VERILOG-FLAG is t, the
+function returns a list of all possible completions. If it is nil it
+returns a string, the longest possible completion, or t if VERILOG-STR is
+an exact match. If VERILOG-FLAG is `lambda', the function returns t if
+VERILOG-STR is an exact match, nil otherwise."
+ (save-excursion
+ (let ((verilog-all nil)
+ match)
+
+ ;; Set buffer to use for searching labels. This should be set
+ ;; within functions which use verilog-completions
+ (set-buffer verilog-buffer-to-use)
+
+ (let ((verilog-str verilog-str))
+ ;; Build regular expression for functions
+ (if (string= verilog-str "")
+ (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
+ (setq verilog-str (verilog-build-defun-re verilog-str)))
+ (goto-char (point-min))
+
+ ;; Build a list of all possible completions
+ (while (verilog-re-search-forward verilog-str nil t)
+ (setq match (buffer-substring (match-beginning 2) (match-end 2)))
+ (if (or (null verilog-pred)
+ (funcall verilog-pred match))
+ (setq verilog-all (cons match verilog-all)))))
+
+ ;; Now we have built a list of all matches. Give response to caller
+ (verilog-completion-response))))
+
+(defun verilog-goto-defun ()
+ "Move to specified Verilog module/interface/task/function.
+The default is a name found in the buffer around point.
+If search fails, other files are checked based on
+`verilog-library-flags'."
+ (interactive)
+ (let* ((default (verilog-get-default-symbol))
+ ;; The following variable is used in verilog-comp-function
+ (verilog-buffer-to-use (current-buffer))
+ (label (if (not (string= default ""))
+ ;; Do completion with default
+ (completing-read (concat "Goto-Label: (default "
+ default ") ")
+ 'verilog-comp-defun nil nil "")
+ ;; There is no default value. Complete without it
+ (completing-read "Goto-Label: "
+ 'verilog-comp-defun nil nil "")))
+ pt)
+ ;; Make sure library paths are correct, in case need to resolve module
+ (verilog-auto-reeval-locals)
+ (verilog-getopt-flags)
+ ;; If there was no response on prompt, use default value
+ (if (string= label "")
+ (setq label default))
+ ;; Goto right place in buffer if label is not an empty string
+ (or (string= label "")
+ (progn
+ (save-excursion
+ (goto-char (point-min))
+ (setq pt
+ (re-search-forward (verilog-build-defun-re label t) nil t)))
+ (when pt
+ (goto-char pt)
+ (beginning-of-line))
+ pt)
+ (verilog-goto-defun-file label))))
+
+;; Eliminate compile warning
+(defvar occur-pos-list)
+
+(defun verilog-showscopes ()
+ "List all scopes in this module."
+ (interactive)
+ (let ((buffer (current-buffer))
+ (linenum 1)
+ (nlines 0)
+ (first 1)
+ (prevpos (point-min))
+ (final-context-start (make-marker))
+ (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)"))
+ (with-output-to-temp-buffer "*Occur*"
+ (save-excursion
+ (message "Searching for %s ..." regexp)
+ ;; Find next match, but give up if prev match was at end of buffer.
+ (while (and (not (= prevpos (point-max)))
+ (verilog-re-search-forward regexp nil t))
+ (goto-char (match-beginning 0))
+ (beginning-of-line)
+ (save-match-data
+ (setq linenum (+ linenum (count-lines prevpos (point)))))
+ (setq prevpos (point))
+ (goto-char (match-end 0))
+ (let* ((start (save-excursion
+ (goto-char (match-beginning 0))
+ (forward-line (if (< nlines 0) nlines (- nlines)))
+ (point)))
+ (end (save-excursion
+ (goto-char (match-end 0))
+ (if (> nlines 0)
+ (forward-line (1+ nlines))
+ (forward-line 1))
+ (point)))
+ (tag (format "%3d" linenum))
+ (empty (make-string (length tag) ?\ ))
+ tem)
+ (save-excursion
+ (setq tem (make-marker))
+ (set-marker tem (point))
+ (set-buffer standard-output)
+ (setq occur-pos-list (cons tem occur-pos-list))
+ (or first (zerop nlines)
+ (insert "--------\n"))
+ (setq first nil)
+ (insert-buffer-substring buffer start end)
+ (backward-char (- end start))
+ (setq tem (if (< nlines 0) (- nlines) nlines))
+ (while (> tem 0)
+ (insert empty ?:)
+ (forward-line 1)
+ (setq tem (1- tem)))
+ (let ((this-linenum linenum))
+ (set-marker final-context-start
+ (+ (point) (- (match-end 0) (match-beginning 0))))
+ (while (< (point) final-context-start)
+ (if (null tag)
+ (setq tag (format "%3d" this-linenum)))
+ (insert tag ?:)))))))
+ (set-buffer-modified-p nil))))
+
+
+;; Highlight helper functions
+(defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
+
+(defun verilog-within-translate-off ()
+ "Return point if within translate-off region, else nil."
+ (and (save-excursion
+ (re-search-backward
+ (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
+ nil t))
+ (equal "off" (match-string 2))
+ (point)))
+
+(defun verilog-start-translate-off (limit)
+ "Return point before translate-off directive if before LIMIT, else nil."
+ (when (re-search-forward
+ (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
+ limit t)
+ (match-beginning 0)))
+
+(defun verilog-back-to-start-translate-off (limit)
+ "Return point before translate-off directive if before LIMIT, else nil."
+ (when (re-search-backward
+ (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
+ limit t)
+ (match-beginning 0)))
+
+(defun verilog-end-translate-off (limit)
+ "Return point after translate-on directive if before LIMIT, else nil."
+
+ (re-search-forward (concat
+ "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
+
+(defun verilog-match-translate-off (limit)
+ "Match a translate-off block, setting `match-data' and returning t, else nil.
+Bound search by LIMIT."
+ (when (< (point) limit)
+ (let ((start (or (verilog-within-translate-off)
+ (verilog-start-translate-off limit)))
+ (case-fold-search t))
+ (when start
+ (let ((end (or (verilog-end-translate-off limit) limit)))
+ (set-match-data (list start end))
+ (goto-char end))))))
+
+(defun verilog-font-lock-match-item (limit)
+ "Match, and move over, any declaration item after point.
+Bound search by LIMIT. Adapted from
+`font-lock-match-c-style-declaration-item-and-skip-to-next'."
+ (condition-case nil
+ (save-restriction
+ (narrow-to-region (point-min) limit)
+ ;; match item
+ (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
+ (save-match-data
+ (goto-char (match-end 1))
+ ;; move to next item
+ (if (looking-at "\\(\\s-*,\\)")
+ (goto-char (match-end 1))
+ (end-of-line) t))))
+ (error nil)))
+
+
+;; Added by Subbu Meiyappan for Header
+
+(defun verilog-header ()
+ "Insert a standard Verilog file header.
+See also `verilog-sk-header' for an alternative format."
+ (interactive)
+ (let ((start (point)))
+ (insert "\
+//-----------------------------------------------------------------------------
+// Title : <title>
+// Project : <project>
+//-----------------------------------------------------------------------------
+// File : <filename>
+// Author : <author>
+// Created : <credate>
+// Last modified : <moddate>
+//-----------------------------------------------------------------------------
+// Description :
+// <description>
+//-----------------------------------------------------------------------------
+// Copyright (c) <copydate> by <company> This model is the confidential and
+// proprietary property of <company> and the possession or use of this
+// file requires a written license from <company>.
+//------------------------------------------------------------------------------
+// Modification history :
+// <modhist>
+//-----------------------------------------------------------------------------
+
+")
+ (goto-char start)
+ (search-forward "<filename>")
+ (replace-match (buffer-name) t t)
+ (search-forward "<author>") (replace-match "" t t)
+ (insert (user-full-name))
+ (insert " <" (user-login-name) "@" (system-name) ">")
+ (search-forward "<credate>") (replace-match "" t t)
+ (verilog-insert-date)
+ (search-forward "<moddate>") (replace-match "" t t)
+ (verilog-insert-date)
+ (search-forward "<copydate>") (replace-match "" t t)
+ (verilog-insert-year)
+ (search-forward "<modhist>") (replace-match "" t t)
+ (verilog-insert-date)
+ (insert " : created")
+ (goto-char start)
+ (let (string)
+ (setq string (read-string "title: "))
+ (search-forward "<title>")
+ (replace-match string t t)
+ (setq string (read-string "project: " verilog-project))
+ (setq verilog-project string)
+ (search-forward "<project>")
+ (replace-match string t t)
+ (setq string (read-string "Company: " verilog-company))
+ (setq verilog-company string)
+ (search-forward "<company>")
+ (replace-match string t t)
+ (search-forward "<company>")
+ (replace-match string t t)
+ (search-forward "<company>")
+ (replace-match string t t)
+ (search-backward "<description>")
+ (replace-match "" t t))))
+
+;; verilog-header Uses the verilog-insert-date function
+
+(defun verilog-insert-date ()
+ "Insert date from the system."
+ (interactive)
+ (if verilog-date-scientific-format
+ (insert (format-time-string "%Y/%m/%d"))
+ (insert (format-time-string "%d.%m.%Y"))))
+
+(defun verilog-insert-year ()
+ "Insert year from the system."
+ (interactive)
+ (insert (format-time-string "%Y")))
+
+
+;;; Signal list parsing:
+;;
+
+;; Elements of a signal list
+;; Unfortunately we use 'assoc' on this, so can't be a vector
+(defsubst verilog-sig-new (name bits comment mem enum signed type multidim modport)
+ (list name bits comment mem enum signed type multidim modport))
+(defsubst verilog-sig-name (sig)
+ (car sig))
+(defsubst verilog-sig-bits (sig) ; First element of packed array (pre signal-name)
+ (nth 1 sig))
+(defsubst verilog-sig-comment (sig)
+ (nth 2 sig))
+(defsubst verilog-sig-memory (sig) ; Unpacked array (post signal-name)
+ (nth 3 sig))
+(defsubst verilog-sig-enum (sig)
+ (nth 4 sig))
+(defsubst verilog-sig-signed (sig)
+ (nth 5 sig))
+(defsubst verilog-sig-type (sig)
+ (nth 6 sig))
+(defsubst verilog-sig-type-set (sig type)
+ (setcar (nthcdr 6 sig) type))
+(defsubst verilog-sig-multidim (sig) ; Second and additional elements of packed array
+ (nth 7 sig))
+(defsubst verilog-sig-multidim-string (sig)
+ (if (verilog-sig-multidim sig)
+ (let ((str "") (args (verilog-sig-multidim sig)))
+ (while args
+ (setq str (concat (car args) str))
+ (setq args (cdr args)))
+ str)))
+(defsubst verilog-sig-modport (sig)
+ (nth 8 sig))
+(defsubst verilog-sig-width (sig)
+ (verilog-make-width-expression (verilog-sig-bits sig)))
+
+(defsubst verilog-alw-new (outputs-del outputs-imm temps inputs)
+ (vector outputs-del outputs-imm temps inputs))
+(defsubst verilog-alw-get-outputs-delayed (sigs)
+ (aref sigs 0))
+(defsubst verilog-alw-get-outputs-immediate (sigs)
+ (aref sigs 1))
+(defsubst verilog-alw-get-temps (sigs)
+ (aref sigs 2))
+(defsubst verilog-alw-get-inputs (sigs)
+ (aref sigs 3))
+(defsubst verilog-alw-get-uses-delayed (sigs)
+ (aref sigs 0))
+
+(defsubst verilog-modport-new (name clockings decls)
+ (list name clockings decls))
+(defsubst verilog-modport-name (sig)
+ (car sig))
+(defsubst verilog-modport-clockings (sig)
+ (nth 1 sig)) ; Returns list of names
+(defsubst verilog-modport-clockings-add (sig val)
+ (setcar (nthcdr 1 sig) (cons val (nth 1 sig))))
+(defsubst verilog-modport-decls (sig)
+ (nth 2 sig)) ; Returns verilog-decls-* structure
+(defsubst verilog-modport-decls-set (sig val)
+ (setcar (nthcdr 2 sig) val))
+
+(defsubst verilog-modi-new (name fob pt type)
+ (vector name fob pt type))
+(defsubst verilog-modi-name (modi)
+ (aref modi 0))
+(defsubst verilog-modi-file-or-buffer (modi)
+ (aref modi 1))
+(defsubst verilog-modi-get-point (modi)
+ (aref modi 2))
+(defsubst verilog-modi-get-type (modi) ; "module" or "interface"
+ (aref modi 3))
+(defsubst verilog-modi-get-decls (modi)
+ (verilog-modi-cache-results modi 'verilog-read-decls))
+(defsubst verilog-modi-get-sub-decls (modi)
+ (verilog-modi-cache-results modi 'verilog-read-sub-decls))
+
+;; Signal reading for given module
+;; Note these all take modi's - as returned from verilog-modi-current
+(defsubst verilog-decls-new (out inout in vars modports assigns consts gparams interfaces)
+ (vector out inout in vars modports assigns consts gparams interfaces))
+(defsubst verilog-decls-append (a b)
+ (cond ((not a) b) ((not b) a)
+ (t (vector (append (aref a 0) (aref b 0)) (append (aref a 1) (aref b 1))
+ (append (aref a 2) (aref b 2)) (append (aref a 3) (aref b 3))
+ (append (aref a 4) (aref b 4)) (append (aref a 5) (aref b 5))
+ (append (aref a 6) (aref b 6)) (append (aref a 7) (aref b 7))
+ (append (aref a 8) (aref b 8))))))
+(defsubst verilog-decls-get-outputs (decls)
+ (aref decls 0))
+(defsubst verilog-decls-get-inouts (decls)
+ (aref decls 1))
+(defsubst verilog-decls-get-inputs (decls)
+ (aref decls 2))
+(defsubst verilog-decls-get-vars (decls)
+ (aref decls 3))
+(defsubst verilog-decls-get-modports (decls) ; Also for clocking blocks; contains another verilog-decls struct
+ (aref decls 4)) ; Returns verilog-modport* structure
+(defsubst verilog-decls-get-assigns (decls)
+ (aref decls 5))
+(defsubst verilog-decls-get-consts (decls)
+ (aref decls 6))
+(defsubst verilog-decls-get-gparams (decls)
+ (aref decls 7))
+(defsubst verilog-decls-get-interfaces (decls)
+ (aref decls 8))
+
+
+(defsubst verilog-subdecls-new (out inout in intf intfd)
+ (vector out inout in intf intfd))
+(defsubst verilog-subdecls-get-outputs (subdecls)
+ (aref subdecls 0))
+(defsubst verilog-subdecls-get-inouts (subdecls)
+ (aref subdecls 1))
+(defsubst verilog-subdecls-get-inputs (subdecls)
+ (aref subdecls 2))
+(defsubst verilog-subdecls-get-interfaces (subdecls)
+ (aref subdecls 3))
+(defsubst verilog-subdecls-get-interfaced (subdecls)
+ (aref subdecls 4))
+
+(defun verilog-signals-from-signame (signame-list)
+ "Return signals in standard form from SIGNAME-LIST, a simple list of names."
+ (mapcar (lambda (name) (verilog-sig-new name nil nil nil nil nil nil nil nil))
+ signame-list))
+
+(defun verilog-signals-in (in-list not-list)
+ "Return list of signals in IN-LIST that are also in NOT-LIST.
+Also remove any duplicates in IN-LIST.
+Signals must be in standard (base vector) form."
+ ;; This function is hot, so implemented as O(1)
+ (cond ((eval-when-compile (fboundp 'make-hash-table))
+ (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
+ (ht-not (make-hash-table :test 'equal :rehash-size 4.0))
+ out-list)
+ (while not-list
+ (puthash (car (car not-list)) t ht-not)
+ (setq not-list (cdr not-list)))
+ (while in-list
+ (when (and (gethash (verilog-sig-name (car in-list)) ht-not)
+ (not (gethash (verilog-sig-name (car in-list)) ht)))
+ (setq out-list (cons (car in-list) out-list))
+ (puthash (verilog-sig-name (car in-list)) t ht))
+ (setq in-list (cdr in-list)))
+ (nreverse out-list)))
+ ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
+ (t
+ (let (out-list)
+ (while in-list
+ (if (and (assoc (verilog-sig-name (car in-list)) not-list)
+ (not (assoc (verilog-sig-name (car in-list)) out-list)))
+ (setq out-list (cons (car in-list) out-list)))
+ (setq in-list (cdr in-list)))
+ (nreverse out-list)))))
+;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("C" "")))
+
+(defun verilog-signals-not-in (in-list not-list)
+ "Return list of signals in IN-LIST that aren't also in NOT-LIST.
+Also remove any duplicates in IN-LIST.
+Signals must be in standard (base vector) form."
+ ;; This function is hot, so implemented as O(1)
+ (cond ((eval-when-compile (fboundp 'make-hash-table))
+ (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
+ out-list)
+ (while not-list
+ (puthash (car (car not-list)) t ht)
+ (setq not-list (cdr not-list)))
+ (while in-list
+ (when (not (gethash (verilog-sig-name (car in-list)) ht))
+ (setq out-list (cons (car in-list) out-list))
+ (puthash (verilog-sig-name (car in-list)) t ht))
+ (setq in-list (cdr in-list)))
+ (nreverse out-list)))
+ ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
+ (t
+ (let (out-list)
+ (while in-list
+ (if (and (not (assoc (verilog-sig-name (car in-list)) not-list))
+ (not (assoc (verilog-sig-name (car in-list)) out-list)))
+ (setq out-list (cons (car in-list) out-list)))
+ (setq in-list (cdr in-list)))
+ (nreverse out-list)))))
+;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
+
+(defun verilog-signals-not-in-struct (in-list not-list)
+ "Return list of signals in IN-LIST that aren't also in NOT-LIST.
+Also remove any duplicates in IN-LIST.
+Any structure in not-list will remove all members in in-list.
+Signals must be in standard (base vector) form."
+ (cond ((eval-when-compile (fboundp 'make-hash-table))
+ (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
+ out-list addit nm)
+ (while not-list
+ (puthash (car (car not-list)) t ht)
+ (setq not-list (cdr not-list)))
+ (while in-list
+ (setq nm (verilog-sig-name (car in-list)))
+ (when (not (gethash nm ht))
+ (setq addit t)
+ (while (string-match "^\\([^\\].*\\)\\.[^.]+$" nm)
+ (setq nm (match-string 1 nm))
+ (setq addit (and addit
+ (not (gethash nm ht)))))
+ (when addit
+ (setq out-list (cons (car in-list) out-list))
+ (puthash (verilog-sig-name (car in-list)) t ht)))
+ (setq in-list (cdr in-list)))
+ (nreverse out-list)))
+ ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
+ (t
+ (let (out-list addit nm)
+ (while in-list
+ (setq nm (verilog-sig-name (car in-list)))
+ (when (and (not (assoc nm not-list))
+ (not (assoc nm out-list)))
+ (setq addit t)
+ (while (string-match "^\\([^\\].*\\)\\.[^.]+$" nm)
+ (setq nm (match-string 1 nm))
+ (setq addit (and addit
+ (not (assoc nm not-list)))))
+ (when addit
+ (setq out-list (cons (car in-list) out-list))))
+ (setq in-list (cdr in-list)))
+ (nreverse out-list)))))
+;;(verilog-signals-not-in-struct '(("A" "") ("B" "") ("DEL.SUB.A" "[2:3]")) '(("DEL.SUB" "") ("EXT" "")))
+
+(defun verilog-signals-memory (in-list)
+ "Return list of signals in IN-LIST that are memorized (multidimensional)."
+ (let (out-list)
+ (while in-list
+ (if (nth 3 (car in-list))
+ (setq out-list (cons (car in-list) out-list)))
+ (setq in-list (cdr in-list)))
+ out-list))
+;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
+
+(defun verilog-signals-sort-compare (a b)
+ "Compare signal A and B for sorting."
+ (string< (verilog-sig-name a) (verilog-sig-name b)))
+
+(defun verilog-signals-not-params (in-list)
+ "Return list of signals in IN-LIST that aren't parameters or numeric constants."
+ (let (out-list)
+ (while in-list
+ ;; Namespace intentionally short for AUTOs and compatibility
+ (unless (boundp (intern (concat "vh-" (verilog-sig-name (car in-list)))))
+ (setq out-list (cons (car in-list) out-list)))
+ (setq in-list (cdr in-list)))
+ (nreverse out-list)))
+
+(defun verilog-signals-with (func in-list)
+ "Return list of signals where FUNC is true executed on each signal in IN-LIST."
+ (let (out-list)
+ (while in-list
+ (when (funcall func (car in-list))
+ (setq out-list (cons (car in-list) out-list)))
+ (setq in-list (cdr in-list)))
+ (nreverse out-list)))
+
+(defun verilog-signals-combine-bus (in-list)
+ "Return a list of signals in IN-LIST, with buses combined.
+Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
+ (let (combo
+ buswarn
+ out-list
+ sig highbit lowbit ; Temp information about current signal
+ sv-name sv-highbit sv-lowbit ; Details about signal we are forming
+ sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
+ sv-modport
+ bus)
+ ;; Shove signals so duplicated signals will be adjacent
+ (setq in-list (sort in-list `verilog-signals-sort-compare))
+ (while in-list
+ (setq sig (car in-list))
+ ;; No current signal; form from existing details
+ (unless sv-name
+ (setq sv-name (verilog-sig-name sig)
+ sv-highbit nil
+ sv-busstring nil
+ sv-comment (verilog-sig-comment sig)
+ sv-memory (verilog-sig-memory sig)
+ sv-enum (verilog-sig-enum sig)
+ sv-signed (verilog-sig-signed sig)
+ sv-type (verilog-sig-type sig)
+ sv-multidim (verilog-sig-multidim sig)
+ sv-modport (verilog-sig-modport sig)
+ combo ""
+ buswarn ""))
+ ;; Extract bus details
+ (setq bus (verilog-sig-bits sig))
+ (setq bus (and bus (verilog-simplify-range-expression bus)))
+ (cond ((and bus
+ (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
+ (setq highbit (string-to-number (match-string 1 bus))
+ lowbit (string-to-number
+ (match-string 2 bus))))
+ (and (string-match "\\[\\([0-9]+\\)\\]" bus)
+ (setq highbit (string-to-number (match-string 1 bus))
+ lowbit highbit))))
+ ;; Combine bits in bus
+ (if sv-highbit
+ (setq sv-highbit (max highbit sv-highbit)
+ sv-lowbit (min lowbit sv-lowbit))
+ (setq sv-highbit highbit
+ sv-lowbit lowbit)))
+ (bus
+ ;; String, probably something like `preproc:0
+ (setq sv-busstring bus)))
+ ;; Peek ahead to next signal
+ (setq in-list (cdr in-list))
+ (setq sig (car in-list))
+ (cond ((and sig (equal sv-name (verilog-sig-name sig)))
+ ;; Combine with this signal
+ (when (and sv-busstring
+ (not (equal sv-busstring (verilog-sig-bits sig))))
+ (when nil ; Debugging
+ (message (concat "Warning, can't merge into single bus `%s%s'"
+ ", the AUTOs may be wrong")
+ sv-name bus))
+ (setq buswarn ", Couldn't Merge"))
+ (if (verilog-sig-comment sig) (setq combo ", ..."))
+ (setq sv-memory (or sv-memory (verilog-sig-memory sig))
+ sv-enum (or sv-enum (verilog-sig-enum sig))
+ sv-signed (or sv-signed (verilog-sig-signed sig))
+ sv-type (or sv-type (verilog-sig-type sig))
+ sv-multidim (or sv-multidim (verilog-sig-multidim sig))
+ sv-modport (or sv-modport (verilog-sig-modport sig))))
+ ;; Doesn't match next signal, add to queue, zero in prep for next
+ ;; Note sig may also be nil for the last signal in the list
+ (t
+ (setq out-list
+ (cons (verilog-sig-new
+ sv-name
+ (or sv-busstring
+ (if sv-highbit
+ (concat "[" (int-to-string sv-highbit) ":"
+ (int-to-string sv-lowbit) "]")))
+ (concat sv-comment combo buswarn)
+ sv-memory sv-enum sv-signed sv-type sv-multidim sv-modport)
+ out-list)
+ sv-name nil))))
+ ;;
+ out-list))
+
+(defun verilog-sig-tieoff (sig)
+ "Return tieoff expression for given SIG, with appropriate width.
+Tieoff value uses `verilog-active-low-regexp' and
+`verilog-auto-reset-widths'."
+ (concat
+ (if (and verilog-active-low-regexp
+ (verilog-string-match-fold verilog-active-low-regexp (verilog-sig-name sig)))
+ "~" "")
+ (cond ((not verilog-auto-reset-widths)
+ "0")
+ ((equal verilog-auto-reset-widths 'unbased)
+ "'0")
+ ;; Else presume verilog-auto-reset-widths is true
+ (t
+ (let* ((width (verilog-sig-width sig)))
+ (cond ((not width)
+ "`0/*NOWIDTH*/")
+ ((string-match "^[0-9]+$" width)
+ (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
+ (t
+ (concat "{" width "{1'b0}}"))))))))
+
+;;
+;; Dumping
+;;
+
+(defun verilog-decls-princ (decls &optional header prefix)
+ "For debug, dump the `verilog-read-decls' structure DECLS.
+Use optional HEADER and PREFIX."
+ (when decls
+ (if header (princ header))
+ (setq prefix (or prefix ""))
+ (verilog-signals-princ (verilog-decls-get-outputs decls)
+ (concat prefix "Outputs:\n") (concat prefix " "))
+ (verilog-signals-princ (verilog-decls-get-inouts decls)
+ (concat prefix "Inout:\n") (concat prefix " "))
+ (verilog-signals-princ (verilog-decls-get-inputs decls)
+ (concat prefix "Inputs:\n") (concat prefix " "))
+ (verilog-signals-princ (verilog-decls-get-vars decls)
+ (concat prefix "Vars:\n") (concat prefix " "))
+ (verilog-signals-princ (verilog-decls-get-assigns decls)
+ (concat prefix "Assigns:\n") (concat prefix " "))
+ (verilog-signals-princ (verilog-decls-get-consts decls)
+ (concat prefix "Consts:\n") (concat prefix " "))
+ (verilog-signals-princ (verilog-decls-get-gparams decls)
+ (concat prefix "Gparams:\n") (concat prefix " "))
+ (verilog-signals-princ (verilog-decls-get-interfaces decls)
+ (concat prefix "Interfaces:\n") (concat prefix " "))
+ (verilog-modport-princ (verilog-decls-get-modports decls)
+ (concat prefix "Modports:\n") (concat prefix " "))
+ (princ "\n")))
+
+(defun verilog-signals-princ (signals &optional header prefix)
+ "For debug, dump internal SIGNALS structures, with HEADER and PREFIX."
+ (when signals
+ (if header (princ header))
+ (while signals
+ (let ((sig (car signals)))
+ (setq signals (cdr signals))
+ (princ prefix)
+ (princ "\"") (princ (verilog-sig-name sig)) (princ "\"")
+ (princ " bits=") (princ (verilog-sig-bits sig))
+ (princ " cmt=") (princ (verilog-sig-comment sig))
+ (princ " mem=") (princ (verilog-sig-memory sig))
+ (princ " enum=") (princ (verilog-sig-enum sig))
+ (princ " sign=") (princ (verilog-sig-signed sig))
+ (princ " type=") (princ (verilog-sig-type sig))
+ (princ " dim=") (princ (verilog-sig-multidim sig))
+ (princ " modp=") (princ (verilog-sig-modport sig))
+ (princ "\n")))))
+
+(defun verilog-modport-princ (modports &optional header prefix)
+ "For debug, dump internal MODPORTS structures, with HEADER and PREFIX."
+ (when modports
+ (if header (princ header))
+ (while modports
+ (let ((sig (car modports)))
+ (setq modports (cdr modports))
+ (princ prefix)
+ (princ "\"") (princ (verilog-modport-name sig)) (princ "\"")
+ (princ " clockings=") (princ (verilog-modport-clockings sig))
+ (princ "\n")
+ (verilog-decls-princ (verilog-modport-decls sig)
+ (concat prefix " syms:\n")
+ (concat prefix " "))))))
+
+;;
+;; Port/Wire/Etc Reading
+;;
+
+(defun verilog-read-inst-backward-name ()
+ "Internal. Move point back to beginning of inst-name."
+ (verilog-backward-open-paren)
+ (let (done)
+ (while (not done)
+ (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_$]\\|\\]\\)" nil nil) ; ] isn't word boundary
+ (cond ((looking-at ")")
+ (verilog-backward-open-paren))
+ (t (setq done t)))))
+ (while (looking-at "\\]")
+ (verilog-backward-open-bracket)
+ (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_$]\\|\\]\\)" nil nil))
+ (skip-chars-backward "a-zA-Z0-9`_$"))
+
+(defun verilog-read-inst-module-matcher ()
+ "Set match data 0 with module_name when point is inside instantiation."
+ (verilog-read-inst-backward-name)
+ ;; Skip over instantiation name
+ (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_$]\\|)\\)" nil nil) ; ) isn't word boundary
+ ;; Check for parameterized instantiations
+ (when (looking-at ")")
+ (verilog-backward-open-paren)
+ (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_$]" nil nil))
+ (skip-chars-backward "a-zA-Z0-9'_$")
+ ;; #1 is legal syntax for gate primitives
+ (when (save-excursion
+ (verilog-backward-syntactic-ws-quick)
+ (eq ?# (char-before)))
+ (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_$]" nil nil)
+ (skip-chars-backward "a-zA-Z0-9'_$"))
+ (looking-at "[a-zA-Z0-9`_$]+")
+ ;; Important: don't use match string, this must work with Emacs 19 font-lock on
+ (buffer-substring-no-properties (match-beginning 0) (match-end 0))
+ ;; Caller assumes match-beginning/match-end is still set
+ )
+
+(defun verilog-read-inst-module ()
+ "Return module_name when point is inside instantiation."
+ (save-excursion
+ (verilog-read-inst-module-matcher)))
+
+(defun verilog-read-inst-name ()
+ "Return instance_name when point is inside instantiation."
+ (save-excursion
+ (verilog-read-inst-backward-name)
+ (looking-at "[a-zA-Z0-9`_$]+")
+ ;; Important: don't use match string, this must work with Emacs 19 font-lock on
+ (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
+
+(defun verilog-read-module-name ()
+ "Return module name when after its ( or ;."
+ (save-excursion
+ (re-search-backward "[(;]")
+ ;; Due to "module x import y (" we must search for declaration begin
+ (verilog-re-search-backward-quick verilog-defun-re nil nil)
+ (goto-char (match-end 0))
+ (verilog-re-search-forward-quick "\\b[a-zA-Z0-9`_$]+" nil nil)
+ ;; Important: don't use match string, this must work with Emacs 19 font-lock on
+ (verilog-symbol-detick
+ (buffer-substring-no-properties (match-beginning 0) (match-end 0)) t)))
+
+(defun verilog-read-inst-param-value ()
+ "Return list of parameters and values when point is inside instantiation."
+ (save-excursion
+ (verilog-read-inst-backward-name)
+ ;; Skip over instantiation name
+ (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_$]\\|)\\)" nil nil) ; ) isn't word boundary
+ ;; If there are parameterized instantiations
+ (when (looking-at ")")
+ (let ((end-pt (point))
+ params
+ param-name paren-beg-pt param-value)
+ (verilog-backward-open-paren)
+ (while (verilog-re-search-forward-quick "\\." end-pt t)
+ (verilog-re-search-forward-quick "\\([a-zA-Z0-9`_$]\\)" nil nil)
+ (skip-chars-backward "a-zA-Z0-9'_$")
+ (looking-at "[a-zA-Z0-9`_$]+")
+ (setq param-name (buffer-substring-no-properties
+ (match-beginning 0) (match-end 0)))
+ (verilog-re-search-forward-quick "(" nil nil)
+ (setq paren-beg-pt (point))
+ (verilog-forward-close-paren)
+ (setq param-value (verilog-string-remove-spaces
+ (buffer-substring-no-properties
+ paren-beg-pt (1- (point)))))
+ (setq params (cons (list param-name param-value) params)))
+ params))))
+
+(defun verilog-read-auto-params (num-param &optional max-param)
+ "Return parameter list inside auto.
+Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
+ (let ((olist))
+ (save-excursion
+ ;; /*AUTOPUNT("parameter", "parameter")*/
+ (backward-sexp 1)
+ (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
+ (setq olist (cons (match-string 1) olist))
+ (goto-char (match-end 0))))
+ (or (eq nil num-param)
+ (<= num-param (length olist))
+ (error "%s: Expected %d parameters" (verilog-point-text) num-param))
+ (if (eq max-param nil) (setq max-param num-param))
+ (or (eq nil max-param)
+ (>= max-param (length olist))
+ (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
+ (nreverse olist)))
+
+(defun verilog-read-decls ()
+ "Compute signal declaration information for the current module at point.
+Return an array of [outputs inouts inputs wire reg assign const]."
+ (let ((end-mod-point (or (verilog-get-end-of-defun) (point-max)))
+ (functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t)
+ in-modport in-clocking in-ign-to-semi ptype ign-prop
+ sigs-in sigs-out sigs-inout sigs-var sigs-assign sigs-const
+ sigs-gparam sigs-intf sigs-modports
+ vec expect-signal keywd last-keywd newsig rvalue enum io
+ signed typedefed multidim
+ modport
+ varstack tmp)
+ ;;(if dbg (setq dbg (concat dbg (format "\n\nverilog-read-decls START PT %s END %s\n" (point) end-mod-point))))
+ (save-excursion
+ (verilog-beg-of-defun-quick)
+ (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
+ (while (< (point) end-mod-point)
+ ;;(if dbg (setq dbg (concat dbg (format "Pt %s Vec %s C%c Kwd'%s'\n" (point) vec (following-char) keywd))))
+ (cond
+ ((looking-at "//")
+ (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
+ (setq enum (match-string 2)))
+ (search-forward "\n"))
+ ((looking-at "/\\*")
+ (forward-char 2)
+ (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
+ (setq enum (match-string 2)))
+ (or (search-forward "*/")
+ (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
+ ((looking-at "(\\*")
+ ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
+ (forward-char 1)
+ (or (search-forward "*)")
+ (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
+ ((eq ?\" (following-char))
+ (or (re-search-forward "[^\\]\"" nil t) ; don't forward-char first, since we look for a non backslash first
+ (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
+ ((eq ?\; (following-char))
+ (cond (in-ign-to-semi ; Such as inside a "import ...;" in a module header
+ (setq in-ign-to-semi nil))
+ ((and in-modport (not (eq in-modport t))) ; end of a modport declaration
+ (verilog-modport-decls-set
+ in-modport
+ (verilog-decls-new sigs-out sigs-inout sigs-in
+ nil nil nil nil nil nil))
+ ;; Pop from varstack to restore state to pre-clocking
+ (setq tmp (car varstack)
+ varstack (cdr varstack)
+ sigs-out (aref tmp 0)
+ sigs-inout (aref tmp 1)
+ sigs-in (aref tmp 2))
+ (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
+ v2kargs-ok nil in-modport nil ign-prop nil))
+ (t
+ (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
+ v2kargs-ok nil in-modport nil ign-prop nil)))
+ (forward-char 1))
+ ((eq ?= (following-char))
+ (setq rvalue t newsig nil)
+ (forward-char 1))
+ ((and (eq ?, (following-char))
+ (eq paren sig-paren))
+ (setq rvalue nil)
+ (forward-char 1))
+ ;; ,'s can occur inside {} & funcs
+ ((looking-at "[{(]")
+ (setq paren (1+ paren))
+ (forward-char 1))
+ ((looking-at "[})]")
+ (setq paren (1- paren))
+ (forward-char 1)
+ (when (< paren sig-paren)
+ (setq expect-signal nil rvalue nil))) ; ) that ends variables inside v2k arg list
+ ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
+ (goto-char (match-end 0))
+ (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
+ (setcar (cdr (cdr (cdr newsig)))
+ (if (verilog-sig-memory newsig)
+ (concat (verilog-sig-memory newsig) (match-string 1))
+ (match-string-no-properties 1))))
+ (vec ; Multidimensional
+ (setq multidim (cons vec multidim))
+ (setq vec (verilog-string-replace-matches
+ "\\s-+" "" nil nil (match-string-no-properties 1))))
+ (t ; Bit width
+ (setq vec (verilog-string-replace-matches
+ "\\s-+" "" nil nil (match-string-no-properties 1))))))
+ ;; Normal or escaped identifier -- note we remember the \ if escaped
+ ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
+ (goto-char (match-end 0))
+ (setq last-keywd keywd
+ keywd (match-string-no-properties 1))
+ (when (string-match "^\\\\" (match-string 1))
+ (setq keywd (concat keywd " "))) ; Escaped ID needs space at end
+ ;; Add any :: package names to same identifier
+ (while (looking-at "\\s-*::\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
+ (goto-char (match-end 0))
+ (setq keywd (concat keywd "::" (match-string 1)))
+ (when (string-match "^\\\\" (match-string 1))
+ (setq keywd (concat keywd " ")))) ; Escaped ID needs space at end
+ (cond ((equal keywd "input")
+ (setq vec nil enum nil rvalue nil newsig nil signed nil
+ typedefed nil multidim nil ptype nil modport nil
+ expect-signal 'sigs-in io t sig-paren paren))
+ ((equal keywd "output")
+ (setq vec nil enum nil rvalue nil newsig nil signed nil
+ typedefed nil multidim nil ptype nil modport nil
+ expect-signal 'sigs-out io t sig-paren paren))
+ ((equal keywd "inout")
+ (setq vec nil enum nil rvalue nil newsig nil signed nil
+ typedefed nil multidim nil ptype nil modport nil
+ expect-signal 'sigs-inout io t sig-paren paren))
+ ((equal keywd "parameter")
+ (setq vec nil enum nil rvalue nil signed nil
+ typedefed nil multidim nil ptype nil modport nil
+ expect-signal 'sigs-gparam io t sig-paren paren))
+ ((member keywd '("wire" "reg" ; Fast
+ ;; net_type
+ "tri" "tri0" "tri1" "triand" "trior" "trireg"
+ "uwire" "wand" "wor"
+ ;; integer_atom_type
+ "byte" "shortint" "int" "longint" "integer" "time"
+ "supply0" "supply1"
+ ;; integer_vector_type - "reg" above
+ "bit" "logic"
+ ;; non_integer_type
+ "shortreal" "real" "realtime"
+ ;; data_type
+ "string" "event" "chandle"))
+ (cond (io
+ (setq typedefed
+ (if typedefed (concat typedefed " " keywd) keywd)))
+ (t (setq vec nil enum nil rvalue nil signed nil
+ typedefed nil multidim nil sig-paren paren
+ expect-signal 'sigs-var modport nil))))
+ ((equal keywd "assign")
+ (setq vec nil enum nil rvalue nil signed nil
+ typedefed nil multidim nil ptype nil modport nil
+ expect-signal 'sigs-assign sig-paren paren))
+ ((member keywd '("localparam" "genvar"))
+ (setq vec nil enum nil rvalue nil signed nil
+ typedefed nil multidim nil ptype nil modport nil
+ expect-signal 'sigs-const sig-paren paren))
+ ((member keywd '("signed" "unsigned"))
+ (setq signed keywd))
+ ((member keywd '("assert" "assume" "cover" "expect" "restrict"))
+ (setq ign-prop t))
+ ((member keywd '("class" "covergroup" "function"
+ "property" "randsequence" "sequence" "task"))
+ (unless ign-prop
+ (setq functask (1+ functask))))
+ ((member keywd '("endclass" "endgroup" "endfunction"
+ "endproperty" "endsequence" "endtask"))
+ (setq functask (1- functask)))
+ ((equal keywd "modport")
+ (setq in-modport t))
+ ((and (equal keywd "clocking")
+ (not (equal last-keywd "default")))
+ (setq in-clocking t))
+ ((equal keywd "import")
+ (if v2kargs-ok ; import in module header, not a modport import
+ (setq in-ign-to-semi t rvalue t)))
+ ((equal keywd "type")
+ (setq ptype t))
+ ((equal keywd "var"))
+ ;; Ifdef? Ignore name of define
+ ((member keywd '("`ifdef" "`ifndef" "`elsif"))
+ (setq rvalue t))
+ ;; Type?
+ ((unless ptype
+ (verilog-typedef-name-p keywd))
+ (cond (io
+ (setq typedefed
+ (if typedefed (concat typedefed " " keywd) keywd)))
+ (t (setq vec nil enum nil rvalue nil signed nil
+ typedefed keywd ; Have a type
+ multidim nil sig-paren paren
+ expect-signal 'sigs-var modport nil))))
+ ;; Interface with optional modport in v2k arglist?
+ ;; Skip over parsing modport, and take the interface name as the type
+ ((and v2kargs-ok
+ (eq paren 1)
+ (not rvalue)
+ (looking-at "\\s-*\\(\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\\)\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*"))
+ (when (match-end 2) (goto-char (match-end 2)))
+ (setq vec nil enum nil rvalue nil signed nil
+ typedefed keywd multidim nil ptype nil modport (match-string 2)
+ newsig nil sig-paren paren
+ expect-signal 'sigs-intf io t ))
+ ;; Ignore dotted LHS assignments: "assign foo.bar = z;"
+ ((looking-at "\\s-*\\.")
+ (goto-char (match-end 0))
+ (when (not rvalue)
+ (setq expect-signal nil)))
+ ;; "modport <keywd>"
+ ((and (eq in-modport t)
+ (not (member keywd verilog-keywords)))
+ (setq in-modport (verilog-modport-new keywd nil nil))
+ (setq sigs-modports (cons in-modport sigs-modports))
+ ;; Push old sig values to stack and point to new signal list
+ (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
+ varstack))
+ (setq sigs-in nil sigs-inout nil sigs-out nil))
+ ;; "modport x (clocking <keywd>)"
+ ((and in-modport in-clocking)
+ (verilog-modport-clockings-add in-modport keywd)
+ (setq in-clocking nil))
+ ;; endclocking
+ ((and in-clocking
+ (equal keywd "endclocking"))
+ (unless (eq in-clocking t)
+ (verilog-modport-decls-set
+ in-clocking
+ (verilog-decls-new sigs-out sigs-inout sigs-in
+ nil nil nil nil nil nil))
+ ;; Pop from varstack to restore state to pre-clocking
+ (setq tmp (car varstack)
+ varstack (cdr varstack)
+ sigs-out (aref tmp 0)
+ sigs-inout (aref tmp 1)
+ sigs-in (aref tmp 2)))
+ (setq in-clocking nil))
+ ;; "clocking <keywd>"
+ ((and (eq in-clocking t)
+ (not (member keywd verilog-keywords)))
+ (setq in-clocking (verilog-modport-new keywd nil nil))
+ (setq sigs-modports (cons in-clocking sigs-modports))
+ ;; Push old sig values to stack and point to new signal list
+ (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
+ varstack))
+ (setq sigs-in nil sigs-inout nil sigs-out nil))
+ ;; New signal, maybe?
+ ((and expect-signal
+ (not rvalue)
+ (eq functask 0)
+ (not (member keywd verilog-keywords)))
+ ;; Add new signal to expect-signal's variable
+ ;;(if dbg (setq dbg (concat dbg (format "Pt %s New sig %s'\n" (point) keywd))))
+ (setq newsig (verilog-sig-new keywd vec nil nil enum signed typedefed multidim modport))
+ (set expect-signal (cons newsig
+ (symbol-value expect-signal))))))
+ (t
+ (forward-char 1)))
+ (skip-syntax-forward " "))
+ ;; Return arguments
+ (setq tmp (verilog-decls-new (nreverse sigs-out)
+ (nreverse sigs-inout)
+ (nreverse sigs-in)
+ (nreverse sigs-var)
+ (nreverse sigs-modports)
+ (nreverse sigs-assign)
+ (nreverse sigs-const)
+ (nreverse sigs-gparam)
+ (nreverse sigs-intf)))
+ ;;(if dbg (verilog-decls-princ tmp))
+ tmp)))
+
+(defvar verilog-read-sub-decls-in-interfaced nil
+ "For `verilog-read-sub-decls', process next signal as under interfaced block.")
+
+(defvar verilog-read-sub-decls-gate-ios nil
+ "For `verilog-read-sub-decls', gate IO pins remaining, nil if non-primitive.")
+
+(eval-when-compile
+ ;; Prevent compile warnings; these are let's, not globals
+ ;; Do not remove the eval-when-compile
+ ;; - we want an error when we are debugging this code if they are refed.
+ (defvar sigs-in)
+ (defvar sigs-inout)
+ (defvar sigs-intf)
+ (defvar sigs-intfd)
+ (defvar sigs-out)
+ (defvar sigs-out-d)
+ (defvar sigs-out-i)
+ (defvar sigs-out-unk)
+ (defvar sigs-temp)
+ ;; These are known to be from other packages and may not be defined
+ (defvar diff-command)
+ ;; There are known to be from newer versions of Emacs
+ (defvar create-lockfiles)
+ (defvar which-func-modes))
+
+(defun verilog-read-sub-decls-type (par-values portdata)
+ "For `verilog-read-sub-decls-line', decode a signal type."
+ (let* ((type (verilog-sig-type portdata))
+ (pvassoc (assoc type par-values)))
+ (cond ((member type '("wire" "reg")) nil)
+ (pvassoc (nth 1 pvassoc))
+ (t type))))
+
+(defun verilog-read-sub-decls-sig (submoddecls par-values comment port sig vec multidim mem)
+ "For `verilog-read-sub-decls-line', add a signal."
+ ;; sig eq t to indicate .name syntax
+ ;;(message "vrsds: %s(%S)" port sig)
+ (let ((dotname (eq sig t))
+ portdata)
+ (when sig
+ (setq port (verilog-symbol-detick-denumber port))
+ (setq sig (if dotname port (verilog-symbol-detick-denumber sig)))
+ (if vec (setq vec (verilog-symbol-detick-denumber vec)))
+ (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
+ (if mem (setq mem (verilog-symbol-detick-denumber mem)))
+ (unless (or (not sig)
+ (equal sig "")) ; Ignore .foo(1'b1) assignments
+ (cond ((or (setq portdata (assoc port (verilog-decls-get-inouts submoddecls)))
+ (equal "inout" verilog-read-sub-decls-gate-ios))
+ (setq sigs-inout
+ (cons (verilog-sig-new
+ sig
+ (if dotname (verilog-sig-bits portdata) vec)
+ (concat "To/From " comment)
+ mem
+ nil
+ (verilog-sig-signed portdata)
+ (verilog-read-sub-decls-type par-values portdata)
+ multidim nil)
+ sigs-inout)))
+ ((or (setq portdata (assoc port (verilog-decls-get-outputs submoddecls)))
+ (equal "output" verilog-read-sub-decls-gate-ios))
+ (setq sigs-out
+ (cons (verilog-sig-new
+ sig
+ (if dotname (verilog-sig-bits portdata) vec)
+ (concat "From " comment)
+ mem
+ nil
+ (verilog-sig-signed portdata)
+ ;; Though ok in SV, in V2K code, propagating the
+ ;; "reg" in "output reg" upwards isn't legal.
+ ;; Also for backwards compatibility we don't propagate
+ ;; "input wire" upwards.
+ ;; See also `verilog-signals-edit-wire-reg'.
+ (verilog-read-sub-decls-type par-values portdata)
+ multidim nil)
+ sigs-out)))
+ ((or (setq portdata (assoc port (verilog-decls-get-inputs submoddecls)))
+ (equal "input" verilog-read-sub-decls-gate-ios))
+ (setq sigs-in
+ (cons (verilog-sig-new
+ sig
+ (if dotname (verilog-sig-bits portdata) vec)
+ (concat "To " comment)
+ mem
+ nil
+ (verilog-sig-signed portdata)
+ (verilog-read-sub-decls-type par-values portdata)
+ multidim nil)
+ sigs-in)))
+ ((setq portdata (assoc port (verilog-decls-get-interfaces submoddecls)))
+ (setq sigs-intf
+ (cons (verilog-sig-new
+ sig
+ (if dotname (verilog-sig-bits portdata) vec)
+ (concat "To/From " comment)
+ mem
+ nil
+ (verilog-sig-signed portdata)
+ (verilog-read-sub-decls-type par-values portdata)
+ multidim nil)
+ sigs-intf)))
+ ((setq portdata (and verilog-read-sub-decls-in-interfaced
+ (assoc port (verilog-decls-get-vars submoddecls))))
+ (setq sigs-intfd
+ (cons (verilog-sig-new
+ sig
+ (if dotname (verilog-sig-bits portdata) vec)
+ (concat "To/From " comment)
+ mem
+ nil
+ (verilog-sig-signed portdata)
+ (verilog-read-sub-decls-type par-values portdata)
+ multidim nil)
+ sigs-intf)))
+ ;; (t -- warning pin isn't defined.) ; Leave for lint tool
+ )))))
+
+(defun verilog-read-sub-decls-expr (submoddecls par-values comment port expr)
+ "For `verilog-read-sub-decls-line', parse a subexpression and add signals."
+ ;;(message "vrsde: `%s'" expr)
+ ;; Replace special /*[....]*/ comments inserted by verilog-auto-inst-port
+ (setq expr (verilog-string-replace-matches "/\\*\\(\\.?\\[[^*]+\\]\\)\\*/" "\\1" nil nil expr))
+ ;; Remove front operators
+ (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
+ ;;
+ (cond
+ ;; {..., a, b} requires us to recurse on a,b
+ ;; To support {#{},{#{a,b}} we'll just split everything on [{},]
+ ((string-match "^\\s-*{\\(.*\\)}\\s-*$" expr)
+ (unless verilog-auto-ignore-concat
+ (let ((mlst (split-string (match-string 1 expr) "[{},]"))
+ mstr)
+ (while (setq mstr (pop mlst))
+ (verilog-read-sub-decls-expr submoddecls par-values comment port mstr)))))
+ (t
+ (let (sig vec multidim mem)
+ ;; Remove leading reduction operators, etc
+ (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
+ ;;(message "vrsde-ptop: `%s'" expr)
+ (cond ; Find \signal. Final space is part of escaped signal name
+ ((string-match "^\\s-*\\(\\\\[^ \t\n\f]+\\s-\\)" expr)
+ ;;(message "vrsde-s: `%s'" (match-string 1 expr))
+ (setq sig (match-string 1 expr)
+ expr (substring expr (match-end 0))))
+ ;; Find signal
+ ((string-match "^\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" expr)
+ ;;(message "vrsde-s: `%s'" (match-string 1 expr))
+ (setq sig (verilog-string-remove-spaces (match-string 1 expr))
+ expr (substring expr (match-end 0)))))
+ ;; Find [vector] or [multi][multi][multi][vector]
+ (while (string-match "^\\s-*\\(\\[[^]]+\\]\\)" expr)
+ ;;(message "vrsde-v: `%s'" (match-string 1 expr))
+ (when vec (setq multidim (cons vec multidim)))
+ (setq vec (match-string 1 expr)
+ expr (substring expr (match-end 0))))
+ ;; Find .[unpacked_memory] or .[unpacked][unpacked]...
+ (while (string-match "^\\s-*\\.\\(\\(\\[[^]]+\\]\\)+\\)" expr)
+ ;;(message "vrsde-m: `%s'" (match-string 1 expr))
+ (setq mem (match-string 1 expr)
+ expr (substring expr (match-end 0))))
+ ;; If found signal, and nothing unrecognized, add the signal
+ ;;(message "vrsde-rem: `%s'" expr)
+ (when (and sig (string-match "^\\s-*$" expr))
+ (verilog-read-sub-decls-sig submoddecls par-values comment port sig vec multidim mem))))))
+
+(defun verilog-read-sub-decls-line (submoddecls par-values comment)
+ "For `verilog-read-sub-decls', read lines of port defs until none match.
+Inserts the list of signals found, using submodi to look up each port."
+ (let (done port)
+ (save-excursion
+ (forward-line 1)
+ (while (not done)
+ ;; Get port name
+ (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
+ (setq port (match-string-no-properties 1))
+ (goto-char (match-end 0)))
+ ;; .\escaped (
+ ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
+ (setq port (concat (match-string-no-properties 1) " ")) ; escaped id's need trailing space
+ (goto-char (match-end 0)))
+ ;; .name
+ ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*[,)/]")
+ (verilog-read-sub-decls-sig
+ submoddecls par-values comment (match-string-no-properties 1) t ; sig==t for .name
+ nil nil nil) ; vec multidim mem
+ (setq port nil))
+ ;; .\escaped_name
+ ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*[,)/]")
+ (verilog-read-sub-decls-sig
+ submoddecls par-values comment (concat (match-string-no-properties 1) " ") t ; sig==t for .name
+ nil nil nil) ; vec multidim mem
+ (setq port nil))
+ ;; random
+ ((looking-at "\\s-*\\.[^(]*(")
+ (setq port nil) ; skip this line
+ (goto-char (match-end 0)))
+ (t
+ (setq port nil done t))) ; Unknown, ignore rest of line
+ ;; Get signal name. Point is at the first-non-space after (
+ ;; We intentionally ignore (non-escaped) signals with .s in them
+ ;; this prevents AUTOWIRE etc from noticing hierarchical sigs.
+ (when port
+ (cond ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)")
+ (verilog-read-sub-decls-sig
+ submoddecls par-values comment port
+ (verilog-string-remove-spaces (match-string-no-properties 1)) ; sig
+ nil nil nil)) ; vec multidim mem
+ ;;
+ ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
+ (verilog-read-sub-decls-sig
+ submoddecls par-values comment port
+ (verilog-string-remove-spaces (match-string-no-properties 1)) ; sig
+ (match-string-no-properties 2) nil nil)) ; vec multidim mem
+ ;; Fastpath was above looking-at's.
+ ;; For something more complicated invoke a parser
+ ((looking-at "[^)]+")
+ (verilog-read-sub-decls-expr
+ submoddecls par-values comment port
+ (buffer-substring-no-properties
+ (point) (1- (progn (search-backward "(") ; start at (
+ (verilog-forward-sexp-ign-cmt 1)
+ (point)))))))) ; expr
+ ;;
+ (forward-line 1)))))
+;;(verilog-read-sub-decls-line (verilog-subdecls-new nil nil nil nil nil) nil "Cmt")
+
+(defun verilog-read-sub-decls-gate (submoddecls par-values comment submod end-inst-point)
+ "For `verilog-read-sub-decls', read lines of UDP gate decl until none match.
+Inserts the list of signals found."
+ (save-excursion
+ (let ((iolist (cdr (assoc submod verilog-gate-ios))))
+ (while (< (point) end-inst-point)
+ ;; Get primitive's signal name, as will never have port, and no trailing )
+ (cond ((looking-at "//")
+ (search-forward "\n"))
+ ((looking-at "/\\*")
+ (or (search-forward "*/")
+ (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
+ ((looking-at "(\\*")
+ ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
+ (forward-char 1)
+ (or (search-forward "*)")
+ (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
+ ;; On pins, parse and advance to next pin
+ ;; Looking at pin, but *not* an // Output comment, or ) to end the inst
+ ((looking-at "\\s-*[a-zA-Z0-9`_$({}\\\\][^,]*")
+ (goto-char (match-end 0))
+ (setq verilog-read-sub-decls-gate-ios (or (car iolist) "input")
+ iolist (cdr iolist))
+ (verilog-read-sub-decls-expr
+ submoddecls par-values comment "primitive_port"
+ (match-string 0)))
+ (t
+ (forward-char 1)
+ (skip-syntax-forward " ")))))))
+
+(defun verilog-read-sub-decls ()
+ "Internally parse signals going to modules under this module.
+Return an array of [ outputs inouts inputs ] signals for modules that are
+instantiated in this module. For example if declare A A (.B(SIG)) and SIG
+is an output, then SIG will be included in the list.
+
+This only works on instantiations created with /*AUTOINST*/ converted by
+\\[verilog-auto-inst]. Otherwise, it would have to read in the whole
+component library to determine connectivity of the design.
+
+One work around for this problem is to manually create // Inputs and //
+Outputs comments above subcell signals, for example:
+
+ module ModuleName (
+ // Outputs
+ .out (out),
+ // Inputs
+ .in (in));"
+ (save-excursion
+ (let ((end-mod-point (verilog-get-end-of-defun))
+ st-point end-inst-point par-values
+ ;; below 3 modified by verilog-read-sub-decls-line
+ sigs-out sigs-inout sigs-in sigs-intf sigs-intfd)
+ (verilog-beg-of-defun-quick)
+ (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
+ (save-excursion
+ (goto-char (match-beginning 0))
+ (setq par-values (and verilog-auto-inst-param-value
+ verilog-auto-inst-param-value-type
+ (verilog-read-inst-param-value)))
+ (unless (verilog-inside-comment-or-string-p)
+ ;; Attempt to snarf a comment
+ (let* ((submod (verilog-read-inst-module))
+ (inst (verilog-read-inst-name))
+ (subprim (member submod verilog-gate-keywords))
+ (comment (concat inst " of " submod ".v"))
+ submodi submoddecls)
+ (cond
+ (subprim
+ (setq submodi `primitive
+ submoddecls (verilog-decls-new nil nil nil nil nil nil nil nil nil)
+ comment (concat inst " of " submod))
+ (verilog-backward-open-paren)
+ (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
+ (point))
+ st-point (point))
+ (forward-char 1)
+ (verilog-read-sub-decls-gate submoddecls par-values comment submod end-inst-point))
+ ;; Non-primitive
+ (t
+ (when (setq submodi (verilog-modi-lookup submod t))
+ (setq submoddecls (verilog-modi-get-decls submodi)
+ verilog-read-sub-decls-gate-ios nil)
+ (verilog-backward-open-paren)
+ (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
+ (point))
+ st-point (point))
+ ;; This could have used a list created by verilog-auto-inst
+ ;; However I want it to be runnable even on user's manually added signals
+ (let ((verilog-read-sub-decls-in-interfaced t))
+ (while (re-search-forward "\\s *(?\\s *// Interfaced" end-inst-point t)
+ (verilog-read-sub-decls-line submoddecls par-values comment))) ; Modifies sigs-ifd
+ (goto-char st-point)
+ (while (re-search-forward "\\s *(?\\s *// Interfaces" end-inst-point t)
+ (verilog-read-sub-decls-line submoddecls par-values comment)) ; Modifies sigs-out
+ (goto-char st-point)
+ (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
+ (verilog-read-sub-decls-line submoddecls par-values comment)) ; Modifies sigs-out
+ (goto-char st-point)
+ (while (re-search-forward "\\s *(?\\s *// Inouts" end-inst-point t)
+ (verilog-read-sub-decls-line submoddecls par-values comment)) ; Modifies sigs-inout
+ (goto-char st-point)
+ (while (re-search-forward "\\s *(?\\s *// Inputs" end-inst-point t)
+ (verilog-read-sub-decls-line submoddecls par-values comment)) ; Modifies sigs-in
+ )))))))
+ ;; Combine duplicate bits
+ ;;(setq rr (vector sigs-out sigs-inout sigs-in))
+ (verilog-subdecls-new
+ (verilog-signals-combine-bus (nreverse sigs-out))
+ (verilog-signals-combine-bus (nreverse sigs-inout))
+ (verilog-signals-combine-bus (nreverse sigs-in))
+ (verilog-signals-combine-bus (nreverse sigs-intf))
+ (verilog-signals-combine-bus (nreverse sigs-intfd))))))
+
+(defun verilog-read-inst-pins ()
+ "Return an array of [ pins ] for the current instantiation at point.
+For example if declare A A (.B(SIG)) then B will be included in the list."
+ (save-excursion
+ (let ((end-mod-point (point)) ; presume at /*AUTOINST*/ point
+ pins pin)
+ (verilog-backward-open-paren)
+ (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
+ (setq pin (match-string 1))
+ (unless (verilog-inside-comment-or-string-p)
+ (setq pins (cons (list pin) pins))
+ (when (looking-at "(")
+ (verilog-forward-sexp-ign-cmt 1))))
+ (vector pins))))
+
+(defun verilog-read-arg-pins ()
+ "Return an array of [ pins ] for the current argument declaration at point."
+ (save-excursion
+ (let ((end-mod-point (point)) ; presume at /*AUTOARG*/ point
+ pins pin)
+ (verilog-backward-open-paren)
+ (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
+ (setq pin (match-string 1))
+ (unless (verilog-inside-comment-or-string-p)
+ (setq pins (cons (list pin) pins))))
+ (vector pins))))
+
+(defun verilog-read-auto-constants (beg end-mod-point)
+ "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
+ ;; Insert new
+ (save-excursion
+ (let (sig-list tpl-end-pt)
+ (goto-char beg)
+ (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
+ (if (not (looking-at "\\s *("))
+ (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
+ (search-forward "(" end-mod-point)
+ (setq tpl-end-pt (save-excursion
+ (backward-char 1)
+ (verilog-forward-sexp-cmt 1) ; Moves to paren that closes argdecl's
+ (backward-char 1)
+ (point)))
+ (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
+ (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
+ sig-list)))
+
+(defvar verilog-cache-has-lisp nil "True if any AUTO_LISP in buffer.")
+(make-variable-buffer-local 'verilog-cache-has-lisp)
+
+(defun verilog-read-auto-lisp-present ()
+ "Set `verilog-cache-has-lisp' if any AUTO_LISP in this buffer."
+ (save-excursion
+ (goto-char (point-min))
+ (setq verilog-cache-has-lisp (re-search-forward "\\<AUTO_LISP(" nil t))))
+
+(defun verilog-read-auto-lisp (start end)
+ "Look for and evaluate an AUTO_LISP between START and END.
+Must call `verilog-read-auto-lisp-present' before this function."
+ ;; This function is expensive for large buffers, so we cache if any AUTO_LISP exists
+ (when verilog-cache-has-lisp
+ (save-excursion
+ (goto-char start)
+ (while (re-search-forward "\\<AUTO_LISP(" end t)
+ (backward-char)
+ (let* ((beg-pt (prog1 (point)
+ (verilog-forward-sexp-cmt 1))) ; Closing paren
+ (end-pt (point))
+ (verilog-in-hooks t))
+ (eval-region beg-pt end-pt nil))))))
+
+(defun verilog-read-always-signals-recurse
+ (exit-keywd rvalue temp-next)
+ "Recursive routine for parentheses/bracket matching.
+EXIT-KEYWD is expression to stop at, nil if top level.
+RVALUE is true if at right hand side of equal.
+IGNORE-NEXT is true to ignore next token, fake from inside case statement."
+ (let* ((semi-rvalue (equal "endcase" exit-keywd)) ; true if after a ; we are looking for rvalue
+ keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-list end-else-check
+ ignore-next)
+ ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue temp-next))))
+ (while (not (or (eobp) gotend))
+ (cond
+ ((looking-at "//")
+ (search-forward "\n"))
+ ((looking-at "/\\*")
+ (or (search-forward "*/")
+ (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
+ ((looking-at "(\\*")
+ ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
+ (forward-char 1)
+ (or (search-forward "*)")
+ (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
+ (t (setq keywd (buffer-substring-no-properties
+ (point)
+ (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
+ (forward-char 1))
+ (point)))
+ sig-last-tolk sig-tolk
+ sig-tolk nil)
+ ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S gs=%S\n" (point) keywd rvalue ignore-next end-else-check got-sig))))
+ (cond
+ ((equal keywd "\"")
+ (or (re-search-forward "[^\\]\"" nil t)
+ (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
+ ;; else at top level loop, keep parsing
+ ((and end-else-check (equal keywd "else"))
+ ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
+ ;; no forward movement, want to see else in lower loop
+ (setq end-else-check nil))
+ ;; End at top level loop
+ ((and end-else-check (looking-at "[^ \t\n\f]"))
+ ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
+ (setq gotend t))
+ ;; Final statement?
+ ((and exit-keywd (and (equal keywd exit-keywd)
+ (not (looking-at "::"))))
+ (setq gotend t)
+ (forward-char (length keywd)))
+ ;; Standard tokens...
+ ((equal keywd ";")
+ (setq ignore-next nil rvalue semi-rvalue)
+ ;; Final statement at top level loop?
+ (when (not exit-keywd)
+ ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
+ (setq end-else-check t))
+ (forward-char 1))
+ ((equal keywd "'")
+ (if (looking-at "'[sS]?[hdxboHDXBO]?[ \t]*[0-9a-fA-F_xzXZ?]+")
+ (goto-char (match-end 0))
+ (forward-char 1)))
+ ((equal keywd ":") ; Case statement, begin/end label, x?y:z
+ (cond ((looking-at "::")
+ (forward-char 1)) ; Another forward-char below
+ ((equal "endcase" exit-keywd) ; case x: y=z; statement next
+ (setq ignore-next nil rvalue nil))
+ ((equal "?" exit-keywd) ; x?y:z rvalue
+ ) ; NOP
+ ((equal "]" exit-keywd) ; [x:y] rvalue
+ ) ; NOP
+ (got-sig ; label: statement
+ (setq ignore-next nil rvalue semi-rvalue got-sig nil))
+ ((not rvalue) ; begin label
+ (setq ignore-next t rvalue nil)))
+ (forward-char 1))
+ ((equal keywd "=")
+ (when got-sig
+ ;;(if dbg (setq dbg (concat dbg (format "\t\tequal got-sig=%S got-list=%s\n" got-sig got-list))))
+ (set got-list (cons got-sig (symbol-value got-list)))
+ (setq got-sig nil))
+ (when (not rvalue)
+ (if (eq (char-before) ?< )
+ (setq sigs-out-d (append sigs-out-d sigs-out-unk)
+ sigs-out-unk nil)
+ (setq sigs-out-i (append sigs-out-i sigs-out-unk)
+ sigs-out-unk nil)))
+ (setq ignore-next nil rvalue t)
+ (forward-char 1))
+ ((equal keywd "?")
+ (forward-char 1)
+ (verilog-read-always-signals-recurse ":" rvalue nil))
+ ((equal keywd "[")
+ (forward-char 1)
+ (verilog-read-always-signals-recurse "]" t nil))
+ ((equal keywd "(")
+ (forward-char 1)
+ (cond (sig-last-tolk ; Function call; zap last signal
+ (setq got-sig nil)))
+ (cond ((equal last-keywd "for")
+ ;; temp-next: Variables on LHS are lvalues, but generally we want
+ ;; to ignore them, assuming they are loop increments
+ (verilog-read-always-signals-recurse ";" nil t)
+ (verilog-read-always-signals-recurse ";" t nil)
+ (verilog-read-always-signals-recurse ")" nil nil))
+ (t (verilog-read-always-signals-recurse ")" t nil))))
+ ((equal keywd "begin")
+ (skip-syntax-forward "w_")
+ (verilog-read-always-signals-recurse "end" nil nil)
+ ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
+ (setq ignore-next nil rvalue semi-rvalue)
+ (if (not exit-keywd) (setq end-else-check t)))
+ ((member keywd '("case" "casex" "casez" "randcase"))
+ (skip-syntax-forward "w_")
+ (verilog-read-always-signals-recurse "endcase" t nil)
+ (setq ignore-next nil rvalue semi-rvalue)
+ (if (not exit-keywd) (setq gotend t))) ; top level begin/end
+ ((string-match "^[$`a-zA-Z_]" keywd) ; not exactly word constituent
+ (cond ((member keywd '("`ifdef" "`ifndef" "`elsif"))
+ (setq ignore-next t))
+ ((or ignore-next
+ (member keywd verilog-keywords)
+ (string-match "^\\$" keywd)) ; PLI task
+ (setq ignore-next nil))
+ (t
+ (setq keywd (verilog-symbol-detick-denumber keywd))
+ (when got-sig
+ (set got-list (cons got-sig (symbol-value got-list)))
+ ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S got-list=%S\n" got-sig got-list))))
+ )
+ (setq got-list (cond (temp-next 'sigs-temp)
+ (rvalue 'sigs-in)
+ (t 'sigs-out-unk))
+ got-sig (if (or (not keywd)
+ (assoc keywd (symbol-value got-list)))
+ nil (list keywd nil nil))
+ temp-next nil
+ sig-tolk t)))
+ (skip-chars-forward "a-zA-Z0-9$_.%`"))
+ (t
+ (forward-char 1)))
+ ;; End of non-comment token
+ (setq last-keywd keywd)))
+ (skip-syntax-forward " "))
+ ;; Append the final pending signal
+ (when got-sig
+ ;;(if dbg (setq dbg (concat dbg (format "\t\tfinal got-sig=%S got-list=%s\n" got-sig got-list))))
+ (set got-list (cons got-sig (symbol-value got-list)))
+ (setq got-sig nil))
+ ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
+ ))
+
+(defun verilog-read-always-signals ()
+ "Parse always block at point and return list of (outputs inout inputs)."
+ (save-excursion
+ (let* (;(dbg "")
+ sigs-out-d sigs-out-i sigs-out-unk sigs-temp sigs-in)
+ (verilog-read-always-signals-recurse nil nil nil)
+ (setq sigs-out-i (append sigs-out-i sigs-out-unk)
+ sigs-out-unk nil)
+ ;;(if dbg (with-current-buffer (get-buffer-create "*vl-dbg*") (delete-region (point-min) (point-max)) (insert dbg) (setq dbg "")))
+ ;; Return what was found
+ (verilog-alw-new sigs-out-d sigs-out-i sigs-temp sigs-in))))
+
+(defun verilog-read-instants ()
+ "Parse module at point and return list of ( ( file instance ) ... )."
+ (verilog-beg-of-defun-quick)
+ (let* ((end-mod-point (verilog-get-end-of-defun))
+ (state nil)
+ (instants-list nil))
+ (save-excursion
+ (while (< (point) end-mod-point)
+ ;; Stay at level 0, no comments
+ (while (progn
+ (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
+ (or (> (car state) 0) ; in parens
+ (nth 5 state) ; comment
+ ))
+ (forward-line 1))
+ (beginning-of-line)
+ (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
+ ;;(if (looking-at "^\\(.+\\)$")
+ (let ((module (match-string 1))
+ (instant (match-string 2)))
+ (if (not (member module verilog-keywords))
+ (setq instants-list (cons (list module instant) instants-list)))))
+ (forward-line 1)))
+ instants-list))
+
+
+(defun verilog-read-auto-template-middle ()
+ "With point in middle of an AUTO_TEMPLATE, parse it.
+Returns REGEXP and list of ( (signal_name connection_name)... )."
+ (save-excursion
+ ;; Find beginning
+ (let ((tpl-regexp "\\([0-9]+\\)")
+ (lineno -1) ; -1 to offset for the AUTO_TEMPLATE's newline
+ (templateno 0)
+ tpl-sig-list tpl-wild-list tpl-end-pt rep)
+ ;; Parse "REGEXP"
+ ;; We reserve @"..." for future lisp expressions that evaluate
+ ;; once-per-AUTOINST
+ (when (looking-at "\\s-*\"\\([^\"]*\\)\"")
+ (setq tpl-regexp (match-string 1))
+ (goto-char (match-end 0)))
+ (search-forward "(")
+ ;; Parse lines in the template
+ (when (or verilog-auto-inst-template-numbers
+ verilog-auto-template-warn-unused)
+ (save-excursion
+ (let ((pre-pt (point)))
+ (goto-char (point-min))
+ (while (search-forward "AUTO_TEMPLATE" pre-pt t)
+ (setq templateno (1+ templateno)))
+ (while (< (point) pre-pt)
+ (forward-line 1)
+ (setq lineno (1+ lineno))))))
+ (setq tpl-end-pt (save-excursion
+ (backward-char 1)
+ (verilog-forward-sexp-cmt 1) ; Moves to paren that closes argdecl's
+ (backward-char 1)
+ (point)))
+ ;;
+ (while (< (point) tpl-end-pt)
+ (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
+ (setq tpl-sig-list
+ (cons (list
+ (match-string-no-properties 1)
+ (match-string-no-properties 2)
+ templateno lineno)
+ tpl-sig-list))
+ (goto-char (match-end 0)))
+ ;; Regexp form??
+ ((looking-at
+ ;; Regexp bug in XEmacs disallows ][ inside [], and wants + last
+ "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
+ (setq rep (match-string-no-properties 3))
+ (goto-char (match-end 0))
+ (setq tpl-wild-list
+ (cons (list
+ (concat "^"
+ (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
+ (match-string 1))
+ "$")
+ rep
+ templateno lineno)
+ tpl-wild-list)))
+ ((looking-at "[ \t\f]+")
+ (goto-char (match-end 0)))
+ ((looking-at "\n")
+ (setq lineno (1+ lineno))
+ (goto-char (match-end 0)))
+ ((looking-at "//")
+ (search-forward "\n")
+ (setq lineno (1+ lineno)))
+ ((looking-at "/\\*")
+ (forward-char 2)
+ (or (search-forward "*/")
+ (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
+ (t
+ (error "%s: AUTO_TEMPLATE parsing error: %s"
+ (verilog-point-text)
+ (progn (looking-at ".*$") (match-string 0))))))
+ ;; Return
+ (vector tpl-regexp
+ (list tpl-sig-list tpl-wild-list)))))
+
+(defun verilog-read-auto-template (module)
+ "Look for an auto_template for the instantiation of the given MODULE.
+If found returns `verilog-read-auto-template-inside' structure."
+ (save-excursion
+ ;; Find beginning
+ (let ((pt (point)))
+ ;; Note this search is expensive, as we hunt from mod-begin to point
+ ;; for every instantiation. Likewise in verilog-read-auto-lisp.
+ ;; So, we look first for an exact string rather than a slow regexp.
+ ;; Someday we may keep a cache of every template, but this would also
+ ;; need to record the relative position of each AUTOINST, as multiple
+ ;; templates exist for each module, and we're inserting lines.
+ (cond ((or
+ ;; See also regexp in `verilog-auto-template-lint'
+ (verilog-re-search-backward-substr
+ "AUTO_TEMPLATE"
+ (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
+ ;; Also try forward of this AUTOINST
+ ;; This is for historical support; this isn't speced as working
+ (progn
+ (goto-char pt)
+ (verilog-re-search-forward-substr
+ "AUTO_TEMPLATE"
+ (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
+ (goto-char (match-end 0))
+ (verilog-read-auto-template-middle))
+ ;; If no template found
+ (t (vector "" nil))))))
+;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
+
+(defvar verilog-auto-template-hits nil "Successful lookups with `verilog-read-auto-template-hit'.")
+(make-variable-buffer-local 'verilog-auto-template-hits)
+
+(defun verilog-read-auto-template-init ()
+ "Initialize `verilog-read-auto-template'."
+ (when (eval-when-compile (fboundp 'make-hash-table)) ; else feature not allowed
+ (when verilog-auto-template-warn-unused
+ (setq verilog-auto-template-hits
+ (make-hash-table :test 'equal :rehash-size 4.0)))))
+
+(defun verilog-read-auto-template-hit (tpl-ass)
+ "Record that TPL-ASS template from `verilog-read-auto-template' was used."
+ (when (eval-when-compile (fboundp 'make-hash-table)) ; else feature not allowed
+ (when verilog-auto-template-warn-unused
+ (unless verilog-auto-template-hits
+ (verilog-read-auto-template-init))
+ (puthash (vector (nth 2 tpl-ass) (nth 3 tpl-ass)) t
+ verilog-auto-template-hits))))
+
+(defun verilog-set-define (defname defvalue &optional buffer enumname)
+ "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
+Optionally associate it with the specified enumeration ENUMNAME."
+ (with-current-buffer (or buffer (current-buffer))
+ ;; Namespace intentionally short for AUTOs and compatibility
+ (let ((mac (intern (concat "vh-" defname))))
+ ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
+ ;; Need to define to a constant if no value given
+ (set (make-local-variable mac)
+ (if (equal defvalue "") "1" defvalue)))
+ (if enumname
+ ;; Namespace intentionally short for AUTOs and compatibility
+ (let ((enumvar (intern (concat "venum-" enumname))))
+ ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
+ (unless (boundp enumvar) (set enumvar nil))
+ (add-to-list (make-local-variable enumvar) defname)))))
+
+(defun verilog-read-defines (&optional filename recurse subcall)
+ "Read \\=`defines and parameters for the current file, or optional FILENAME.
+If the filename is provided, `verilog-library-flags' will be used to
+resolve it. If optional RECURSE is non-nil, recurse through \\=`includes.
+
+Localparams must be simple assignments to constants, or have their own
+\"localparam\" label rather than a list of localparams. Thus:
+
+ localparam X = 5, Y = 10; // Ok
+ localparam X = {1\\='b1, 2\\='h2}; // Ok
+ localparam X = {1\\='b1, 2\\='h2}, Y = 10; // Bad, make into 2 localparam lines
+
+Defines must be simple text substitutions, one on a line, starting
+at the beginning of the line. Any ifdefs or multiline comments around the
+define are ignored.
+
+Defines are stored inside Emacs variables using the name
+vh-{definename}.
+
+Localparams define what symbols are constants so that AUTOSENSE
+will not include them in sensitivity lists. However any
+parameters in the include file are not considered ports in the
+including file, thus will not appear in AUTOINSTPARAM lists for a
+parent module..
+
+The file variables feature can be used to set defines that
+`verilog-mode' can see; put at the *END* of your file something
+like:
+
+ // Local Variables:
+ // vh-macro:\"macro_definition\"
+ // End:
+
+If macros are defined earlier in the same file and you want their values,
+you can read them automatically with:
+
+ // Local Variables:
+ // verilog-auto-read-includes:t
+ // End:
+
+Or a more specific alternative example, which requires having
+`enable-local-eval' non-nil:
+
+ // Local Variables:
+ // eval:(verilog-read-defines)
+ // eval:(verilog-read-defines \"group_standard_includes.v\")
+ // End:
+
+Note these are only read when the file is first visited, you must use
+\\[find-alternate-file] RET to have these take effect after editing them!
+
+If you want to disable the \"Process `eval' or hook local variables\"
+warning message, you need to add to your init file:
+
+ (setq enable-local-eval t)"
+ (let ((origbuf (current-buffer)))
+ (save-excursion
+ (unless subcall (verilog-getopt-flags))
+ (when filename
+ (let ((fns (verilog-library-filenames filename (buffer-file-name))))
+ (if fns
+ (set-buffer (find-file-noselect (car fns)))
+ (error "%s: Can't find verilog-read-defines file: %s"
+ (verilog-point-text) filename))))
+ (when recurse
+ (goto-char (point-min))
+ (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
+ (let ((inc (verilog-string-replace-matches
+ "\"" "" nil nil (match-string-no-properties 1))))
+ (unless (verilog-inside-comment-or-string-p)
+ (verilog-read-defines inc recurse t)))))
+ ;; Read `defines
+ ;; note we don't use verilog-re... it's faster this way, and that
+ ;; function has problems when comments are at the end of the define
+ (goto-char (point-min))
+ (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
+ (let ((defname (match-string-no-properties 1))
+ (defvalue (match-string-no-properties 2)))
+ (unless (verilog-inside-comment-or-string-p (match-beginning 0))
+ (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
+ (verilog-set-define defname defvalue origbuf))))
+ ;; Hack: Read parameters
+ (goto-char (point-min))
+ (while (re-search-forward
+ "^\\s-*\\(parameter\\|localparam\\)\\(\\s-*\\[[^]]*\\]\\)?\\s-*" nil t)
+ (let (enumname)
+ ;; The primary way of getting defines is verilog-read-decls
+ ;; However, that isn't called yet for included files, so we'll add another scheme
+ (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
+ (setq enumname (match-string-no-properties 2)))
+ (forward-comment 99999)
+ (while (looking-at (concat "\\s-*,?\\s-*\\(?:/[/*].*?$\\)?\\s-*\\([a-zA-Z0-9_$]+\\)"
+ "\\s-*=\\s-*\\([^;,]*\\),?\\s-*\\(/[/*].*?$\\)?\\s-*"))
+ (unless (verilog-inside-comment-or-string-p (match-beginning 0))
+ (verilog-set-define (match-string-no-properties 1)
+ (match-string-no-properties 2) origbuf enumname))
+ (goto-char (match-end 0))
+ (forward-comment 99999)))))))
+
+(defun verilog-read-includes ()
+ "Read \\=`includes for the current file.
+This will find all of the \\=`includes which are at the beginning of lines,
+ignoring any ifdefs or multiline comments around them.
+`verilog-read-defines' is then performed on the current and each included
+file.
+
+It is often useful put at the *END* of your file something like:
+
+ // Local Variables:
+ // verilog-auto-read-includes:t
+ // End:
+
+Or the equivalent longer version, which requires having
+`enable-local-eval' non-nil:
+
+ // Local Variables:
+ // eval:(verilog-read-defines)
+ // eval:(verilog-read-includes)
+ // End:
+
+Note includes are only read when the file is first visited, you must use
+\\[find-alternate-file] RET to have these take effect after editing them!
+
+It is good to get in the habit of including all needed files in each .v
+file that needs it, rather than waiting for compile time. This will aid
+this process, Verilint, and readability. To prevent defining the same
+variable over and over when many modules are compiled together, put a test
+around the inside each include file:
+
+foo.v (an include file):
+ \\=`ifdef _FOO_V // include if not already included
+ \\=`else
+ \\=`define _FOO_V
+ ... contents of file
+ \\=`endif // _FOO_V"
+ ;;slow: (verilog-read-defines nil t)
+ (save-excursion
+ (verilog-getopt-flags)
+ (goto-char (point-min))
+ (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
+ (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
+ (verilog-read-defines inc nil t)))))
+
+(defun verilog-read-signals (&optional start end)
+ "Return a simple list of all possible signals in the file.
+Bounded by optional region from START to END. Overly aggressive but fast.
+Some macros and such are also found and included. For dinotrace.el."
+ (let (sigs-all keywd)
+ (progn;save-excursion
+ (goto-char (or start (point-min)))
+ (setq end (or end (point-max)))
+ (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
+ (forward-char -1)
+ (cond
+ ((looking-at "//")
+ (search-forward "\n"))
+ ((looking-at "/\\*")
+ (search-forward "*/"))
+ ((looking-at "(\\*")
+ (or (looking-at "(\\*\\s-*)") ; It's an "always @ (*)"
+ (search-forward "*)")))
+ ((eq ?\" (following-char))
+ (re-search-forward "[^\\]\"")) ; don't forward-char first, since we look for a non backslash first
+ ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
+ (goto-char (match-end 0))
+ (setq keywd (match-string-no-properties 1))
+ (or (member keywd verilog-keywords)
+ (member keywd sigs-all)
+ (setq sigs-all (cons keywd sigs-all))))
+ (t (forward-char 1))))
+ ;; Return list
+ sigs-all)))
+
+;;
+;; Argument file parsing
+;;
+
+(defun verilog-getopt (arglist)
+ "Parse -f, -v etc arguments in ARGLIST list or string."
+ (unless (listp arglist) (setq arglist (list arglist)))
+ (let ((space-args '())
+ arg next-param)
+ ;; Split on spaces, so users can pass whole command lines
+ (while arglist
+ (setq arg (car arglist)
+ arglist (cdr arglist))
+ (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
+ (setq space-args (append space-args
+ (list (match-string-no-properties 1 arg))))
+ (setq arg (match-string 2 arg))))
+ ;; Parse arguments
+ (while space-args
+ (setq arg (car space-args)
+ space-args (cdr space-args))
+ (cond
+ ;; Need another arg
+ ((equal arg "-f")
+ (setq next-param arg))
+ ((equal arg "-v")
+ (setq next-param arg))
+ ((equal arg "-y")
+ (setq next-param arg))
+ ;; +libext+(ext1)+(ext2)...
+ ((string-match "^\\+libext\\+\\(.*\\)" arg)
+ (setq arg (match-string 1 arg))
+ (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
+ (verilog-add-list-unique `verilog-library-extensions
+ (match-string 1 arg))
+ (setq arg (match-string 2 arg))))
+ ;;
+ ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ; -Ddefine=val
+ (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ; -Ddefine
+ (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ; +define+val
+ (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ; +define+define
+ (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
+ ;;
+ ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ; +incdir+dir
+ (string-match "^-I\\(.*\\)" arg)) ; -Idir
+ (verilog-add-list-unique `verilog-library-directories
+ (match-string 1 (substitute-in-file-name arg))))
+ ;; Ignore
+ ((equal "+librescan" arg))
+ ((string-match "^-U\\(.*\\)" arg)) ; -Udefine
+ ;; Second parameters
+ ((equal next-param "-f")
+ (setq next-param nil)
+ (verilog-getopt-file (substitute-in-file-name arg)))
+ ((equal next-param "-v")
+ (setq next-param nil)
+ (verilog-add-list-unique `verilog-library-files
+ (substitute-in-file-name arg)))
+ ((equal next-param "-y")
+ (setq next-param nil)
+ (verilog-add-list-unique `verilog-library-directories
+ (substitute-in-file-name arg)))
+ ;; Filename
+ ((string-match "^[^-+]" arg)
+ (verilog-add-list-unique `verilog-library-files
+ (substitute-in-file-name arg)))
+ ;; Default - ignore; no warning
+ ))))
+;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
+
+(defun verilog-getopt-file (filename)
+ "Read Verilog options from the specified FILENAME."
+ (save-excursion
+ (let ((fns (verilog-library-filenames filename (buffer-file-name)))
+ (orig-buffer (current-buffer))
+ line)
+ (if fns
+ (set-buffer (find-file-noselect (car fns)))
+ (error "%s: Can't find verilog-getopt-file -f file: %s"
+ (verilog-point-text) filename))
+ (goto-char (point-min))
+ (while (not (eobp))
+ (setq line (buffer-substring (point) (point-at-eol)))
+ (forward-line 1)
+ (when (string-match "//" line)
+ (setq line (substring line 0 (match-beginning 0))))
+ (with-current-buffer orig-buffer ; Variables are buffer-local, so need right context.
+ (verilog-getopt line))))))
+
+(defun verilog-getopt-flags ()
+ "Convert `verilog-library-flags' into standard library variables."
+ ;; If the flags are local, then all the outputs should be local also
+ (when (local-variable-p `verilog-library-flags (current-buffer))
+ (mapc 'make-local-variable '(verilog-library-extensions
+ verilog-library-directories
+ verilog-library-files
+ verilog-library-flags)))
+ ;; Allow user to customize
+ (verilog-run-hooks 'verilog-before-getopt-flags-hook)
+ ;; Process arguments
+ (verilog-getopt verilog-library-flags)
+ ;; Allow user to customize
+ (verilog-run-hooks 'verilog-getopt-flags-hook))
+
+(defun verilog-add-list-unique (varref object)
+ "Append to VARREF list the given OBJECT,
+unless it is already a member of the variable's list."
+ (unless (member object (symbol-value varref))
+ (set varref (append (symbol-value varref) (list object))))
+ varref)
+;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
+
+(defun verilog-current-flags ()
+ "Convert `verilog-library-flags' and similar variables to command line.
+Used for __FLAGS__ in `verilog-expand-command'."
+ (let ((cmd (mapconcat `concat verilog-library-flags " ")))
+ (when (equal cmd "")
+ (setq cmd (concat
+ "+libext+" (mapconcat `concat verilog-library-extensions "+")
+ (mapconcat (lambda (i) (concat " -y " i " +incdir+" i))
+ verilog-library-directories "")
+ (mapconcat (lambda (i) (concat " -v " i))
+ verilog-library-files ""))))
+ cmd))
+;;(verilog-current-flags)
+
+
+;;; Cached directory support:
+;;
+
+(defvar verilog-dir-cache-preserving nil
+ "If true, the directory cache is enabled, and file system changes are ignored.
+See `verilog-dir-exists-p' and `verilog-dir-files'.")
+
+;; If adding new cached variable, add also to verilog-preserve-dir-cache
+(defvar verilog-dir-cache-list nil
+ "Alist of (((Cwd Dirname) Results)...) for caching `verilog-dir-files'.")
+(defvar verilog-dir-cache-lib-filenames nil
+ "Cached data for `verilog-library-filenames'.")
+
+(defmacro verilog-preserve-dir-cache (&rest body)
+ "Execute the BODY forms, allowing directory cache preservation within BODY.
+This means that changes inside BODY made to the file system will not be
+seen by the `verilog-dir-files' and related functions."
+ `(let ((verilog-dir-cache-preserving (current-buffer))
+ verilog-dir-cache-list
+ verilog-dir-cache-lib-filenames)
+ (progn ,@body)))
+
+(defun verilog-dir-files (dirname)
+ "Return all filenames in the DIRNAME directory.
+Relative paths depend on the `default-directory'.
+Results are cached if inside `verilog-preserve-dir-cache'."
+ (unless verilog-dir-cache-preserving
+ (setq verilog-dir-cache-list nil)) ; Cache disabled
+ ;; We don't use expand-file-name on the dirname to make key, as it's slow
+ (let* ((cache-key (list dirname default-directory))
+ (fass (assoc cache-key verilog-dir-cache-list))
+ exp-dirname data)
+ (cond (fass ; Return data from cache hit
+ (nth 1 fass))
+ (t
+ (setq exp-dirname (expand-file-name dirname)
+ data (and (file-directory-p exp-dirname)
+ (directory-files exp-dirname nil nil nil)))
+ ;; Note we also encache nil for non-existing dirs.
+ (setq verilog-dir-cache-list (cons (list cache-key data)
+ verilog-dir-cache-list))
+ data))))
+;; Miss-and-hit test:
+;;(verilog-preserve-dir-cache (prin1 (verilog-dir-files "."))
+;; (prin1 (verilog-dir-files ".")) nil)
+
+(defun verilog-dir-file-exists-p (filename)
+ "Return true if FILENAME exists.
+Like `file-exists-p' but results are cached if inside
+`verilog-preserve-dir-cache'."
+ (let* ((dirname (file-name-directory filename))
+ ;; Correct for file-name-nondirectory returning same if no slash.
+ (dirnamed (if (or (not dirname) (equal dirname filename))
+ default-directory dirname))
+ (flist (verilog-dir-files dirnamed)))
+ (and flist
+ (member (file-name-nondirectory filename) flist)
+ t)))
+;;(verilog-dir-file-exists-p "verilog-mode.el")
+;;(verilog-dir-file-exists-p "../verilog-mode/verilog-mode.el")
+
+
+;;; Module name lookup:
+;;
+
+(defun verilog-module-inside-filename-p (module filename)
+ "Return modi if MODULE is specified inside FILENAME, else nil.
+Allows version control to check out the file if need be."
+ (and (or (file-exists-p filename)
+ (and (fboundp 'vc-backend)
+ (vc-backend filename)))
+ (let (modi type)
+ (with-current-buffer (find-file-noselect filename)
+ (save-excursion
+ (goto-char (point-min))
+ (while (and
+ ;; It may be tempting to look for verilog-defun-re,
+ ;; don't, it slows things down a lot!
+ (verilog-re-search-forward-quick "\\<\\(module\\|interface\\|program\\)\\>" nil t)
+ (setq type (match-string-no-properties 0))
+ (verilog-re-search-forward-quick "[(;]" nil t))
+ (if (equal module (verilog-read-module-name))
+ (setq modi (verilog-modi-new module filename (point) type))))
+ modi)))))
+
+(defun verilog-is-number (symbol)
+ "Return true if SYMBOL is number-like."
+ (or (string-match "^[0-9 \t:]+$" symbol)
+ (string-match "^[---]*[0-9]+$" symbol)
+ (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)))
+
+(defun verilog-symbol-detick (symbol wing-it)
+ "Return an expanded SYMBOL name without any defines.
+If the variable vh-{symbol} is defined, return that value.
+If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
+ (while (and symbol (string-match "^`" symbol))
+ (setq symbol (substring symbol 1))
+ (setq symbol
+ ;; Namespace intentionally short for AUTOs and compatibility
+ (if (boundp (intern (concat "vh-" symbol)))
+ ;; Emacs has a bug where boundp on a buffer-local
+ ;; variable in only one buffer returns t in another.
+ ;; This can confuse, so check for nil.
+ ;; Namespace intentionally short for AUTOs and compatibility
+ (let ((val (eval (intern (concat "vh-" symbol)))))
+ (if (eq val nil)
+ (if wing-it symbol nil)
+ val))
+ (if wing-it symbol nil))))
+ symbol)
+;;(verilog-symbol-detick "`mod" nil)
+
+(defun verilog-symbol-detick-denumber (symbol)
+ "Return SYMBOL with defines converted and any numbers dropped to nil."
+ (when (string-match "^`" symbol)
+ ;; This only will work if the define is a simple signal, not
+ ;; something like a[b]. Sorry, it should be substituted into the parser
+ (setq symbol
+ (verilog-string-replace-matches
+ "\\[[^0-9: \t]+\\]" "" nil nil
+ (or (verilog-symbol-detick symbol nil)
+ (if verilog-auto-sense-defines-constant
+ "0"
+ symbol)))))
+ (if (verilog-is-number symbol)
+ nil
+ symbol))
+
+(defun verilog-symbol-detick-text (text)
+ "Return TEXT without any known defines.
+If the variable vh-{symbol} is defined, substitute that value."
+ (let ((ok t) symbol val)
+ (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
+ (setq symbol (match-string 1 text))
+ ;;(message symbol)
+ (cond ((and
+ ;; Namespace intentionally short for AUTOs and compatibility
+ (boundp (intern (concat "vh-" symbol)))
+ ;; Emacs has a bug where boundp on a buffer-local
+ ;; variable in only one buffer returns t in another.
+ ;; This can confuse, so check for nil.
+ ;; Namespace intentionally short for AUTOs and compatibility
+ (setq val (eval (intern (concat "vh-" symbol)))))
+ (setq text (replace-match val nil nil text)))
+ (t (setq ok nil)))))
+ text)
+;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
+
+(defun verilog-expand-dirnames (&optional dirnames)
+ "Return a list of existing directories given a list of wildcarded DIRNAMES.
+Or, just the existing dirnames themselves if there are no wildcards."
+ ;; Note this function is performance critical.
+ ;; Do not call anything that requires disk access that cannot be cached.
+ (interactive)
+ (unless dirnames
+ (error "`verilog-library-directories' should include at least `.'"))
+ (setq dirnames (reverse dirnames)) ; not nreverse
+ (let ((dirlist nil)
+ pattern dirfile dirfiles dirname root filename rest basefile)
+ (while dirnames
+ (setq dirname (substitute-in-file-name (car dirnames))
+ dirnames (cdr dirnames))
+ (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ; root
+ "\\([^/\\]*[*?][^/\\]*\\)" ; filename with *?
+ "\\(.*\\)") ; rest
+ dirname)
+ (setq root (match-string 1 dirname)
+ filename (match-string 2 dirname)
+ rest (match-string 3 dirname)
+ pattern filename)
+ ;; now replace those * and ? with .+ and .
+ ;; use ^ and /> to get only whole file names
+ (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
+ pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
+ pattern (concat "^" pattern "$")
+ dirfiles (verilog-dir-files root))
+ (while dirfiles
+ (setq basefile (car dirfiles)
+ dirfile (expand-file-name (concat root basefile rest))
+ dirfiles (cdr dirfiles))
+ (if (and (string-match pattern basefile)
+ ;; Don't allow abc/*/rtl to match abc/rtl via ..
+ (not (equal basefile "."))
+ (not (equal basefile ".."))
+ (file-directory-p dirfile))
+ (setq dirlist (cons dirfile dirlist)))))
+ ;; Defaults
+ (t
+ (if (file-directory-p dirname)
+ (setq dirlist (cons dirname dirlist))))))
+ dirlist))
+;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
+
+(defun verilog-library-filenames (filename &optional current check-ext)
+ "Return a search path to find the given FILENAME or module name.
+Uses the optional CURRENT filename or variable `buffer-file-name', plus
+`verilog-library-directories' and `verilog-library-extensions'
+variables to build the path. With optional CHECK-EXT also check
+`verilog-library-extensions'."
+ (unless current (setq current (buffer-file-name)))
+ (unless verilog-dir-cache-preserving
+ (setq verilog-dir-cache-lib-filenames nil))
+ (let* ((cache-key (list filename current check-ext))
+ (fass (assoc cache-key verilog-dir-cache-lib-filenames))
+ chkdirs chkdir chkexts fn outlist)
+ (cond (fass ; Return data from cache hit
+ (nth 1 fass))
+ (t
+ ;; Note this expand can't be easily cached, as we need to
+ ;; pick up buffer-local variables for newly read sub-module files
+ (setq chkdirs (verilog-expand-dirnames verilog-library-directories))
+ (while chkdirs
+ (setq chkdir (expand-file-name (car chkdirs)
+ (file-name-directory current))
+ chkexts (if check-ext verilog-library-extensions `("")))
+ (while chkexts
+ (setq fn (expand-file-name (concat filename (car chkexts))
+ chkdir))
+ ;;(message "Check for %s" fn)
+ (if (verilog-dir-file-exists-p fn)
+ (setq outlist (cons (expand-file-name
+ fn (file-name-directory current))
+ outlist)))
+ (setq chkexts (cdr chkexts)))
+ (setq chkdirs (cdr chkdirs)))
+ (setq outlist (nreverse outlist))
+ (setq verilog-dir-cache-lib-filenames
+ (cons (list cache-key outlist)
+ verilog-dir-cache-lib-filenames))
+ outlist))))
+
+(defun verilog-module-filenames (module current)
+ "Return a search path to find the given MODULE name.
+Uses the CURRENT filename, `verilog-library-extensions',
+`verilog-library-directories' and `verilog-library-files'
+variables to build the path."
+ ;; Return search locations for it
+ (append (list current) ; first, current buffer
+ (verilog-library-filenames module current t)
+ ;; Finally any libraries; fixed up if using e.g. tramp
+ (mapcar (lambda (fname)
+ (if (file-name-absolute-p fname)
+ (concat (file-remote-p current) fname)
+ fname))
+ verilog-library-files)))
+
+;;
+;; Module Information
+;;
+;; Many of these functions work on "modi" a module information structure
+;; A modi is: [module-name-string file-name begin-point]
+
+(defvar verilog-cache-enabled t
+ "Non-nil enables caching of signals, etc. Set to nil for debugging to make things SLOW!")
+
+(defvar verilog-modi-cache-list nil
+ "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
+For speeding up verilog-modi-get-* commands.
+Buffer-local.")
+(make-variable-buffer-local 'verilog-modi-cache-list)
+
+(defvar verilog-modi-cache-preserve-tick nil
+ "Modification tick after which the cache is still considered valid.
+Use `verilog-preserve-modi-cache' to set it.")
+(defvar verilog-modi-cache-preserve-buffer nil
+ "Modification tick after which the cache is still considered valid.
+Use `verilog-preserve-modi-cache' to set it.")
+(defvar verilog-modi-cache-current-enable nil
+ "Non-nil means allow caching `verilog-modi-current', set by let().")
+(defvar verilog-modi-cache-current nil
+ "Currently active `verilog-modi-current', if any, set by let().")
+(defvar verilog-modi-cache-current-max nil
+ "Current endmodule point for `verilog-modi-cache-current', if any.")
+
+(defun verilog-modi-current ()
+ "Return the modi structure for the module currently at point, possibly cached."
+ (cond ((and verilog-modi-cache-current
+ (>= (point) (verilog-modi-get-point verilog-modi-cache-current))
+ (<= (point) verilog-modi-cache-current-max))
+ ;; Slow assertion, for debugging the cache:
+ ;;(or (equal verilog-modi-cache-current (verilog-modi-current-get)) (debug))
+ verilog-modi-cache-current)
+ (verilog-modi-cache-current-enable
+ (setq verilog-modi-cache-current (verilog-modi-current-get)
+ verilog-modi-cache-current-max
+ ;; The cache expires when we pass "endmodule" as then the
+ ;; current modi may change to the next module
+ ;; This relies on the AUTOs generally inserting, not deleting text
+ (save-excursion
+ (verilog-re-search-forward-quick verilog-end-defun-re nil nil)))
+ verilog-modi-cache-current)
+ (t
+ (verilog-modi-current-get))))
+
+(defun verilog-modi-current-get ()
+ "Return the modi structure for the module currently at point."
+ (let* (name type pt)
+ ;; read current module's name
+ (save-excursion
+ (verilog-re-search-backward-quick verilog-defun-re nil nil)
+ (setq type (match-string-no-properties 0))
+ (verilog-re-search-forward-quick "(" nil nil)
+ (setq name (verilog-read-module-name))
+ (setq pt (point)))
+ ;; return modi - note this vector built two places
+ (verilog-modi-new name (or (buffer-file-name) (current-buffer)) pt type)))
+
+(defvar verilog-modi-lookup-cache nil "Hash of (modulename modi).")
+(make-variable-buffer-local 'verilog-modi-lookup-cache)
+(defvar verilog-modi-lookup-last-current nil "Cache of `current-buffer' at last lookup.")
+(defvar verilog-modi-lookup-last-tick nil "Cache of `buffer-chars-modified-tick' at last lookup.")
+
+(defun verilog-modi-lookup (module allow-cache &optional ignore-error)
+ "Find the file and point at which MODULE is defined.
+If ALLOW-CACHE is set, check and remember cache of previous lookups.
+Return modi if successful, else print message unless IGNORE-ERROR is true."
+ (let* ((current (or (buffer-file-name) (current-buffer)))
+ modi)
+ ;; Check cache
+ ;;(message "verilog-modi-lookup: %s" module)
+ (cond ((and verilog-modi-lookup-cache
+ verilog-cache-enabled
+ allow-cache
+ (setq modi (gethash module verilog-modi-lookup-cache))
+ (equal verilog-modi-lookup-last-current current)
+ ;; If hit is in current buffer, then tick must match
+ (or (equal verilog-modi-lookup-last-tick (buffer-chars-modified-tick))
+ (not (equal current (verilog-modi-file-or-buffer modi)))))
+ ;;(message "verilog-modi-lookup: HIT %S" modi)
+ modi)
+ ;; Miss
+ (t (let* ((realname (verilog-symbol-detick module t))
+ (orig-filenames (verilog-module-filenames realname current))
+ (filenames orig-filenames)
+ mif)
+ (while (and filenames (not mif))
+ (if (not (setq mif (verilog-module-inside-filename-p realname (car filenames))))
+ (setq filenames (cdr filenames))))
+ ;; mif has correct form to become later elements of modi
+ (setq modi mif)
+ (or mif ignore-error
+ (error
+ (concat
+ "%s: Can't locate `%s' module definition%s"
+ "\n Check the verilog-library-directories variable."
+ "\n I looked in (if not listed, doesn't exist):\n\t%s")
+ (verilog-point-text) module
+ (if (not (equal module realname))
+ (concat " (Expanded macro to " realname ")")
+ "")
+ (mapconcat 'concat orig-filenames "\n\t")))
+ (when (eval-when-compile (fboundp 'make-hash-table))
+ (unless verilog-modi-lookup-cache
+ (setq verilog-modi-lookup-cache
+ (make-hash-table :test 'equal :rehash-size 4.0)))
+ (puthash module modi verilog-modi-lookup-cache))
+ (setq verilog-modi-lookup-last-current current
+ verilog-modi-lookup-last-tick (buffer-chars-modified-tick)))))
+ modi))
+
+(defun verilog-modi-filename (modi)
+ "Filename of MODI, or name of buffer if it's never been saved."
+ (if (bufferp (verilog-modi-file-or-buffer modi))
+ (or (buffer-file-name (verilog-modi-file-or-buffer modi))
+ (buffer-name (verilog-modi-file-or-buffer modi)))
+ (verilog-modi-file-or-buffer modi)))
+
+(defun verilog-modi-goto (modi)
+ "Move point/buffer to specified MODI."
+ (or modi (error "Passed unfound modi to goto, check earlier"))
+ (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
+ (verilog-modi-file-or-buffer modi)
+ (find-file-noselect (verilog-modi-file-or-buffer modi))))
+ (or (equal major-mode `verilog-mode) ; Put into Verilog mode to get syntax
+ (verilog-mode))
+ (goto-char (verilog-modi-get-point modi)))
+
+(defun verilog-goto-defun-file (module)
+ "Move point to the file at which a given MODULE is defined."
+ (interactive "sGoto File for Module: ")
+ (let* ((modi (verilog-modi-lookup module nil)))
+ (when modi
+ (verilog-modi-goto modi)
+ (switch-to-buffer (current-buffer)))))
+
+(defun verilog-modi-cache-results (modi function)
+ "Run on MODI the given FUNCTION. Locate the module in a file.
+Cache the output of function so next call may have faster access."
+ (let (fass)
+ (save-excursion ; Cache is buffer-local so can't avoid this.
+ (verilog-modi-goto modi)
+ (if (and (setq fass (assoc (list modi function)
+ verilog-modi-cache-list))
+ ;; Destroy caching when incorrect; Modified or file changed
+ (not (and verilog-cache-enabled
+ (or (equal (buffer-chars-modified-tick) (nth 1 fass))
+ (and verilog-modi-cache-preserve-tick
+ (<= verilog-modi-cache-preserve-tick (nth 1 fass))
+ (equal verilog-modi-cache-preserve-buffer (current-buffer))))
+ (equal (visited-file-modtime) (nth 2 fass)))))
+ (setq verilog-modi-cache-list nil
+ fass nil))
+ (cond (fass
+ ;; Return data from cache hit
+ (nth 3 fass))
+ (t
+ ;; Read from file
+ ;; Clear then restore any highlighting to make emacs19 happy
+ (let ((func-returns
+ (verilog-save-font-no-change-functions
+ (funcall function))))
+ ;; Cache for next time
+ (setq verilog-modi-cache-list
+ (cons (list (list modi function)
+ (buffer-chars-modified-tick)
+ (visited-file-modtime)
+ func-returns)
+ verilog-modi-cache-list))
+ func-returns))))))
+
+(defun verilog-modi-cache-add (modi function element sig-list)
+ "Add function return results to the module cache.
+Update MODI's cache for given FUNCTION so that the return ELEMENT of that
+function now contains the additional SIG-LIST parameters."
+ (let (fass)
+ (save-excursion
+ (verilog-modi-goto modi)
+ (if (setq fass (assoc (list modi function)
+ verilog-modi-cache-list))
+ (let ((func-returns (nth 3 fass)))
+ (aset func-returns element
+ (append sig-list (aref func-returns element))))))))
+
+(defmacro verilog-preserve-modi-cache (&rest body)
+ "Execute the BODY forms, allowing cache preservation within BODY.
+This means that changes to the buffer will not result in the cache being
+flushed. If the changes affect the modsig state, they must call the
+modsig-cache-add-* function, else the results of later calls may be
+incorrect. Without this, changes are assumed to be adding/removing signals
+and invalidating the cache."
+ `(let ((verilog-modi-cache-preserve-tick (buffer-chars-modified-tick))
+ (verilog-modi-cache-preserve-buffer (current-buffer)))
+ (progn ,@body)))
+
+
+(defun verilog-modi-modport-lookup-one (modi name &optional ignore-error)
+ "Given a MODI, return the declarations related to the given modport NAME.
+Report errors unless optional IGNORE-ERROR."
+ ;; Recursive routine - see below
+ (let* ((realname (verilog-symbol-detick name t))
+ (modport (assoc name (verilog-decls-get-modports (verilog-modi-get-decls modi)))))
+ (or modport ignore-error
+ (error "%s: Can't locate `%s' modport definition%s"
+ (verilog-point-text) name
+ (if (not (equal name realname))
+ (concat " (Expanded macro to " realname ")")
+ "")))
+ (let* ((decls (verilog-modport-decls modport))
+ (clks (verilog-modport-clockings modport)))
+ ;; Now expand any clocking's
+ (while clks
+ (setq decls (verilog-decls-append
+ decls
+ (verilog-modi-modport-lookup-one modi (car clks) ignore-error)))
+ (setq clks (cdr clks)))
+ decls)))
+
+(defun verilog-modi-modport-lookup (modi name-re &optional ignore-error)
+ "Given a MODI, return the declarations related to the given modport NAME-RE.
+If the modport points to any clocking blocks, expand the signals to include
+those clocking block's signals."
+ ;; Recursive routine - see below
+ (let* ((mod-decls (verilog-modi-get-decls modi))
+ (clks (verilog-decls-get-modports mod-decls))
+ (name-re (concat "^" name-re "$"))
+ (decls (verilog-decls-new nil nil nil nil nil nil nil nil nil)))
+ ;; Pull in all modports
+ (while clks
+ (when (string-match name-re (verilog-modport-name (car clks)))
+ (setq decls (verilog-decls-append
+ decls
+ (verilog-modi-modport-lookup-one modi (verilog-modport-name (car clks)) ignore-error))))
+ (setq clks (cdr clks)))
+ decls))
+
+(defun verilog-signals-matching-enum (in-list enum)
+ "Return all signals in IN-LIST matching the given ENUM."
+ (let (out-list)
+ (while in-list
+ (if (equal (verilog-sig-enum (car in-list)) enum)
+ (setq out-list (cons (car in-list) out-list)))
+ (setq in-list (cdr in-list)))
+ ;; New scheme
+ ;; Namespace intentionally short for AUTOs and compatibility
+ (let* ((enumvar (intern (concat "venum-" enum)))
+ (enumlist (and (boundp enumvar) (eval enumvar))))
+ (while enumlist
+ (add-to-list 'out-list (list (car enumlist)))
+ (setq enumlist (cdr enumlist))))
+ (nreverse out-list)))
+
+(defun verilog-signals-matching-regexp (in-list regexp)
+ "Return all signals in IN-LIST matching the given REGEXP, if non-nil."
+ (if (or (not regexp) (equal regexp ""))
+ in-list
+ (let ((case-fold-search verilog-case-fold)
+ out-list)
+ (while in-list
+ (if (string-match regexp (verilog-sig-name (car in-list)))
+ (setq out-list (cons (car in-list) out-list)))
+ (setq in-list (cdr in-list)))
+ (nreverse out-list))))
+
+(defun verilog-signals-not-matching-regexp (in-list regexp)
+ "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
+ (if (or (not regexp) (equal regexp ""))
+ in-list
+ (let ((case-fold-search verilog-case-fold)
+ out-list)
+ (while in-list
+ (if (not (string-match regexp (verilog-sig-name (car in-list))))
+ (setq out-list (cons (car in-list) out-list)))
+ (setq in-list (cdr in-list)))
+ (nreverse out-list))))
+
+(defun verilog-signals-matching-dir-re (in-list decl-type regexp)
+ "Return all signals in IN-LIST matching the given DECL-TYPE and REGEXP,
+if non-nil."
+ (if (or (not regexp) (equal regexp ""))
+ in-list
+ (let (out-list to-match)
+ (while in-list
+ ;; Note verilog-insert-one-definition matches on this order
+ (setq to-match (concat
+ decl-type
+ " " (verilog-sig-signed (car in-list))
+ " " (verilog-sig-multidim (car in-list))
+ (verilog-sig-bits (car in-list))))
+ (if (string-match regexp to-match)
+ (setq out-list (cons (car in-list) out-list)))
+ (setq in-list (cdr in-list)))
+ (nreverse out-list))))
+
+(defun verilog-signals-edit-wire-reg (in-list)
+ "Return all signals in IN-LIST with wire/reg data types made blank."
+ (mapcar (lambda (sig)
+ (when (member (verilog-sig-type sig) '("wire" "reg"))
+ (verilog-sig-type-set sig nil))
+ sig) in-list))
+
+;; Combined
+(defun verilog-decls-get-signals (decls)
+ "Return all declared signals in DECLS, excluding `assign' statements."
+ (append
+ (verilog-decls-get-outputs decls)
+ (verilog-decls-get-inouts decls)
+ (verilog-decls-get-inputs decls)
+ (verilog-decls-get-vars decls)
+ (verilog-decls-get-consts decls)
+ (verilog-decls-get-gparams decls)))
+
+(defun verilog-decls-get-ports (decls)
+ (append
+ (verilog-decls-get-outputs decls)
+ (verilog-decls-get-inouts decls)
+ (verilog-decls-get-inputs decls)))
+
+(defun verilog-decls-get-iovars (decls)
+ (append
+ (verilog-decls-get-vars decls)
+ (verilog-decls-get-outputs decls)
+ (verilog-decls-get-inouts decls)
+ (verilog-decls-get-inputs decls)))
+
+(defsubst verilog-modi-cache-add-outputs (modi sig-list)
+ (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
+(defsubst verilog-modi-cache-add-inouts (modi sig-list)
+ (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
+(defsubst verilog-modi-cache-add-inputs (modi sig-list)
+ (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
+(defsubst verilog-modi-cache-add-vars (modi sig-list)
+ (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
+(defsubst verilog-modi-cache-add-gparams (modi sig-list)
+ (verilog-modi-cache-add modi 'verilog-read-decls 7 sig-list))
+
+
+;;; Auto creation utilities:
+;;
+
+(defun verilog-auto-re-search-do (search-for func)
+ "Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs."
+ (goto-char (point-min))
+ (while (verilog-re-search-forward-quick search-for nil t)
+ (funcall func)))
+
+(defun verilog-insert-one-definition (sig type indent-pt)
+ "Print out a definition for SIG of the given TYPE,
+with appropriate INDENT-PT indentation."
+ (indent-to indent-pt)
+ ;; Note verilog-signals-matching-dir-re matches on this order
+ (insert type)
+ (when (verilog-sig-modport sig)
+ (insert "." (verilog-sig-modport sig)))
+ (when (verilog-sig-signed sig)
+ (insert " " (verilog-sig-signed sig)))
+ (when (verilog-sig-multidim sig)
+ (insert " " (verilog-sig-multidim-string sig)))
+ (when (verilog-sig-bits sig)
+ (insert " " (verilog-sig-bits sig)))
+ (indent-to (max 24 (+ indent-pt 16)))
+ (unless (= (char-syntax (preceding-char)) ?\ )
+ (insert " ")) ; Need space between "]name" if indent-to did nothing
+ (insert (verilog-sig-name sig))
+ (when (verilog-sig-memory sig)
+ (insert " " (verilog-sig-memory sig))))
+
+(defun verilog-insert-definition (modi sigs direction indent-pt v2k &optional dont-sort)
+ "Print out a definition for MODI's list of SIGS of the given DIRECTION,
+with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
+format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output.
+When MODI is non-null, also add to modi-cache, for tracking."
+ (when modi
+ (cond ((equal direction "wire")
+ (verilog-modi-cache-add-vars modi sigs))
+ ((equal direction "reg")
+ (verilog-modi-cache-add-vars modi sigs))
+ ((equal direction "output")
+ (verilog-modi-cache-add-outputs modi sigs)
+ (when verilog-auto-declare-nettype
+ (verilog-modi-cache-add-vars modi sigs)))
+ ((equal direction "input")
+ (verilog-modi-cache-add-inputs modi sigs)
+ (when verilog-auto-declare-nettype
+ (verilog-modi-cache-add-vars modi sigs)))
+ ((equal direction "inout")
+ (verilog-modi-cache-add-inouts modi sigs)
+ (when verilog-auto-declare-nettype
+ (verilog-modi-cache-add-vars modi sigs)))
+ ((equal direction "interface"))
+ ((equal direction "parameter")
+ (verilog-modi-cache-add-gparams modi sigs))
+ (t
+ (error "Unsupported verilog-insert-definition direction: `%s'" direction))))
+ (or dont-sort
+ (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
+ (while sigs
+ (let ((sig (car sigs)))
+ (verilog-insert-one-definition
+ sig
+ ;; Want "type x" or "output type x", not "wire type x"
+ (cond ((or (verilog-sig-type sig)
+ verilog-auto-wire-type)
+ (concat
+ (when (member direction '("input" "output" "inout"))
+ (concat direction " "))
+ (or (verilog-sig-type sig)
+ verilog-auto-wire-type)))
+ ((and verilog-auto-declare-nettype
+ (member direction '("input" "output" "inout")))
+ (concat direction " " verilog-auto-declare-nettype))
+ (t
+ direction))
+ indent-pt)
+ (insert (if v2k "," ";"))
+ (if (or (not verilog-auto-wire-comment)
+ (not (verilog-sig-comment sig))
+ (equal "" (verilog-sig-comment sig)))
+ (insert "\n")
+ (indent-to (max 48 (+ indent-pt 40)))
+ (verilog-insert "// " (verilog-sig-comment sig) "\n"))
+ (setq sigs (cdr sigs)))))
+
+(eval-when-compile
+ (if (not (boundp 'indent-pt))
+ (defvar indent-pt nil "Local used by `verilog-insert-indent'.")))
+
+(defun verilog-insert-indent (&rest stuff)
+ "Indent to position stored in local `indent-pt' variable, then insert STUFF.
+Presumes that any newlines end a list element."
+ (let ((need-indent t))
+ (while stuff
+ (if need-indent (indent-to indent-pt))
+ (setq need-indent nil)
+ (verilog-insert (car stuff))
+ (setq need-indent (string-match "\n$" (car stuff))
+ stuff (cdr stuff)))))
+;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
+
+(defun verilog-forward-or-insert-line ()
+ "Move forward a line, unless at EOB, then insert a newline."
+ (if (eobp) (insert "\n")
+ (forward-line)))
+
+(defun verilog-repair-open-comma ()
+ "Insert comma if previous argument is other than an open parenthesis or endif."
+ ;; We can't just search backward for ) as it might be inside another expression.
+ ;; Also want "`ifdef X input foo `endif" to just leave things to the human to deal with
+ (save-excursion
+ (verilog-backward-syntactic-ws-quick)
+ (when (and (not (save-excursion ; Not beginning (, or existing ,
+ (backward-char 1)
+ (looking-at "[(,]")))
+ (not (save-excursion ; Not `endif, or user define
+ (backward-char 1)
+ (skip-chars-backward "[a-zA-Z0-9_`]")
+ (looking-at "`"))))
+ (insert ","))))
+
+(defun verilog-repair-close-comma ()
+ "If point is at a comma followed by a close parenthesis, fix it.
+This repairs those mis-inserted by an AUTOARG."
+ ;; It would be much nicer if Verilog allowed extra commas like Perl does!
+ (save-excursion
+ (verilog-forward-close-paren)
+ (backward-char 1)
+ (verilog-backward-syntactic-ws-quick)
+ (backward-char 1)
+ (when (looking-at ",")
+ (delete-char 1))))
+
+(defun verilog-make-width-expression (range-exp)
+ "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
+ ;; strip off the []
+ (cond ((not range-exp)
+ "1")
+ (t
+ (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
+ (setq range-exp (match-string 1 range-exp)))
+ (cond ((not range-exp)
+ "1")
+ ;; [#:#] We can compute a numeric result
+ ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$"
+ range-exp)
+ (int-to-string
+ (1+ (abs (- (string-to-number (match-string 1 range-exp))
+ (string-to-number (match-string 2 range-exp)))))))
+ ;; [PARAM-1:0] can just return PARAM
+ ((string-match "^\\s *\\([a-zA-Z_][a-zA-Z0-9_]*\\)\\s *-\\s *1\\s *:\\s *0\\s *$" range-exp)
+ (match-string 1 range-exp))
+ ;; [arbitrary] need math
+ ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
+ (concat "(1+(" (match-string 1 range-exp) ")"
+ (if (equal "0" (match-string 2 range-exp))
+ "" ; Don't bother with -(0)
+ (concat "-(" (match-string 2 range-exp) ")"))
+ ")"))
+ (t nil)))))
+;;(verilog-make-width-expression "`A:`B")
+
+(defun verilog-simplify-range-expression (expr)
+ "Return a simplified range expression with constants eliminated from EXPR."
+ ;; Note this is always called with brackets; ie [z] or [z:z]
+ (if (not (string-match "[---+*()]" expr))
+ expr ; short-circuit
+ (let ((out expr)
+ (last-pass ""))
+ (while (not (equal last-pass out))
+ (setq last-pass out)
+ ;; Prefix regexp needs beginning of match, or some symbol of
+ ;; lesser or equal precedence. We assume the [:]'s exist in expr.
+ ;; Ditto the end.
+ (while (string-match
+ (concat "\\([[({:*+-]\\)" ; - must be last
+ "(\\<\\([0-9A-Za-z_]+\\))"
+ "\\([])}:*+-]\\)")
+ out)
+ (setq out (replace-match "\\1\\2\\3" nil nil out)))
+ (while (string-match
+ (concat "\\([[({:*+-]\\)" ; - must be last
+ "\\$clog2\\s *(\\<\\([0-9]+\\))"
+ "\\([])}:*+-]\\)")
+ out)
+ (setq out (replace-match
+ (concat
+ (match-string 1 out)
+ (int-to-string (verilog-clog2 (string-to-number (match-string 2 out))))
+ (match-string 3 out))
+ nil nil out)))
+ ;; For precedence do * before +/-
+ (while (string-match
+ (concat "\\([[({:*+-]\\)"
+ "\\([0-9]+\\)\\s *\\([*]\\)\\s *\\([0-9]+\\)"
+ "\\([])}:*+-]\\)")
+ out)
+ (setq out (replace-match
+ (concat (match-string 1 out)
+ (int-to-string (* (string-to-number (match-string 2 out))
+ (string-to-number (match-string 4 out))))
+ (match-string 5 out))
+ nil nil out)))
+ (while (string-match
+ (concat "\\([[({:+-]\\)" ; No * here as higher prec
+ "\\([0-9]+\\)\\s *\\([---+]\\)\\s *\\([0-9]+\\)"
+ "\\([])}:+-]\\)")
+ out)
+ (let ((pre (match-string 1 out))
+ (lhs (string-to-number (match-string 2 out)))
+ (rhs (string-to-number (match-string 4 out)))
+ (post (match-string 5 out))
+ val)
+ (when (equal pre "-")
+ (setq lhs (- lhs)))
+ (setq val (if (equal (match-string 3 out) "-")
+ (- lhs rhs)
+ (+ lhs rhs))
+ out (replace-match
+ (concat (if (and (equal pre "-")
+ (< val 0))
+ "" ; Not "--20" but just "-20"
+ pre)
+ (int-to-string val)
+ post)
+ nil nil out)) )))
+ out)))
+
+;;(verilog-simplify-range-expression "[1:3]") ; 1
+;;(verilog-simplify-range-expression "[(1):3]") ; 1
+;;(verilog-simplify-range-expression "[(((16)+1)+1+(1+1))]") ; 20
+;;(verilog-simplify-range-expression "[(2*3+6*7)]") ; 48
+;;(verilog-simplify-range-expression "[(FOO*4-1*2)]") ; FOO*4-2
+;;(verilog-simplify-range-expression "[(FOO*4+1-1)]") ; FOO*4+0
+;;(verilog-simplify-range-expression "[(func(BAR))]") ; func(BAR)
+;;(verilog-simplify-range-expression "[FOO-1+1-1+1]") ; FOO-0
+;;(verilog-simplify-range-expression "[$clog2(2)]") ; 1
+;;(verilog-simplify-range-expression "[$clog2(7)]") ; 3
+
+(defun verilog-clog2 (value)
+ "Compute $clog2 - ceiling log2 of VALUE."
+ (if (< value 1)
+ 0
+ (ceiling (/ (log value) (log 2)))))
+
+(defun verilog-typedef-name-p (variable-name)
+ "Return true if the VARIABLE-NAME is a type definition."
+ (when verilog-typedef-regexp
+ (verilog-string-match-fold verilog-typedef-regexp variable-name)))
+
+;;; Auto deletion:
+;;
+
+(defun verilog-delete-autos-lined ()
+ "Delete autos that occupy multiple lines, between begin and end comments."
+ ;; The newline must not have a comment property, so we must
+ ;; delete the end auto's newline, not the first newline
+ (forward-line 1)
+ (let ((pt (point)))
+ (when (and
+ (looking-at "\\s-*// Beginning")
+ (search-forward "// End of automatic" nil t))
+ ;; End exists
+ (end-of-line)
+ (forward-line 1)
+ (delete-region pt (point)))))
+
+(defun verilog-delete-empty-auto-pair ()
+ "Delete begin/end auto pair at point, if empty."
+ (forward-line 0)
+ (when (looking-at (concat "\\s-*// Beginning of automatic.*\n"
+ "\\s-*// End of automatics\n"))
+ (delete-region (point) (save-excursion (forward-line 2) (point)))))
+
+(defun verilog-forward-close-paren ()
+ "Find the close parenthesis that match the current point.
+Ignore other close parenthesis with matching open parens."
+ (let ((parens 1))
+ (while (> parens 0)
+ (unless (verilog-re-search-forward-quick "[()]" nil t)
+ (error "%s: Mismatching ()" (verilog-point-text)))
+ (cond ((= (preceding-char) ?\( )
+ (setq parens (1+ parens)))
+ ((= (preceding-char) ?\) )
+ (setq parens (1- parens)))))))
+
+(defun verilog-backward-open-paren ()
+ "Find the open parenthesis that match the current point.
+Ignore other open parenthesis with matching close parens."
+ (let ((parens 1))
+ (while (> parens 0)
+ (unless (verilog-re-search-backward-quick "[()]" nil t)
+ (error "%s: Mismatching ()" (verilog-point-text)))
+ (cond ((= (following-char) ?\) )
+ (setq parens (1+ parens)))
+ ((= (following-char) ?\( )
+ (setq parens (1- parens)))))))
+
+(defun verilog-backward-open-bracket ()
+ "Find the open bracket that match the current point.
+Ignore other open bracket with matching close bracket."
+ (let ((parens 1))
+ (while (> parens 0)
+ (unless (verilog-re-search-backward-quick "[][]" nil t)
+ (error "%s: Mismatching []" (verilog-point-text)))
+ (cond ((= (following-char) ?\] )
+ (setq parens (1+ parens)))
+ ((= (following-char) ?\[ )
+ (setq parens (1- parens)))))))
+
+(defun verilog-delete-to-paren ()
+ "Delete the automatic inst/sense/arg created by autos.
+Deletion stops at the matching end parenthesis, outside comments."
+ (delete-region (point)
+ (save-excursion
+ (verilog-backward-open-paren)
+ (verilog-forward-sexp-ign-cmt 1) ; Moves to paren that closes argdecl's
+ (backward-char 1)
+ (point))))
+
+(defun verilog-auto-star-safe ()
+ "Return if a .* AUTOINST is safe to delete or expand.
+It was created by the AUTOS themselves, or by the user."
+ (and verilog-auto-star-expand
+ (looking-at
+ (concat "[ \t\n\f,]*\\([)]\\|// " verilog-inst-comment-re "\\)"))))
+
+(defun verilog-delete-auto-star-all ()
+ "Delete a .* AUTOINST, if it is safe."
+ (when (verilog-auto-star-safe)
+ (verilog-delete-to-paren)))
+
+(defun verilog-delete-auto-star-implicit ()
+ "Delete all .* implicit connections created by `verilog-auto-star'.
+This function will be called automatically at save unless
+`verilog-auto-star-save' is set, any non-templated expanded pins will be
+removed."
+ (interactive)
+ (let (paren-pt indent have-close-paren)
+ (save-excursion
+ (goto-char (point-min))
+ ;; We need to match these even outside of comments.
+ ;; For reasonable performance, we don't check if inside comments, sorry.
+ (while (re-search-forward "// Implicit \\.\\*" nil t)
+ (setq paren-pt (point))
+ (beginning-of-line)
+ (setq have-close-paren
+ (save-excursion
+ (when (search-forward ");" paren-pt t)
+ (setq indent (current-indentation))
+ t)))
+ (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
+ (when have-close-paren
+ ;; Delete extra commentary
+ (save-excursion
+ (while (progn
+ (forward-line -1)
+ (looking-at (concat "\\s *//\\s *" verilog-inst-comment-re "\n")))
+ (delete-region (match-beginning 0) (match-end 0))))
+ ;; If it is simple, we can put the ); on the same line as the last text
+ (let ((rtn-pt (point)))
+ (save-excursion
+ (while (progn (backward-char 1)
+ (looking-at "[ \t\n\f]")))
+ (when (looking-at ",")
+ (delete-region (+ 1 (point)) rtn-pt))))
+ (when (bolp)
+ (indent-to indent))
+ (insert ");\n")
+ ;; Still need to kill final comma - always is one as we put one after the .*
+ (re-search-backward ",")
+ (delete-char 1))))))
+
+(defun verilog-delete-auto-buffer ()
+ "Perform `verilog-delete-auto' on the current buffer.
+Intended for internal use inside a `verilog-save-font-no-change-functions' block."
+ ;; Allow user to customize
+ (verilog-run-hooks 'verilog-before-delete-auto-hook)
+
+ ;; Remove those that have multi-line insertions, possibly with parameters
+ ;; We allow anything beginning with AUTO, so that users can add their own
+ ;; patterns
+ (verilog-auto-re-search-do
+ (concat "/\\*AUTO[A-Za-z0-9_]+"
+ ;; Optional parens or quoted parameter or .* for (((...)))
+ "\\(\\|([^)]*)\\|(\"[^\"]*\")\\).*?"
+ "\\*/")
+ 'verilog-delete-autos-lined)
+ ;; Remove those that are in parenthesis
+ (verilog-auto-re-search-do
+ (concat "/\\*"
+ (eval-when-compile
+ (verilog-regexp-words
+ `("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
+ "AUTOSENSE")))
+ "\\*/")
+ 'verilog-delete-to-paren)
+ ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
+ (verilog-auto-re-search-do "\\.\\*"
+ 'verilog-delete-auto-star-all)
+ ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
+ (goto-char (point-min))
+ (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)\\([ \tLT0-9]*\\| LHS: .*\\)?$" nil t)
+ (replace-match ""))
+
+ ;; Final customize
+ (verilog-run-hooks 'verilog-delete-auto-hook))
+
+(defun verilog-delete-auto ()
+ "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
+Use \\[verilog-auto] to re-insert the updated AUTOs.
+
+The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
+called before and after this function, respectively."
+ (interactive)
+ (save-excursion
+ (if (buffer-file-name)
+ (find-file-noselect (buffer-file-name))) ; To check we have latest version
+ (verilog-save-font-no-change-functions
+ (verilog-save-scan-cache
+ (verilog-delete-auto-buffer)))))
+
+
+;;; Auto inject:
+;;
+
+(defun verilog-inject-auto ()
+ "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
+
+Any always @ blocks with sensitivity lists that match computed lists will
+be replaced with /*AS*/ comments.
+
+Any cells will get /*AUTOINST*/ added to the end of the pin list.
+Pins with have identical names will be deleted.
+
+Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
+support adding new ports. You may wish to delete older ports yourself.
+
+For example:
+
+ module ExampInject (i, o);
+ input i;
+ input j;
+ output o;
+ always @ (i or j)
+ o = i | j;
+ InstModule instName
+ (.foobar(baz),
+ j(j));
+ endmodule
+
+Typing \\[verilog-inject-auto] will make this into:
+
+ module ExampInject (i, o/*AUTOARG*/
+ // Inputs
+ j);
+ input i;
+ output o;
+ always @ (/*AS*/i or j)
+ o = i | j;
+ InstModule instName
+ (.foobar(baz),
+ /*AUTOINST*/
+ // Outputs
+ j(j));
+ endmodule"
+ (interactive)
+ (verilog-auto t))
+
+(defun verilog-inject-arg ()
+ "Inject AUTOARG into new code. See `verilog-inject-auto'."
+ ;; Presume one module per file.
+ (save-excursion
+ (goto-char (point-min))
+ (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
+ (let ((endmodp (save-excursion
+ (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
+ (point))))
+ ;; See if there's already a comment .. inside a comment so not verilog-re-search
+ (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
+ (verilog-re-search-forward-quick ";" nil t)
+ (backward-char 1)
+ (verilog-backward-syntactic-ws-quick)
+ (backward-char 1) ; Moves to paren that closes argdecl's
+ (when (looking-at ")")
+ (verilog-insert "/*AUTOARG*/")))))))
+
+(defun verilog-inject-sense ()
+ "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
+ (save-excursion
+ (goto-char (point-min))
+ (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
+ (let* ((start-pt (point))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ pre-sigs
+ got-sigs)
+ (backward-char 1)
+ (verilog-forward-sexp-ign-cmt 1)
+ (backward-char 1) ; End )
+ (when (not (verilog-re-search-backward-quick "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
+ (setq pre-sigs (verilog-signals-from-signame
+ (verilog-read-signals start-pt (point)))
+ got-sigs (verilog-auto-sense-sigs moddecls nil))
+ (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
+ (verilog-signals-not-in got-sigs pre-sigs)))
+ (delete-region start-pt (point))
+ (verilog-insert "/*AS*/")))))))
+
+(defun verilog-inject-inst ()
+ "Inject AUTOINST into new code. See `verilog-inject-auto'."
+ (save-excursion
+ (goto-char (point-min))
+ ;; It's hard to distinguish modules; we'll instead search for pins.
+ (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_$]+\\s *(\\s *[a-zA-Z0-9`_$]+\\s *)" nil t)
+ (verilog-backward-open-paren) ; Inst start
+ (cond
+ ((= (preceding-char) ?\#) ; #(...) parameter section, not pin. Skip.
+ (forward-char 1)
+ (verilog-forward-close-paren)) ; Parameters done
+ (t
+ (forward-char 1)
+ (let ((indent-pt (+ (current-column)))
+ (end-pt (save-excursion (verilog-forward-close-paren) (point))))
+ (cond ((verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
+ (goto-char end-pt)) ; Already there, continue search with next instance
+ (t
+ ;; Delete identical interconnect
+ (let ((case-fold-search nil)) ; So we don't convert upper-to-lower, etc
+ (while (verilog-re-search-forward-quick "\\.\\s *\\([a-zA-Z0-9`_$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
+ (delete-region (match-beginning 0) (match-end 0))
+ (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ; Keep it correct
+ (while (or (looking-at "[ \t\n\f,]+")
+ (looking-at "//[^\n]*"))
+ (delete-region (match-beginning 0) (match-end 0))
+ (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
+ (verilog-forward-close-paren)
+ (backward-char 1)
+ ;; Not verilog-re-search, as we don't want to strip comments
+ (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
+ (delete-region (match-beginning 0) (match-end 0)))
+ (verilog-insert "\n")
+ (verilog-insert-indent "/*AUTOINST*/")))))))))
+
+;;
+;; Auto diff:
+;;
+
+(defun verilog-diff-buffers-p (b1 b2 &optional whitespace regexp)
+ "Return nil if buffers B1 and B2 have same contents.
+Else, return point in B1 that first mismatches.
+If optional WHITESPACE true, ignore whitespace.
+If optional REGEXP, ignore differences matching it."
+ (save-excursion
+ (let* ((case-fold-search nil) ; compare-buffer-substrings cares
+ (p1 (with-current-buffer b1 (goto-char (point-min))))
+ (p2 (with-current-buffer b2 (goto-char (point-min))))
+ (maxp1 (with-current-buffer b1 (point-max)))
+ (maxp2 (with-current-buffer b2 (point-max)))
+ (op1 -1) (op2 -1)
+ progress size)
+ (while (not (and (eq p1 op1) (eq p2 op2)))
+ ;; If both windows have whitespace optionally skip over it.
+ (when whitespace
+ ;; skip-syntax-* doesn't count \n
+ (with-current-buffer b1
+ (goto-char p1)
+ (skip-chars-forward " \t\n\r\f\v")
+ (setq p1 (point)))
+ (with-current-buffer b2
+ (goto-char p2)
+ (skip-chars-forward " \t\n\r\f\v")
+ (setq p2 (point))))
+ (when regexp
+ (with-current-buffer b1
+ (goto-char p1)
+ (when (looking-at regexp)
+ (setq p1 (match-end 0))))
+ (with-current-buffer b2
+ (goto-char p2)
+ (when (looking-at regexp)
+ (setq p2 (match-end 0)))))
+ (setq size (min (- maxp1 p1) (- maxp2 p2)))
+ (setq progress (compare-buffer-substrings b2 p2 (+ size p2)
+ b1 p1 (+ size p1)))
+ (setq progress (if (zerop progress) size (1- (abs progress))))
+ (setq op1 p1 op2 p2
+ p1 (+ p1 progress)
+ p2 (+ p2 progress)))
+ ;; Return value
+ (if (and (eq p1 maxp1) (eq p2 maxp2))
+ nil p1))))
+
+(defun verilog-diff-file-with-buffer (f1 b2 &optional whitespace show)
+ "View the differences between file F1 and buffer B2.
+This requires the external program `diff-command' to be in your `exec-path',
+and uses `diff-switches' in which you may want to have \"-u\" flag.
+Ignores WHITESPACE if t, and writes output to stdout if SHOW."
+ ;; Similar to `diff-buffer-with-file' but works on XEmacs, and doesn't
+ ;; call `diff' as `diff' has different calling semantics on different
+ ;; versions of Emacs.
+ (if (not (file-exists-p f1))
+ (message "Buffer `%s' has no associated file on disk" (buffer-name b2))
+ (with-temp-buffer "*Verilog-Diff*"
+ (let ((outbuf (current-buffer))
+ (f2 (make-temp-file "vm-diff-auto-")))
+ (unwind-protect
+ (progn
+ (with-current-buffer b2
+ (save-restriction
+ (widen)
+ (write-region (point-min) (point-max) f2 nil 'nomessage)))
+ (call-process diff-command nil outbuf t
+ diff-switches ; User may want -u in diff-switches
+ (if whitespace "-b" "")
+ f1 f2)
+ ;; Print out results. Alternatively we could have call-processed
+ ;; ourself, but this way we can reuse diff switches
+ (when show
+ (with-current-buffer outbuf (message "%s" (buffer-string))))))
+ (sit-for 0)
+ (when (file-exists-p f2)
+ (delete-file f2))))))
+
+(defun verilog-diff-report (b1 b2 diffpt)
+ "Report differences detected with `verilog-diff-auto'.
+Differences are between buffers B1 and B2, starting at point
+DIFFPT. This function is called via `verilog-diff-function'."
+ (let ((name1 (with-current-buffer b1 (buffer-file-name))))
+ (verilog-warn-error "%s:%d: Difference in AUTO expansion found"
+ name1 (with-current-buffer b1
+ (count-lines (point-min) diffpt)))
+ (cond (noninteractive
+ (verilog-diff-file-with-buffer name1 b2 t t))
+ (t
+ (ediff-buffers b1 b2)))))
+
+(defun verilog-diff-auto ()
+ "Expand AUTOs in a temporary buffer and indicate any change.
+Whitespace is ignored when detecting differences, but once a
+difference is detected, whitespace differences may be shown.
+
+To call this from the command line, see \\[verilog-batch-diff-auto].
+
+The action on differences is selected with
+`verilog-diff-function'. The default is `verilog-diff-report'
+which will report an error and run `ediff' in interactive mode,
+or `diff' in batch mode."
+ (interactive)
+ (let ((b1 (current-buffer)) b2 diffpt
+ (name1 (buffer-file-name))
+ (newname "*Verilog-Diff*"))
+ (save-excursion
+ (when (get-buffer newname)
+ (kill-buffer newname))
+ (setq b2 (let (buffer-file-name) ; Else clone is upset
+ (clone-buffer newname)))
+ (with-current-buffer b2
+ ;; auto requires the filename, but can't have same filename in two
+ ;; buffers; so override both b1 and b2's names
+ (let ((buffer-file-name name1))
+ (unwind-protect
+ (progn
+ (with-current-buffer b1 (setq buffer-file-name nil))
+ (verilog-auto)
+ (when (not verilog-auto-star-save)
+ (verilog-delete-auto-star-implicit)))
+ ;; Restore name if unwind
+ (with-current-buffer b1 (setq buffer-file-name name1)))))
+ ;;
+ (setq diffpt (verilog-diff-buffers-p b1 b2 t verilog-diff-ignore-regexp))
+ (cond ((not diffpt)
+ (unless noninteractive (message "AUTO expansion identical"))
+ (kill-buffer newname)) ; Nice to cleanup after oneself
+ (t
+ (funcall verilog-diff-function b1 b2 diffpt)))
+ ;; Return result of compare
+ diffpt)))
+
+;;
+;; Auto save
+;;
+
+(defun verilog-auto-save-check ()
+ "On saving see if we need auto update."
+ (cond ((not verilog-auto-save-policy)) ; disabled
+ ((not (save-excursion
+ (save-match-data
+ (let ((case-fold-search nil))
+ (goto-char (point-min))
+ (re-search-forward "AUTO" nil t))))))
+ ((eq verilog-auto-save-policy 'force)
+ (verilog-auto))
+ ((not (buffer-modified-p)))
+ ((eq verilog-auto-update-tick (buffer-chars-modified-tick))) ; up-to-date
+ ((eq verilog-auto-save-policy 'detect)
+ (verilog-auto))
+ (t
+ (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
+ (verilog-auto))
+ ;; Don't ask again if didn't update
+ (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))))
+ (when (not verilog-auto-star-save)
+ (verilog-delete-auto-star-implicit))
+ nil) ; Always return nil -- we don't write the file ourselves
+
+(defun verilog-auto-read-locals ()
+ "Return file local variable segment at bottom of file."
+ (save-excursion
+ (goto-char (point-max))
+ (if (re-search-backward "Local Variables:" nil t)
+ (buffer-substring-no-properties (point) (point-max))
+ "")))
+
+(defun verilog-auto-reeval-locals (&optional force)
+ "Read file local variable segment at bottom of file if it has changed.
+If FORCE, always reread it."
+ (let ((curlocal (verilog-auto-read-locals)))
+ (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
+ (set (make-local-variable 'verilog-auto-last-file-locals) curlocal)
+ ;; Note this may cause this function to be recursively invoked,
+ ;; because hack-local-variables may call (verilog-mode)
+ ;; The above when statement will prevent it from recursing forever.
+ (hack-local-variables)
+ t)))
+
+;;; Auto creation:
+;;
+
+(defun verilog-auto-arg-ports (sigs message indent-pt)
+ "Print a list of ports for AUTOARG.
+Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
+ (when sigs
+ (when verilog-auto-arg-sort
+ (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
+ (insert "\n")
+ (indent-to indent-pt)
+ (insert message)
+ (insert "\n")
+ (let ((space ""))
+ (indent-to indent-pt)
+ (while sigs
+ (cond ((equal verilog-auto-arg-format 'single)
+ (insert space)
+ (indent-to indent-pt)
+ (setq space "\n"))
+ ;; verilog-auto-arg-format 'packed
+ ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
+ (insert "\n")
+ (indent-to indent-pt)
+ (setq space " "))
+ (t
+ (insert space)
+ (setq space " ")))
+ (insert (verilog-sig-name (car sigs)) ",")
+ (setq sigs (cdr sigs))))))
+
+(defun verilog-auto-arg ()
+ "Expand AUTOARG statements.
+Replace the argument declarations at the beginning of the
+module with ones automatically derived from input and output
+statements. This can be dangerous if the module is instantiated
+using position-based connections, so use only name-based when
+instantiating the resulting module. Long lines are split based
+on the `fill-column', see \\[set-fill-column].
+
+Limitations:
+ Concatenation and outputting partial buses is not supported.
+
+ Typedefs must match `verilog-typedef-regexp', which is disabled by default.
+
+For example:
+
+ module ExampArg (/*AUTOARG*/);
+ input i;
+ output o;
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampArg (/*AUTOARG*/
+ // Outputs
+ o,
+ // Inputs
+ i
+ );
+ input i;
+ output o;
+ endmodule
+
+The argument declarations may be printed in declaration order to
+best suit order based instantiations, or alphabetically, based on
+the `verilog-auto-arg-sort' variable.
+
+Formatting is controlled with `verilog-auto-arg-format' variable.
+
+Any ports declared between the ( and /*AUTOARG*/ are presumed to be
+predeclared and are not redeclared by AUTOARG. AUTOARG will make a
+conservative guess on adding a comma for the first signal, if you have
+any ifdefs or complicated expressions before the AUTOARG you will need
+to choose the comma yourself.
+
+Avoid declaring ports manually, as it makes code harder to maintain."
+ (save-excursion
+ (let* ((modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (skip-pins (aref (verilog-read-arg-pins) 0)))
+ (verilog-repair-open-comma)
+ (verilog-auto-arg-ports (verilog-signals-not-in
+ (verilog-decls-get-outputs moddecls)
+ skip-pins)
+ "// Outputs"
+ verilog-indent-level-declaration)
+ (verilog-auto-arg-ports (verilog-signals-not-in
+ (verilog-decls-get-inouts moddecls)
+ skip-pins)
+ "// Inouts"
+ verilog-indent-level-declaration)
+ (verilog-auto-arg-ports (verilog-signals-not-in
+ (verilog-decls-get-inputs moddecls)
+ skip-pins)
+ "// Inputs"
+ verilog-indent-level-declaration)
+ (verilog-repair-close-comma)
+ (unless (eq (char-before) ?/ )
+ (insert "\n"))
+ (indent-to verilog-indent-level-declaration))))
+
+(defun verilog-auto-assign-modport ()
+ "Expand AUTOASSIGNMODPORT statements, as part of \\[verilog-auto].
+Take input/output/inout statements from the specified interface
+and modport and use to build assignments into the modport, for
+making verification modules that connect to UVM interfaces.
+
+ The first parameter is the name of an interface.
+
+ The second parameter is a regexp of modports to read from in
+ that interface.
+
+ The third parameter is the instance name to use to dot reference into.
+
+ The optional fourth parameter is a regular expression, and only
+ signals matching the regular expression will be included.
+
+Limitations:
+
+ Interface names must be resolvable to filenames. See `verilog-auto-inst'.
+
+ Inouts are not supported, as assignments must be unidirectional.
+
+ If a signal is part of the interface header and in both a
+ modport and the interface itself, it will not be listed. (As
+ this would result in a syntax error when the connections are
+ made.)
+
+See the example in `verilog-auto-inout-modport'."
+ (save-excursion
+ (let* ((params (verilog-read-auto-params 3 4))
+ (submod (nth 0 params))
+ (modport-re (nth 1 params))
+ (inst-name (nth 2 params))
+ (regexp (nth 3 params))
+ direction-re submodi) ; direction argument not supported until requested
+ ;; Lookup position, etc of co-module
+ ;; Note this may raise an error
+ (when (setq submodi (verilog-modi-lookup submod t))
+ (let* ((indent-pt (current-indentation))
+ (submoddecls (verilog-modi-get-decls submodi))
+ (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
+ (sig-list-i (verilog-signals-in ; Decls doesn't have data types, must resolve
+ (verilog-decls-get-vars submoddecls)
+ (verilog-signals-not-in
+ (verilog-decls-get-inputs submodportdecls)
+ (verilog-decls-get-ports submoddecls))))
+ (sig-list-o (verilog-signals-in ; Decls doesn't have data types, must resolve
+ (verilog-decls-get-vars submoddecls)
+ (verilog-signals-not-in
+ (verilog-decls-get-outputs submodportdecls)
+ (verilog-decls-get-ports submoddecls)))))
+ (forward-line 1)
+ (setq sig-list-i (verilog-signals-edit-wire-reg
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-i regexp)
+ "input" direction-re))
+ sig-list-o (verilog-signals-edit-wire-reg
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-o regexp)
+ "output" direction-re)))
+ (setq sig-list-i (sort (copy-alist sig-list-i) `verilog-signals-sort-compare))
+ (setq sig-list-o (sort (copy-alist sig-list-o) `verilog-signals-sort-compare))
+ (when (or sig-list-i sig-list-o)
+ (verilog-insert-indent "// Beginning of automatic assignments from modport\n")
+ ;; Don't sort them so an upper AUTOINST will match the main module
+ (let ((sigs sig-list-o))
+ (while sigs
+ (verilog-insert-indent "assign " (verilog-sig-name (car sigs))
+ " = " inst-name
+ "." (verilog-sig-name (car sigs)) ";\n")
+ (setq sigs (cdr sigs))))
+ (let ((sigs sig-list-i))
+ (while sigs
+ (verilog-insert-indent "assign " inst-name
+ "." (verilog-sig-name (car sigs))
+ " = " (verilog-sig-name (car sigs)) ";\n")
+ (setq sigs (cdr sigs))))
+ (verilog-insert-indent "// End of automatics\n")))))))
+
+(defun verilog-auto-inst-port-map (_port-st)
+ nil)
+
+(defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
+(defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
+(defvar vl-modport nil "See `verilog-auto-inst'.") ; Prevent compile warning
+(defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
+(defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
+(defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
+(defvar vl-bits nil "See `verilog-auto-inst'.") ; Prevent compile warning
+(defvar vl-mbits nil "See `verilog-auto-inst'.") ; Prevent compile warning
+
+(defun verilog-auto-inst-port (port-st indent-pt moddecls tpl-list tpl-num for-star par-values)
+ "Print out an instantiation connection for this PORT-ST.
+Insert to INDENT-PT, use template TPL-LIST.
+@ are instantiation numbers, replaced with TPL-NUM.
+@\"(expression @)\" are evaluated, with @ as a variable.
+If FOR-STAR add comment it is a .* expansion.
+If PAR-VALUES replace final strings with these parameter values."
+ (let* ((port (verilog-sig-name port-st))
+ (tpl-ass (or (assoc port (car tpl-list))
+ (verilog-auto-inst-port-map port-st)))
+ ;; vl-* are documented for user use
+ (vl-name (verilog-sig-name port-st))
+ (vl-width (verilog-sig-width port-st))
+ (vl-modport (verilog-sig-modport port-st))
+ (vl-memory (verilog-sig-memory port-st))
+ (vl-mbits (if (verilog-sig-multidim port-st)
+ (verilog-sig-multidim-string port-st) ""))
+ (vl-bits (if (or verilog-auto-inst-vector
+ (not (assoc port (verilog-decls-get-signals moddecls)))
+ (not (equal (verilog-sig-bits port-st)
+ (verilog-sig-bits
+ (assoc port (verilog-decls-get-signals moddecls))))))
+ (or (verilog-sig-bits port-st) "")
+ ""))
+ (case-fold-search nil)
+ (check-values par-values)
+ tpl-net dflt-bits)
+ ;; Replace parameters in bit-width
+ (when (and check-values
+ (not (equal vl-bits "")))
+ (while check-values
+ (setq vl-bits (verilog-string-replace-matches
+ (concat "\\<" (nth 0 (car check-values)) "\\>")
+ (concat "(" (nth 1 (car check-values)) ")")
+ t t vl-bits)
+ vl-mbits (verilog-string-replace-matches
+ (concat "\\<" (nth 0 (car check-values)) "\\>")
+ (concat "(" (nth 1 (car check-values)) ")")
+ t t vl-mbits)
+ vl-memory (when vl-memory
+ (verilog-string-replace-matches
+ (concat "\\<" (nth 0 (car check-values)) "\\>")
+ (concat "(" (nth 1 (car check-values)) ")")
+ t t vl-memory))
+ check-values (cdr check-values)))
+ (setq vl-bits (verilog-simplify-range-expression vl-bits)
+ vl-mbits (verilog-simplify-range-expression vl-mbits)
+ vl-memory (when vl-memory (verilog-simplify-range-expression vl-memory))
+ vl-width (verilog-make-width-expression vl-bits))) ; Not in the loop for speed
+ ;; Default net value if not found
+ (setq dflt-bits (if (or (and (verilog-sig-bits port-st)
+ (verilog-sig-multidim port-st))
+ (verilog-sig-memory port-st))
+ (concat "/*" vl-mbits vl-bits
+ ;; .[ used to separate packed from unpacked
+ (if vl-memory "." "")
+ (if vl-memory vl-memory "")
+ "*/")
+ (concat vl-bits))
+ tpl-net (concat port
+ (if (and vl-modport
+ ;; .modport cannot be added if attachment is
+ ;; already declared as modport, VCS croaks
+ (let ((sig (assoc port (verilog-decls-get-interfaces moddecls))))
+ (not (and sig (verilog-sig-modport sig)))))
+ (concat "." vl-modport) "")
+ dflt-bits))
+ ;; Find template
+ (cond (tpl-ass ; Template of exact port name
+ (setq tpl-net (nth 1 tpl-ass)))
+ ((nth 1 tpl-list) ; Wildcards in template, search them
+ (let ((wildcards (nth 1 tpl-list)))
+ (while wildcards
+ (when (string-match (nth 0 (car wildcards)) port)
+ (setq tpl-ass (car wildcards) ; so allow @ parsing
+ tpl-net (replace-match (nth 1 (car wildcards))
+ t nil port)))
+ (setq wildcards (cdr wildcards))))))
+ ;; Parse Templated variable
+ (when tpl-ass
+ ;; Evaluate @"(lispcode)"
+ (when (string-match "@\".*[^\\]\"" tpl-net)
+ (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
+ (setq tpl-net
+ (concat
+ (substring tpl-net 0 (match-beginning 0))
+ (save-match-data
+ (let* ((expr (match-string 1 tpl-net))
+ (value
+ (progn
+ (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
+ (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
+ (prin1 (eval (car (read-from-string expr)))
+ (lambda (_ch) ())))))
+ (if (numberp value) (setq value (number-to-string value)))
+ value))
+ (substring tpl-net (match-end 0))))))
+ ;; Replace @ and [] magic variables in final output
+ (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
+ (setq tpl-net (verilog-string-replace-matches "\\[\\]\\[\\]" dflt-bits nil nil tpl-net))
+ (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
+ ;; Insert it
+ (indent-to indent-pt)
+ (insert "." port)
+ (unless (and verilog-auto-inst-dot-name
+ (equal port tpl-net))
+ (indent-to verilog-auto-inst-column)
+ (insert "(" tpl-net ")"))
+ (insert ",")
+ (cond (tpl-ass
+ (verilog-read-auto-template-hit tpl-ass)
+ (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
+ verilog-auto-inst-column))
+ ;; verilog-insert requires the complete comment in one call - including the newline
+ (cond ((equal verilog-auto-inst-template-numbers `lhs)
+ (verilog-insert " // Templated"
+ " LHS: " (nth 0 tpl-ass)
+ "\n"))
+ (verilog-auto-inst-template-numbers
+ (verilog-insert " // Templated"
+ " T" (int-to-string (nth 2 tpl-ass))
+ " L" (int-to-string (nth 3 tpl-ass))
+ "\n"))
+ (t
+ (verilog-insert " // Templated\n"))))
+ (for-star
+ (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
+ verilog-auto-inst-column))
+ (verilog-insert " // Implicit .*\n"))
+ (t
+ (insert "\n")))))
+;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
+;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
+;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
+
+(defun verilog-auto-inst-port-list (sig-list indent-pt moddecls tpl-list tpl-num for-star par-values)
+ "For `verilog-auto-inst' print a list of ports using `verilog-auto-inst-port'."
+ (when verilog-auto-inst-sort
+ (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare)))
+ (mapc (lambda (port)
+ (verilog-auto-inst-port port indent-pt moddecls
+ tpl-list tpl-num for-star par-values))
+ sig-list))
+
+(defun verilog-auto-inst-first ()
+ "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
+ ;; Do we need a trailing comma?
+ ;; There maybe an ifdef or something similar before us. What a mess. Thus
+ ;; to avoid trouble we only insert on preceding ) or *.
+ ;; Insert first port on new line
+ (insert "\n") ; Must insert before search, so point will move forward if insert comma
+ (save-excursion
+ (verilog-re-search-backward-quick "[^ \t\n\f]" nil nil)
+ (when (looking-at ")\\|\\*") ; Generally don't insert, unless we are fairly sure
+ (forward-char 1)
+ (insert ","))))
+
+(defun verilog-auto-star ()
+ "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
+
+If `verilog-auto-star-expand' is set, .* pins are treated if they were
+AUTOINST statements, otherwise they are ignored. For safety, Verilog mode
+will also ignore any .* that are not last in your pin list (this prevents
+it from deleting pins following the .* when it expands the AUTOINST.)
+
+On writing your file, unless `verilog-auto-star-save' is set, any
+non-templated expanded pins will be removed. You may do this at any time
+with \\[verilog-delete-auto-star-implicit].
+
+If you are converting a module to use .* for the first time, you may wish
+to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
+
+See `verilog-auto-inst' for examples, templates, and more information."
+ (when (verilog-auto-star-safe)
+ (verilog-auto-inst)))
+
+(defun verilog-auto-inst ()
+ "Expand AUTOINST statements, as part of \\[verilog-auto].
+Replace the pin connections to an instantiation or interface
+declaration with ones automatically derived from the module or
+interface header of the instantiated item.
+
+If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
+and delete them before saving unless `verilog-auto-star-save' is set.
+See `verilog-auto-star' for more information.
+
+The pins are printed in declaration order or alphabetically,
+based on the `verilog-auto-inst-sort' variable.
+
+Limitations:
+ Module names must be resolvable to filenames by adding a
+ `verilog-library-extensions', and being found in the same directory, or
+ by changing the variable `verilog-library-flags' or
+ `verilog-library-directories'. Macros `modname are translated through the
+ vh-{name} Emacs variable, if that is not found, it just ignores the \\=`.
+
+ In templates you must have one signal per line, ending in a ), or ));,
+ and have proper () nesting, including a final ); to end the template.
+
+ Typedefs must match `verilog-typedef-regexp', which is disabled by default.
+
+ SystemVerilog multidimensional input/output has only experimental support.
+
+ SystemVerilog .name syntax is used if `verilog-auto-inst-dot-name' is set.
+
+ Parameters referenced by the instantiation will remain symbolic, unless
+ `verilog-auto-inst-param-value' is set.
+
+ Gate primitives (and/or) may have AUTOINST for the purpose of
+ AUTOWIRE declarations, etc. Gates are the only case when
+ position based connections are passed.
+
+ The array part of arrayed instances are ignored; this may
+ result in undesirable default AUTOINST connections; use a
+ template instead.
+
+For example, first take the submodule InstModule.v:
+
+ module InstModule (o,i);
+ output [31:0] o;
+ input i;
+ wire [31:0] o = {32{i}};
+ endmodule
+
+This is then used in an upper level module:
+
+ module ExampInst (o,i);
+ output o;
+ input i;
+ InstModule instName
+ (/*AUTOINST*/);
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampInst (o,i);
+ output o;
+ input i;
+ InstModule instName
+ (/*AUTOINST*/
+ // Outputs
+ .ov (ov[31:0]),
+ // Inputs
+ .i (i));
+ endmodule
+
+Where the list of inputs and outputs came from the inst module.
+
+Exceptions:
+
+ Unless you are instantiating a module multiple times, or the module is
+ something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
+ It just makes for unmaintainable code. To sanitize signal names, try
+ vrename from URL `http://www.veripool.org'.
+
+ When you need to violate this suggestion there are two ways to list
+ exceptions, placing them before the AUTOINST, or using templates.
+
+ Any ports defined before the /*AUTOINST*/ are not included in the list of
+ automatics. This is similar to making a template as described below, but
+ is restricted to simple connections just like you normally make. Also note
+ that any signals before the AUTOINST will only be picked up by AUTOWIRE if
+ you have the appropriate // Input or // Output comment, and exactly the
+ same line formatting as AUTOINST itself uses.
+
+ InstModule instName
+ (// Inputs
+ .i (my_i_dont_mess_with_it),
+ /*AUTOINST*/
+ // Outputs
+ .ov (ov[31:0]));
+
+
+Templates:
+
+ For multiple instantiations based upon a single template, create a
+ commented out template:
+
+ /* InstModule AUTO_TEMPLATE (
+ .sig3 (sigz[]),
+ );
+ */
+
+ Templates go ABOVE the instantiation(s). When an instantiation is
+ expanded `verilog-mode' simply searches up for the closest template.
+ Thus you can have multiple templates for the same module, just alternate
+ between the template for an instantiation and the instantiation itself.
+ (For backward compatibility if no template is found above, it
+ will also look below, but do not use this behavior in new designs.)
+
+ The module name must be the same as the name of the module in the
+ instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
+ words and capitalized. Only signals that must be different for each
+ instantiation need to be listed.
+
+ Inside a template, a [] in a connection name (with nothing else
+ inside the brackets) will be replaced by the same bus subscript
+ as it is being connected to, or the [] will be removed if it is
+ a single bit signal.
+
+ Inside a template, a [][] in a connection name will behave
+ similarly to a [] for scalar or single-dimensional connection;
+ for a multidimensional connection it will print a comment
+ similar to that printed when a template is not used. Generally
+ it is a good idea to do this for all connections in a template,
+ as then they will work for any width signal, and with AUTOWIRE.
+ See PTL_BUS becoming PTL_BUSNEW below.
+
+ Inside a template, a [] in a connection name (with nothing else inside
+ the brackets) will be replaced by the same bus subscript as it is being
+ connected to, or the [] will be removed if it is a single bit signal.
+ Generally it is a good idea to do this for all connections in a template,
+ as then they will work for any width signal, and with AUTOWIRE. See
+ PTL_BUS becoming PTL_BUSNEW below.
+
+ If you have a complicated template, set `verilog-auto-inst-template-numbers'
+ to see which regexps are matching. Don't leave that mode set after
+ debugging is completed though, it will result in lots of extra differences
+ and merge conflicts.
+
+ Setting `verilog-auto-template-warn-unused' will report errors
+ if any template lines are unused.
+
+ For example:
+
+ /* InstModule AUTO_TEMPLATE (
+ .ptl_bus (ptl_busnew[]),
+ );
+ */
+ InstModule ms2m (/*AUTOINST*/);
+
+ Typing \\[verilog-auto] will make this into:
+
+ InstModule ms2m (/*AUTOINST*/
+ // Outputs
+ .NotInTemplate (NotInTemplate),
+ .ptl_bus (ptl_busnew[3:0]), // Templated
+ ....
+
+
+Multiple Module Templates:
+
+ The same template lines can be applied to multiple modules with
+ the syntax as follows:
+
+ /* InstModuleA AUTO_TEMPLATE
+ InstModuleB AUTO_TEMPLATE
+ InstModuleC AUTO_TEMPLATE
+ InstModuleD AUTO_TEMPLATE (
+ .ptl_bus (ptl_busnew[]),
+ );
+ */
+
+ Note there is only one AUTO_TEMPLATE opening parenthesis.
+
+@ Templates:
+
+ It is common to instantiate a cell multiple times, so templates make it
+ trivial to substitute part of the cell name into the connection name.
+
+ /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
+ .sig1 (sigx[@]),
+ .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
+ );
+ */
+
+ If no regular expression is provided immediately after the AUTO_TEMPLATE
+ keyword, then the @ character in any connection names will be replaced
+ with the instantiation number; the first digits found in the cell's
+ instantiation name.
+
+ If a regular expression is provided, the @ character will be replaced
+ with the first () grouping that matches against the cell name. Using a
+ regexp of `\\([0-9]+\\)' provides identical values for @ as when no
+ regexp is provided. If you use multiple layers of parenthesis,
+ `test\\([^0-9]+\\)_\\([0-9]+\\)' would replace @ with non-number
+ characters after test and before _, whereas
+ `\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)' would replace @ with the entire
+ match.
+
+ For example:
+
+ /* InstModule AUTO_TEMPLATE (
+ .ptl_mapvalidx (ptl_mapvalid[@]),
+ .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
+ );
+ */
+ InstModule ms2m (/*AUTOINST*/);
+
+ Typing \\[verilog-auto] will make this into:
+
+ InstModule ms2m (/*AUTOINST*/
+ // Outputs
+ .ptl_mapvalidx (ptl_mapvalid[2]),
+ .ptl_mapvalidp1x (ptl_mapvalid[3]));
+
+ Note the @ character was replaced with the 2 from \"ms2m\".
+
+ Alternatively, using a regular expression for @:
+
+ /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
+ .ptl_mapvalidx (@_ptl_mapvalid),
+ .ptl_mapvalidp1x (ptl_mapvalid_@),
+ );
+ */
+ InstModule ms2_FOO (/*AUTOINST*/);
+ InstModule ms2_BAR (/*AUTOINST*/);
+
+ Typing \\[verilog-auto] will make this into:
+
+ InstModule ms2_FOO (/*AUTOINST*/
+ // Outputs
+ .ptl_mapvalidx (FOO_ptl_mapvalid),
+ .ptl_mapvalidp1x (ptl_mapvalid_FOO));
+ InstModule ms2_BAR (/*AUTOINST*/
+ // Outputs
+ .ptl_mapvalidx (BAR_ptl_mapvalid),
+ .ptl_mapvalidp1x (ptl_mapvalid_BAR));
+
+
+Regexp Templates:
+
+ A template entry of the form
+
+ .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
+
+ will apply an Emacs style regular expression search for any port beginning
+ in pci_req followed by numbers and ending in _l and connecting that to
+ the pci_req_jtag_[] net, with the bus subscript coming from what matches
+ inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
+
+ Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
+ does the same thing. (Note a @ in the connection/replacement text is
+ completely different -- still use \\1 there!) Thus this is the same as
+ the above template:
+
+ .pci_req@_l (pci_req_jtag_[\\1]),
+
+ Here's another example to remove the _l, useful when naming conventions
+ specify _ alone to mean active low. Note the use of [] to keep the bus
+ subscript:
+
+ .\\(.*\\)_l (\\1_[]),
+
+Lisp Templates:
+
+ First any regular expression template is expanded.
+
+ If the syntax @\"( ... )\" is found in a connection, the expression in
+ quotes will be evaluated as a Lisp expression, with @ replaced by the
+ instantiation number. The MAPVALIDP1X example above would put @+1 modulo
+ 4 into the brackets. Quote all double-quotes inside the expression with
+ a leading backslash (\\\"...\\\"); or if the Lisp template is also a
+ regexp template backslash the backslash quote (\\\\\"...\\\\\").
+
+ There are special variables defined that are useful in these
+ Lisp functions:
+
+ vl-name Name portion of the input/output port.
+ vl-bits Bus bits portion of the input/output port (`[2:0]').
+ vl-mbits Multidimensional array bits for port (`[2:0][3:0]').
+ vl-width Width of the input/output port (`3' for [2:0]).
+ May be a (...) expression if bits isn't a constant.
+ vl-dir Direction of the pin input/output/inout/interface.
+ vl-modport The modport, if an interface with a modport.
+ vl-cell-type Module name/type of the cell (`InstModule').
+ vl-cell-name Instance name of the cell (`instName').
+
+ Normal Lisp variables may be used in expressions. See
+ `verilog-read-defines' which can set vh-{definename} variables for use
+ here. Also, any comments of the form:
+
+ /*AUTO_LISP(setq foo 1)*/
+
+ will evaluate any Lisp expression inside the parenthesis between the
+ beginning of the buffer and the point of the AUTOINST. This allows
+ functions to be defined or variables to be changed between instantiations.
+ (See also `verilog-auto-insert-lisp' if you want the output from your
+ lisp function to be inserted.)
+
+ Note that when using lisp expressions errors may occur when @ is not a
+ number; you may need to use the standard Emacs Lisp functions
+ `number-to-string' and `string-to-number'.
+
+ After the evaluation is completed, @ substitution and [] substitution
+ occur.
+
+For more information see the \\[verilog-faq] and forums at URL
+`http://www.veripool.org'."
+ (save-excursion
+ ;; Find beginning
+ (let* ((pt (point))
+ (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
+ (indent-pt (save-excursion (verilog-backward-open-paren)
+ (1+ (current-column))))
+ (verilog-auto-inst-column (max verilog-auto-inst-column
+ (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ submod submodi submoddecls
+ inst skip-pins tpl-list tpl-num did-first par-values)
+
+ ;; Find module name that is instantiated
+ (setq submod (verilog-read-inst-module)
+ inst (verilog-read-inst-name)
+ vl-cell-type submod
+ vl-cell-name inst
+ skip-pins (aref (verilog-read-inst-pins) 0))
+
+ ;; Parse any AUTO_LISP() before here
+ (verilog-read-auto-lisp (point-min) pt)
+
+ ;; Read parameters (after AUTO_LISP)
+ (setq par-values (and verilog-auto-inst-param-value
+ (verilog-read-inst-param-value)))
+
+ ;; Lookup position, etc of submodule
+ ;; Note this may raise an error
+ (when (and (not (member submod verilog-gate-keywords))
+ (setq submodi (verilog-modi-lookup submod t)))
+ (setq submoddecls (verilog-modi-get-decls submodi))
+ ;; If there's a number in the instantiation, it may be an argument to the
+ ;; automatic variable instantiation program.
+ (let* ((tpl-info (verilog-read-auto-template submod))
+ (tpl-regexp (aref tpl-info 0)))
+ (setq tpl-num (if (verilog-string-match-fold tpl-regexp inst)
+ (match-string 1 inst)
+ "")
+ tpl-list (aref tpl-info 1)))
+ ;; Find submodule's signals and dump
+ (let ((sig-list (and (equal (verilog-modi-get-type submodi) "interface")
+ (verilog-signals-not-in
+ (verilog-decls-get-vars submoddecls)
+ skip-pins)))
+ (vl-dir "interfaced"))
+ (when (and sig-list
+ verilog-auto-inst-interfaced-ports)
+ (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
+ ;; Note these are searched for in verilog-read-sub-decls.
+ (verilog-insert-indent "// Interfaced\n")
+ (verilog-auto-inst-port-list sig-list indent-pt moddecls
+ tpl-list tpl-num for-star par-values)))
+ (let ((sig-list (verilog-signals-not-in
+ (verilog-decls-get-interfaces submoddecls)
+ skip-pins))
+ (vl-dir "interface"))
+ (when sig-list
+ (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
+ ;; Note these are searched for in verilog-read-sub-decls.
+ (verilog-insert-indent "// Interfaces\n")
+ (verilog-auto-inst-port-list sig-list indent-pt moddecls
+ tpl-list tpl-num for-star par-values)))
+ (let ((sig-list (verilog-signals-not-in
+ (verilog-decls-get-outputs submoddecls)
+ skip-pins))
+ (vl-dir "output"))
+ (when sig-list
+ (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
+ (verilog-insert-indent "// Outputs\n")
+ (verilog-auto-inst-port-list sig-list indent-pt moddecls
+ tpl-list tpl-num for-star par-values)))
+ (let ((sig-list (verilog-signals-not-in
+ (verilog-decls-get-inouts submoddecls)
+ skip-pins))
+ (vl-dir "inout"))
+ (when sig-list
+ (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
+ (verilog-insert-indent "// Inouts\n")
+ (verilog-auto-inst-port-list sig-list indent-pt moddecls
+ tpl-list tpl-num for-star par-values)))
+ (let ((sig-list (verilog-signals-not-in
+ (verilog-decls-get-inputs submoddecls)
+ skip-pins))
+ (vl-dir "input"))
+ (when sig-list
+ (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
+ (verilog-insert-indent "// Inputs\n")
+ (verilog-auto-inst-port-list sig-list indent-pt moddecls
+ tpl-list tpl-num for-star par-values)))
+ ;; Kill extra semi
+ (save-excursion
+ (cond (did-first
+ (re-search-backward "," pt t)
+ (delete-char 1)
+ (insert ");")
+ (search-forward "\n") ; Added by inst-port
+ (delete-char -1)
+ (if (search-forward ")" nil t) ; From user, moved up a line
+ (delete-char -1))
+ (if (search-forward ";" nil t) ; Don't error if user had syntax error and forgot it
+ (delete-char -1)))))))))
+
+(defun verilog-auto-inst-param ()
+ "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
+Replace the parameter connections to an instantiation with ones
+automatically derived from the module header of the instantiated netlist.
+
+See \\[verilog-auto-inst] for limitations, and templates to customize the
+output.
+
+For example, first take the submodule InstModule.v:
+
+ module InstModule (o,i);
+ parameter PAR;
+ endmodule
+
+This is then used in an upper level module:
+
+ module ExampInst (o,i);
+ parameter PAR;
+ InstModule #(/*AUTOINSTPARAM*/)
+ instName (/*AUTOINST*/);
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampInst (o,i);
+ output o;
+ input i;
+ InstModule #(/*AUTOINSTPARAM*/
+ // Parameters
+ .PAR (PAR));
+ instName (/*AUTOINST*/);
+ endmodule
+
+Where the list of parameter connections come from the inst module.
+
+Templates:
+
+ You can customize the parameter connections using AUTO_TEMPLATEs,
+ just as you would with \\[verilog-auto-inst]."
+ (save-excursion
+ ;; Find beginning
+ (let* ((pt (point))
+ (indent-pt (save-excursion (verilog-backward-open-paren)
+ (1+ (current-column))))
+ (verilog-auto-inst-column (max verilog-auto-inst-column
+ (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ submod submodi submoddecls
+ inst skip-pins tpl-list tpl-num did-first)
+ ;; Find module name that is instantiated
+ (setq submod (save-excursion
+ ;; Get to the point where AUTOINST normally is to read the module
+ (verilog-re-search-forward-quick "[(;]" nil nil)
+ (verilog-read-inst-module))
+ inst (save-excursion
+ ;; Get to the point where AUTOINST normally is to read the module
+ (verilog-re-search-forward-quick "[(;]" nil nil)
+ (verilog-read-inst-name))
+ vl-cell-type submod
+ vl-cell-name inst
+ skip-pins (aref (verilog-read-inst-pins) 0))
+
+ ;; Parse any AUTO_LISP() before here
+ (verilog-read-auto-lisp (point-min) pt)
+
+ ;; Lookup position, etc of submodule
+ ;; Note this may raise an error
+ (when (setq submodi (verilog-modi-lookup submod t))
+ (setq submoddecls (verilog-modi-get-decls submodi))
+ ;; If there's a number in the instantiation, it may be an argument to the
+ ;; automatic variable instantiation program.
+ (let* ((tpl-info (verilog-read-auto-template submod))
+ (tpl-regexp (aref tpl-info 0)))
+ (setq tpl-num (if (verilog-string-match-fold tpl-regexp inst)
+ (match-string 1 inst)
+ "")
+ tpl-list (aref tpl-info 1)))
+ ;; Find submodule's signals and dump
+ (let ((sig-list (verilog-signals-not-in
+ (verilog-decls-get-gparams submoddecls)
+ skip-pins))
+ (vl-dir "parameter"))
+ (when sig-list
+ (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
+ ;; Note these are searched for in verilog-read-sub-decls.
+ (verilog-insert-indent "// Parameters\n")
+ (verilog-auto-inst-port-list sig-list indent-pt moddecls
+ tpl-list tpl-num nil nil)))
+ ;; Kill extra semi
+ (save-excursion
+ (cond (did-first
+ (re-search-backward "," pt t)
+ (delete-char 1)
+ (insert ")")
+ (search-forward "\n") ; Added by inst-port
+ (delete-char -1)
+ (if (search-forward ")" nil t) ; From user, moved up a line
+ (delete-char -1)))))))))
+
+(defun verilog-auto-reg ()
+ "Expand AUTOREG statements, as part of \\[verilog-auto].
+Make reg statements for any output that isn't already declared,
+and isn't a wire output from a block. `verilog-auto-wire-type'
+may be used to change the datatype of the declarations.
+
+Limitations:
+ This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
+
+ This does NOT work on memories, declare those yourself.
+
+An example:
+
+ module ExampReg (o,i);
+ output o;
+ input i;
+ /*AUTOREG*/
+ always o = i;
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampReg (o,i);
+ output o;
+ input i;
+ /*AUTOREG*/
+ // Beginning of automatic regs (for this module's undeclared outputs)
+ reg o;
+ // End of automatics
+ always o = i;
+ endmodule"
+ (save-excursion
+ ;; Point must be at insertion point.
+ (let* ((indent-pt (current-indentation))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (modsubdecls (verilog-modi-get-sub-decls modi))
+ (sig-list (verilog-signals-not-in
+ (verilog-decls-get-outputs moddecls)
+ (append (verilog-signals-with ; ignore typed signals
+ 'verilog-sig-type
+ (verilog-decls-get-outputs moddecls))
+ (verilog-decls-get-vars moddecls)
+ (verilog-decls-get-assigns moddecls)
+ (verilog-decls-get-consts moddecls)
+ (verilog-decls-get-gparams moddecls)
+ (verilog-subdecls-get-interfaced modsubdecls)
+ (verilog-subdecls-get-outputs modsubdecls)
+ (verilog-subdecls-get-inouts modsubdecls)))))
+ (when sig-list
+ (verilog-forward-or-insert-line)
+ (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
+ (verilog-insert-definition modi sig-list "reg" indent-pt nil)
+ (verilog-insert-indent "// End of automatics\n")))))
+
+(defun verilog-auto-reg-input ()
+ "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
+Make reg statements instantiation inputs that aren't already declared.
+This is useful for making a top level shell for testing the module that is
+to be instantiated.
+
+Limitations:
+ This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
+
+ This does NOT work on memories, declare those yourself.
+
+An example (see `verilog-auto-inst' for what else is going on here):
+
+ module ExampRegInput (o,i);
+ output o;
+ input i;
+ /*AUTOREGINPUT*/
+ InstModule instName
+ (/*AUTOINST*/);
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampRegInput (o,i);
+ output o;
+ input i;
+ /*AUTOREGINPUT*/
+ // Beginning of automatic reg inputs (for undeclared ...
+ reg [31:0] iv; // From inst of inst.v
+ // End of automatics
+ InstModule instName
+ (/*AUTOINST*/
+ // Outputs
+ .o (o[31:0]),
+ // Inputs
+ .iv (iv));
+ endmodule"
+ (save-excursion
+ ;; Point must be at insertion point.
+ (let* ((indent-pt (current-indentation))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (modsubdecls (verilog-modi-get-sub-decls modi))
+ (sig-list (verilog-signals-combine-bus
+ (verilog-signals-not-in
+ (append (verilog-subdecls-get-inputs modsubdecls)
+ (verilog-subdecls-get-inouts modsubdecls))
+ (append (verilog-decls-get-signals moddecls)
+ (verilog-decls-get-assigns moddecls))))))
+ (when sig-list
+ (verilog-forward-or-insert-line)
+ (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
+ (verilog-insert-definition modi sig-list "reg" indent-pt nil)
+ (verilog-insert-indent "// End of automatics\n")))))
+
+(defun verilog-auto-logic-setup ()
+ "Prepare variables due to AUTOLOGIC."
+ (unless verilog-auto-wire-type
+ (set (make-local-variable 'verilog-auto-wire-type)
+ "logic")))
+
+(defun verilog-auto-logic ()
+ "Expand AUTOLOGIC statements, as part of \\[verilog-auto].
+Make wire statements using the SystemVerilog logic keyword.
+This is currently equivalent to:
+
+ /*AUTOWIRE*/
+
+with the below at the bottom of the file
+
+ // Local Variables:
+ // verilog-auto-logic-type:\"logic\"
+ // End:
+
+In the future AUTOLOGIC may declare additional identifiers,
+while AUTOWIRE will not."
+ (save-excursion
+ (verilog-auto-logic-setup)
+ (verilog-auto-wire)))
+
+(defun verilog-auto-wire ()
+ "Expand AUTOWIRE statements, as part of \\[verilog-auto].
+Make wire statements for instantiations outputs that aren't
+already declared. `verilog-auto-wire-type' may be used to change
+the datatype of the declarations.
+
+Limitations:
+ This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
+ and all buses must have widths, such as those from AUTOINST, or using []
+ in AUTO_TEMPLATEs.
+
+ This does NOT work on memories or SystemVerilog .name connections,
+ declare those yourself.
+
+ Verilog mode will add \"Couldn't Merge\" comments to signals it cannot
+ determine how to bus together. This occurs when you have ports with
+ non-numeric or non-sequential bus subscripts. If Verilog mode
+ mis-guessed, you'll have to declare them yourself.
+
+An example (see `verilog-auto-inst' for what else is going on here):
+
+ module ExampWire (o,i);
+ output o;
+ input i;
+ /*AUTOWIRE*/
+ InstModule instName
+ (/*AUTOINST*/);
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampWire (o,i);
+ output o;
+ input i;
+ /*AUTOWIRE*/
+ // Beginning of automatic wires
+ wire [31:0] ov; // From inst of inst.v
+ // End of automatics
+ InstModule instName
+ (/*AUTOINST*/
+ // Outputs
+ .ov (ov[31:0]),
+ // Inputs
+ .i (i));
+ wire o = | ov;
+ endmodule"
+ (save-excursion
+ ;; Point must be at insertion point.
+ (let* ((indent-pt (current-indentation))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (modsubdecls (verilog-modi-get-sub-decls modi))
+ (sig-list (verilog-signals-combine-bus
+ (verilog-signals-not-in
+ (append (verilog-subdecls-get-outputs modsubdecls)
+ (verilog-subdecls-get-inouts modsubdecls))
+ (verilog-decls-get-signals moddecls)))))
+ (when sig-list
+ (verilog-forward-or-insert-line)
+ (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
+ (verilog-insert-definition modi sig-list "wire" indent-pt nil)
+ (verilog-insert-indent "// End of automatics\n")
+ ;; We used to optionally call verilog-pretty-declarations and
+ ;; verilog-pretty-expr here, but it's too slow on huge modules,
+ ;; plus makes everyone's module change. Finally those call
+ ;; syntax-ppss which is broken when change hooks are disabled.
+ ))))
+
+(defun verilog-auto-output ()
+ "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
+Make output statements for any output signal from an /*AUTOINST*/ that
+isn't an input to another AUTOINST. This is useful for modules which
+only instantiate other modules.
+
+Limitations:
+ This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
+
+ If placed inside the parenthesis of a module declaration, it creates
+ Verilog 2001 style, else uses Verilog 1995 style.
+
+ If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
+ instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
+
+ Typedefs must match `verilog-typedef-regexp', which is disabled by default.
+
+ Types are added to declarations if an AUTOLOGIC or
+ `verilog-auto-wire-type' is set to logic.
+
+ Signals matching `verilog-auto-output-ignore-regexp' are not included.
+
+An example (see `verilog-auto-inst' for what else is going on here):
+
+ module ExampOutput (ov,i);
+ input i;
+ /*AUTOOUTPUT*/
+ InstModule instName
+ (/*AUTOINST*/);
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampOutput (ov,i);
+ input i;
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [31:0] ov; // From inst of inst.v
+ // End of automatics
+ InstModule instName
+ (/*AUTOINST*/
+ // Outputs
+ .ov (ov[31:0]),
+ // Inputs
+ .i (i));
+ endmodule
+
+You may also provide an optional regular expression, in which case only
+signals matching the regular expression will be included. For example the
+same expansion will result from only extracting outputs starting with ov:
+
+ /*AUTOOUTPUT(\"^ov\")*/"
+ (save-excursion
+ ;; Point must be at insertion point.
+ (let* ((indent-pt (current-indentation))
+ (params (verilog-read-auto-params 0 1))
+ (regexp (nth 0 params))
+ (v2k (verilog-in-paren-quick))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (modsubdecls (verilog-modi-get-sub-decls modi))
+ (sig-list (verilog-signals-not-in
+ (verilog-subdecls-get-outputs modsubdecls)
+ (append (verilog-decls-get-outputs moddecls)
+ (verilog-decls-get-inouts moddecls)
+ (verilog-decls-get-inputs moddecls)
+ (verilog-subdecls-get-inputs modsubdecls)
+ (verilog-subdecls-get-inouts modsubdecls)))))
+ (when regexp
+ (setq sig-list (verilog-signals-matching-regexp
+ sig-list regexp)))
+ (setq sig-list (verilog-signals-not-matching-regexp
+ sig-list verilog-auto-output-ignore-regexp))
+ (verilog-forward-or-insert-line)
+ (when v2k (verilog-repair-open-comma))
+ (when sig-list
+ (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
+ (verilog-insert-definition modi sig-list "output" indent-pt v2k)
+ (verilog-insert-indent "// End of automatics\n"))
+ (when v2k (verilog-repair-close-comma)))))
+
+(defun verilog-auto-output-every ()
+ "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
+Make output statements for any signals that aren't primary inputs or
+outputs already. This makes every signal in the design an output. This is
+useful to get Synopsys to preserve every signal in the design, since it
+won't optimize away the outputs.
+
+An example:
+
+ module ExampOutputEvery (o,i,tempa,tempb);
+ output o;
+ input i;
+ /*AUTOOUTPUTEVERY*/
+ wire tempa = i;
+ wire tempb = tempa;
+ wire o = tempb;
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampOutputEvery (o,i,tempa,tempb);
+ output o;
+ input i;
+ /*AUTOOUTPUTEVERY*/
+ // Beginning of automatic outputs (every signal)
+ output tempb;
+ output tempa;
+ // End of automatics
+ wire tempa = i;
+ wire tempb = tempa;
+ wire o = tempb;
+ endmodule
+
+You may also provide an optional regular expression, in which case only
+signals matching the regular expression will be included. For example the
+same expansion will result from only extracting outputs starting with ov:
+
+ /*AUTOOUTPUTEVERY(\"^ov\")*/"
+ (save-excursion
+ ;;Point must be at insertion point
+ (let* ((indent-pt (current-indentation))
+ (params (verilog-read-auto-params 0 1))
+ (regexp (nth 0 params))
+ (v2k (verilog-in-paren-quick))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (sig-list (verilog-signals-combine-bus
+ (verilog-signals-not-in
+ (verilog-decls-get-signals moddecls)
+ (verilog-decls-get-ports moddecls)))))
+ (when regexp
+ (setq sig-list (verilog-signals-matching-regexp
+ sig-list regexp)))
+ (setq sig-list (verilog-signals-not-matching-regexp
+ sig-list verilog-auto-output-ignore-regexp))
+ (verilog-forward-or-insert-line)
+ (when v2k (verilog-repair-open-comma))
+ (when sig-list
+ (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
+ (verilog-insert-definition modi sig-list "output" indent-pt v2k)
+ (verilog-insert-indent "// End of automatics\n"))
+ (when v2k (verilog-repair-close-comma)))))
+
+(defun verilog-auto-input ()
+ "Expand AUTOINPUT statements, as part of \\[verilog-auto].
+Make input statements for any input signal into an /*AUTOINST*/ that
+isn't declared elsewhere inside the module. This is useful for modules which
+only instantiate other modules.
+
+Limitations:
+ This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
+
+ If placed inside the parenthesis of a module declaration, it creates
+ Verilog 2001 style, else uses Verilog 1995 style.
+
+ If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
+ instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
+
+ Typedefs must match `verilog-typedef-regexp', which is disabled by default.
+
+ Types are added to declarations if an AUTOLOGIC or
+ `verilog-auto-wire-type' is set to logic.
+
+ Signals matching `verilog-auto-input-ignore-regexp' are not included.
+
+An example (see `verilog-auto-inst' for what else is going on here):
+
+ module ExampInput (ov,i);
+ output [31:0] ov;
+ /*AUTOINPUT*/
+ InstModule instName
+ (/*AUTOINST*/);
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampInput (ov,i);
+ output [31:0] ov;
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input i; // From inst of inst.v
+ // End of automatics
+ InstModule instName
+ (/*AUTOINST*/
+ // Outputs
+ .ov (ov[31:0]),
+ // Inputs
+ .i (i));
+ endmodule
+
+You may also provide an optional regular expression, in which case only
+signals matching the regular expression will be included. For example the
+same expansion will result from only extracting inputs starting with i:
+
+ /*AUTOINPUT(\"^i\")*/"
+ (save-excursion
+ (let* ((indent-pt (current-indentation))
+ (params (verilog-read-auto-params 0 1))
+ (regexp (nth 0 params))
+ (v2k (verilog-in-paren-quick))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (modsubdecls (verilog-modi-get-sub-decls modi))
+ (sig-list (verilog-signals-not-in
+ (verilog-subdecls-get-inputs modsubdecls)
+ (append (verilog-decls-get-inputs moddecls)
+ (verilog-decls-get-inouts moddecls)
+ (verilog-decls-get-outputs moddecls)
+ (verilog-decls-get-vars moddecls)
+ (verilog-decls-get-consts moddecls)
+ (verilog-decls-get-gparams moddecls)
+ (verilog-subdecls-get-interfaced modsubdecls)
+ (verilog-subdecls-get-outputs modsubdecls)
+ (verilog-subdecls-get-inouts modsubdecls)))))
+ (when regexp
+ (setq sig-list (verilog-signals-matching-regexp
+ sig-list regexp)))
+ (setq sig-list (verilog-signals-not-matching-regexp
+ sig-list verilog-auto-input-ignore-regexp))
+ (verilog-forward-or-insert-line)
+ (when v2k (verilog-repair-open-comma))
+ (when sig-list
+ (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
+ (verilog-insert-definition modi sig-list "input" indent-pt v2k)
+ (verilog-insert-indent "// End of automatics\n"))
+ (when v2k (verilog-repair-close-comma)))))
+
+(defun verilog-auto-inout ()
+ "Expand AUTOINOUT statements, as part of \\[verilog-auto].
+Make inout statements for any inout signal in an /*AUTOINST*/ that
+isn't declared elsewhere inside the module.
+
+Limitations:
+ This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
+
+ If placed inside the parenthesis of a module declaration, it creates
+ Verilog 2001 style, else uses Verilog 1995 style.
+
+ If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
+ instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
+
+ Typedefs must match `verilog-typedef-regexp', which is disabled by default.
+
+ Types are added to declarations if an AUTOLOGIC or
+ `verilog-auto-wire-type' is set to logic.
+
+ Signals matching `verilog-auto-inout-ignore-regexp' are not included.
+
+An example (see `verilog-auto-inst' for what else is going on here):
+
+ module ExampInout (ov,i);
+ input i;
+ /*AUTOINOUT*/
+ InstModule instName
+ (/*AUTOINST*/);
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampInout (ov,i);
+ input i;
+ /*AUTOINOUT*/
+ // Beginning of automatic inouts (from unused autoinst inouts)
+ inout [31:0] ov; // From inst of inst.v
+ // End of automatics
+ InstModule instName
+ (/*AUTOINST*/
+ // Inouts
+ .ov (ov[31:0]),
+ // Inputs
+ .i (i));
+ endmodule
+
+You may also provide an optional regular expression, in which case only
+signals matching the regular expression will be included. For example the
+same expansion will result from only extracting inouts starting with i:
+
+ /*AUTOINOUT(\"^i\")*/"
+ (save-excursion
+ ;; Point must be at insertion point.
+ (let* ((indent-pt (current-indentation))
+ (params (verilog-read-auto-params 0 1))
+ (regexp (nth 0 params))
+ (v2k (verilog-in-paren-quick))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (modsubdecls (verilog-modi-get-sub-decls modi))
+ (sig-list (verilog-signals-not-in
+ (verilog-subdecls-get-inouts modsubdecls)
+ (append (verilog-decls-get-outputs moddecls)
+ (verilog-decls-get-inouts moddecls)
+ (verilog-decls-get-inputs moddecls)
+ (verilog-subdecls-get-inputs modsubdecls)
+ (verilog-subdecls-get-outputs modsubdecls)))))
+ (when regexp
+ (setq sig-list (verilog-signals-matching-regexp
+ sig-list regexp)))
+ (setq sig-list (verilog-signals-not-matching-regexp
+ sig-list verilog-auto-inout-ignore-regexp))
+ (verilog-forward-or-insert-line)
+ (when v2k (verilog-repair-open-comma))
+ (when sig-list
+ (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
+ (verilog-insert-definition modi sig-list "inout" indent-pt v2k)
+ (verilog-insert-indent "// End of automatics\n"))
+ (when v2k (verilog-repair-close-comma)))))
+
+(defun verilog-auto-inout-module (&optional complement all-in)
+ "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
+Take input/output/inout statements from the specified module and insert
+into the current module. This is useful for making null templates and
+shell modules which need to have identical I/O with another module.
+Any I/O which are already defined in this module will not be redefined.
+For the complement of this function, see `verilog-auto-inout-comp',
+and to make monitors with all inputs, see `verilog-auto-inout-in'.
+
+Limitations:
+ If placed inside the parenthesis of a module declaration, it creates
+ Verilog 2001 style, else uses Verilog 1995 style.
+
+ Concatenation and outputting partial buses is not supported.
+
+ Module names must be resolvable to filenames. See `verilog-auto-inst'.
+
+ Signals are not inserted in the same order as in the original module,
+ though they will appear to be in the same order to an AUTOINST
+ instantiating either module.
+
+ Signals declared as \"output reg\" or \"output wire\" etc will
+ lose the wire/reg declaration so that shell modules may
+ generate those outputs differently. However, \"output logic\"
+ is propagated.
+
+An example:
+
+ module ExampShell (/*AUTOARG*/);
+ /*AUTOINOUTMODULE(\"ExampMain\")*/
+ endmodule
+
+ module ExampMain (i,o,io);
+ input i;
+ output o;
+ inout io;
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampShell (/*AUTOARG*/i,o,io);
+ /*AUTOINOUTMODULE(\"ExampMain\")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output o;
+ inout io;
+ input i;
+ // End of automatics
+ endmodule
+
+You may also provide an optional regular expression, in which case only
+signals matching the regular expression will be included. For example the
+same expansion will result from only extracting signals starting with i:
+
+ /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
+
+You may also provide an optional third argument regular
+expression, in which case only signals which have that pin
+direction and data type matching that regular expression will be
+included. This matches against everything before the signal name
+in the declaration, for example against \"input\" (single
+bit), \"output logic\" (direction and type) or
+\"output [1:0]\" (direction and implicit type). You also
+probably want to skip spaces in your regexp.
+
+For example, the below will result in matching the output \"o\"
+against the previous example's module:
+
+ /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/
+
+You may also provide an optional fourth argument regular
+expression, which if not \"\" only signals which do NOT match
+that expression are included."
+ ;; Beware spacing of quotes in above as can mess up Emacs indenter
+ (save-excursion
+ (let* ((params (verilog-read-auto-params 1 4))
+ (submod (nth 0 params))
+ (regexp (nth 1 params))
+ (direction-re (nth 2 params))
+ (not-re (nth 3 params))
+ submodi)
+ ;; Lookup position, etc of co-module
+ ;; Note this may raise an error
+ (when (setq submodi (verilog-modi-lookup submod t))
+ (let* ((indent-pt (current-indentation))
+ (v2k (verilog-in-paren-quick))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (submoddecls (verilog-modi-get-decls submodi))
+ (sig-list-i (verilog-signals-not-in
+ (cond (all-in
+ (append
+ (verilog-decls-get-inputs submoddecls)
+ (verilog-decls-get-inouts submoddecls)
+ (verilog-decls-get-outputs submoddecls)))
+ (complement
+ (verilog-decls-get-outputs submoddecls))
+ (t (verilog-decls-get-inputs submoddecls)))
+ (append (verilog-decls-get-inputs moddecls))))
+ (sig-list-o (verilog-signals-not-in
+ (cond (all-in nil)
+ (complement
+ (verilog-decls-get-inputs submoddecls))
+ (t (verilog-decls-get-outputs submoddecls)))
+ (append (verilog-decls-get-outputs moddecls))))
+ (sig-list-io (verilog-signals-not-in
+ (cond (all-in nil)
+ (t (verilog-decls-get-inouts submoddecls)))
+ (append (verilog-decls-get-inouts moddecls))))
+ (sig-list-if (verilog-signals-not-in
+ (verilog-decls-get-interfaces submoddecls)
+ (append (verilog-decls-get-interfaces moddecls)))))
+ (forward-line 1)
+ (setq sig-list-i (verilog-signals-edit-wire-reg
+ (verilog-signals-not-matching-regexp
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-i regexp)
+ "input" direction-re) not-re))
+ sig-list-o (verilog-signals-edit-wire-reg
+ (verilog-signals-not-matching-regexp
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-o regexp)
+ "output" direction-re) not-re))
+ sig-list-io (verilog-signals-edit-wire-reg
+ (verilog-signals-not-matching-regexp
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-io regexp)
+ "inout" direction-re) not-re))
+ sig-list-if (verilog-signals-not-matching-regexp
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-if regexp)
+ "interface" direction-re) not-re))
+ (when v2k (verilog-repair-open-comma))
+ (when (or sig-list-i sig-list-o sig-list-io sig-list-if)
+ (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
+ ;; Don't sort them so an upper AUTOINST will match the main module
+ (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
+ (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
+ (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
+ (verilog-insert-definition modi sig-list-if "interface" indent-pt v2k t)
+ (verilog-insert-indent "// End of automatics\n"))
+ (when v2k (verilog-repair-close-comma)))))))
+
+(defun verilog-auto-inout-comp ()
+ "Expand AUTOINOUTCOMP statements, as part of \\[verilog-auto].
+Take input/output/inout statements from the specified module and
+insert the inverse into the current module (inputs become outputs
+and vice-versa.) This is useful for making test and stimulus
+modules which need to have complementing I/O with another module.
+Any I/O which are already defined in this module will not be
+redefined. For the complement of this function, see
+`verilog-auto-inout-module'.
+
+Limitations:
+ If placed inside the parenthesis of a module declaration, it creates
+ Verilog 2001 style, else uses Verilog 1995 style.
+
+ Concatenation and outputting partial buses is not supported.
+
+ Module names must be resolvable to filenames. See `verilog-auto-inst'.
+
+ Signals are not inserted in the same order as in the original module,
+ though they will appear to be in the same order to an AUTOINST
+ instantiating either module.
+
+An example:
+
+ module ExampShell (/*AUTOARG*/);
+ /*AUTOINOUTCOMP(\"ExampMain\")*/
+ endmodule
+
+ module ExampMain (i,o,io);
+ input i;
+ output o;
+ inout io;
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampShell (/*AUTOARG*/i,o,io);
+ /*AUTOINOUTCOMP(\"ExampMain\")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ output i;
+ inout io;
+ input o;
+ // End of automatics
+ endmodule
+
+You may also provide an optional regular expression, in which case only
+signals matching the regular expression will be included. For example the
+same expansion will result from only extracting signals starting with i:
+
+ /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/
+
+You may also provide an optional third argument regular
+expression, in which case only signals which have that pin
+direction and data type matching that regular expression will be
+included. This matches against everything before the signal name
+in the declaration, for example against \"input\" (single
+bit), \"output logic\" (direction and type)
+or \"output [1:0]\" (direction and implicit type). You also
+probably want to skip spaces in your regexp.
+
+For example, the below will result in matching the output \"o\"
+against the previous example's module:
+
+ /*AUTOINOUTCOMP(\"ExampMain\",\"\",\"^output.*\")*/
+
+You may also provide an optional fourth argument regular
+expression, which if not \"\" only signals which do NOT match
+that expression are included."
+ ;; Beware spacing of quotes in above as can mess up Emacs indenter
+ (verilog-auto-inout-module t nil))
+
+(defun verilog-auto-inout-in ()
+ "Expand AUTOINOUTIN statements, as part of \\[verilog-auto].
+Take input/output/inout statements from the specified module and
+insert them as all inputs into the current module. This is
+useful for making monitor modules which need to see all signals
+as inputs based on another module. Any I/O which are already
+defined in this module will not be redefined. See also
+`verilog-auto-inout-module'.
+
+Limitations:
+ If placed inside the parenthesis of a module declaration, it creates
+ Verilog 2001 style, else uses Verilog 1995 style.
+
+ Concatenation and outputting partial buses is not supported.
+
+ Module names must be resolvable to filenames. See `verilog-auto-inst'.
+
+ Signals are not inserted in the same order as in the original module,
+ though they will appear to be in the same order to an AUTOINST
+ instantiating either module.
+
+An example:
+
+ module ExampShell (/*AUTOARG*/);
+ /*AUTOINOUTIN(\"ExampMain\")*/
+ endmodule
+
+ module ExampMain (i,o,io);
+ input i;
+ output o;
+ inout io;
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampShell (/*AUTOARG*/i,o,io);
+ /*AUTOINOUTIN(\"ExampMain\")*/
+ // Beginning of automatic in/out/inouts (from specific module)
+ input i;
+ input io;
+ input o;
+ // End of automatics
+ endmodule
+
+You may also provide an optional regular expression, in which case only
+signals matching the regular expression will be included. For example the
+same expansion will result from only extracting signals starting with i:
+
+ /*AUTOINOUTIN(\"ExampMain\",\"^i\")*/"
+ (verilog-auto-inout-module nil t))
+
+(defun verilog-auto-inout-param ()
+ "Expand AUTOINOUTPARAM statements, as part of \\[verilog-auto].
+Take input/output/inout statements from the specified module and insert
+into the current module. This is useful for making null templates and
+shell modules which need to have identical I/O with another module.
+Any I/O which are already defined in this module will not be redefined.
+For the complement of this function, see `verilog-auto-inout-comp',
+and to make monitors with all inputs, see `verilog-auto-inout-in'.
+
+Limitations:
+ If placed inside the parenthesis of a module declaration, it creates
+ Verilog 2001 style, else uses Verilog 1995 style.
+
+ Module names must be resolvable to filenames. See `verilog-auto-inst'.
+
+ Parameters are inserted in the same order as in the original module.
+
+ Parameters do not have values, which is SystemVerilog 2009 syntax.
+
+An example:
+
+ module ExampShell ();
+ /*AUTOINOUTPARAM(\"ExampMain\")*/
+ endmodule
+
+ module ExampMain ();
+ parameter PARAM = 22;
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampShell (/*AUTOARG*/i,o,io);
+ /*AUTOINOUTPARAM(\"ExampMain\")*/
+ // Beginning of automatic parameters (from specific module)
+ parameter PARAM;
+ // End of automatics
+ endmodule
+
+You may also provide an optional regular expression, in which case only
+parameters matching the regular expression will be included. For example the
+same expansion will result from only extracting parameters starting with i:
+
+ /*AUTOINOUTPARAM(\"ExampMain\",\"^i\")*/"
+ (save-excursion
+ (let* ((params (verilog-read-auto-params 1 2))
+ (submod (nth 0 params))
+ (regexp (nth 1 params))
+ submodi)
+ ;; Lookup position, etc of co-module
+ ;; Note this may raise an error
+ (when (setq submodi (verilog-modi-lookup submod t))
+ (let* ((indent-pt (current-indentation))
+ (v2k (verilog-in-paren-quick))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (submoddecls (verilog-modi-get-decls submodi))
+ (sig-list-p (verilog-signals-not-in
+ (verilog-decls-get-gparams submoddecls)
+ (append (verilog-decls-get-gparams moddecls)))))
+ (forward-line 1)
+ (setq sig-list-p (verilog-signals-matching-regexp sig-list-p regexp))
+ (when v2k (verilog-repair-open-comma))
+ (when sig-list-p
+ (verilog-insert-indent "// Beginning of automatic parameters (from specific module)\n")
+ ;; Don't sort them so an upper AUTOINST will match the main module
+ (verilog-insert-definition modi sig-list-p "parameter" indent-pt v2k t)
+ (verilog-insert-indent "// End of automatics\n"))
+ (when v2k (verilog-repair-close-comma)))))))
+
+(defun verilog-auto-inout-modport ()
+ "Expand AUTOINOUTMODPORT statements, as part of \\[verilog-auto].
+Take input/output/inout statements from the specified interface
+and modport and insert into the current module. This is useful
+for making verification modules that connect to UVM interfaces.
+
+ The first parameter is the name of an interface.
+
+ The second parameter is a regexp of modports to read from in
+ that interface.
+
+ The optional third parameter is a regular expression, and only
+ signals matching the regular expression will be included.
+
+Limitations:
+ If placed inside the parenthesis of a module declaration, it creates
+ Verilog 2001 style, else uses Verilog 1995 style.
+
+ Interface names must be resolvable to filenames. See `verilog-auto-inst'.
+
+As with other autos, any inputs/outputs declared in the module
+will suppress the AUTO from redeclaring an inputs/outputs by
+the same name.
+
+An example:
+
+ interface ExampIf
+ ( input logic clk );
+ logic req_val;
+ logic [7:0] req_dat;
+ clocking mon_clkblk @(posedge clk);
+ input req_val;
+ input req_dat;
+ endclocking
+ modport mp(clocking mon_clkblk);
+ endinterface
+
+ module ExampMain
+ ( input clk,
+ /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
+ // Beginning of automatic in/out/inouts (from modport)
+ input [7:0] req_dat,
+ input req_val
+ // End of automatics
+ );
+ /*AUTOASSIGNMODPORT(\"ExampIf\" \"mp\")*/
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ ...
+ module ExampMain
+ ( input clk,
+ /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
+ // Beginning of automatic in/out/inouts (from modport)
+ input req_dat,
+ input req_val
+ // End of automatics
+ );
+
+If the modport is part of a UVM monitor/driver class, this
+creates a wrapper module that may be used to instantiate the
+driver/monitor using AUTOINST in the testbench."
+ (save-excursion
+ (let* ((params (verilog-read-auto-params 2 3))
+ (submod (nth 0 params))
+ (modport-re (nth 1 params))
+ (regexp (nth 2 params))
+ direction-re submodi) ; direction argument not supported until requested
+ ;; Lookup position, etc of co-module
+ ;; Note this may raise an error
+ (when (setq submodi (verilog-modi-lookup submod t))
+ (let* ((indent-pt (current-indentation))
+ (v2k (verilog-in-paren-quick))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (submoddecls (verilog-modi-get-decls submodi))
+ (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
+ (sig-list-i (verilog-signals-in ; Decls doesn't have data types, must resolve
+ (verilog-decls-get-vars submoddecls)
+ (verilog-signals-not-in
+ (verilog-decls-get-inputs submodportdecls)
+ (append (verilog-decls-get-ports submoddecls)
+ (verilog-decls-get-ports moddecls)))))
+ (sig-list-o (verilog-signals-in ; Decls doesn't have data types, must resolve
+ (verilog-decls-get-vars submoddecls)
+ (verilog-signals-not-in
+ (verilog-decls-get-outputs submodportdecls)
+ (append (verilog-decls-get-ports submoddecls)
+ (verilog-decls-get-ports moddecls)))))
+ (sig-list-io (verilog-signals-in ; Decls doesn't have data types, must resolve
+ (verilog-decls-get-vars submoddecls)
+ (verilog-signals-not-in
+ (verilog-decls-get-inouts submodportdecls)
+ (append (verilog-decls-get-ports submoddecls)
+ (verilog-decls-get-ports moddecls))))))
+ (forward-line 1)
+ (setq sig-list-i (verilog-signals-edit-wire-reg
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-i regexp)
+ "input" direction-re))
+ sig-list-o (verilog-signals-edit-wire-reg
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-o regexp)
+ "output" direction-re))
+ sig-list-io (verilog-signals-edit-wire-reg
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-io regexp)
+ "inout" direction-re)))
+ (when v2k (verilog-repair-open-comma))
+ (when (or sig-list-i sig-list-o sig-list-io)
+ (verilog-insert-indent "// Beginning of automatic in/out/inouts (from modport)\n")
+ ;; Don't sort them so an upper AUTOINST will match the main module
+ (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
+ (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
+ (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
+ (verilog-insert-indent "// End of automatics\n"))
+ (when v2k (verilog-repair-close-comma)))))))
+
+(defun verilog-auto-insert-lisp ()
+ "Expand AUTOINSERTLISP statements, as part of \\[verilog-auto].
+The Lisp code provided is called before other AUTOS are expanded,
+and the Lisp code generally will call `insert' to insert text
+into the current file beginning on the line after the
+AUTOINSERTLISP.
+
+See also AUTOINSERTLAST and `verilog-auto-insert-last' which
+executes after (as opposed to before) other AUTOs.
+
+See also AUTO_LISP, which takes a Lisp expression and evaluates
+it during `verilog-auto-inst' but does not insert any text.
+
+An example:
+
+ module ExampInsertLisp;
+ /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/
+ endmodule
+
+ // For this example we declare the function in the
+ // module's file itself. Often you'd define it instead
+ // in a site-start.el or init file.
+ /*
+ Local Variables:
+ eval:
+ (defun my-verilog-insert-hello (who)
+ (insert (concat \"initial $write(\\\"hello \" who \"\\\");\\n\")))
+ End:
+ */
+
+Typing \\[verilog-auto] will call my-verilog-insert-hello and
+expand the above into:
+
+ // Beginning of automatic insert lisp
+ initial $write(\"hello world\");
+ // End of automatics
+
+You can also call an external program and insert the returned
+text:
+
+ /*AUTOINSERTLISP(insert (shell-command-to-string \"echo //hello\"))*/
+ // Beginning of automatic insert lisp
+ //hello
+ // End of automatics"
+ (save-excursion
+ ;; Point is at end of /*AUTO...*/
+ (let* ((indent-pt (current-indentation))
+ (cmd-end-pt (save-excursion (search-backward ")")
+ (forward-char)
+ (point))) ; Closing paren
+ (cmd-beg-pt (save-excursion (goto-char cmd-end-pt)
+ (backward-sexp 1) ; Inside comment
+ (point))) ; Beginning paren
+ (cmd (buffer-substring-no-properties cmd-beg-pt cmd-end-pt)))
+ (verilog-forward-or-insert-line)
+ ;; Some commands don't move point (like insert-file) so we always
+ ;; add the begin/end comments, then delete it if not needed
+ (verilog-insert-indent "// Beginning of automatic insert lisp\n")
+ (verilog-insert-indent "// End of automatics\n")
+ (forward-line -1)
+ (eval (read cmd))
+ (forward-line -1)
+ (setq verilog-scan-cache-tick nil) ; Clear cache; inserted unknown text
+ (verilog-delete-empty-auto-pair))))
+
+(defun verilog-auto-insert-last ()
+ "Expand AUTOINSERTLAST statements, as part of \\[verilog-auto].
+The Lisp code provided is called after all other AUTOS have been
+expanded, and the Lisp code generally will call `insert' to
+insert text into the current file beginning on the line after the
+AUTOINSERTLAST.
+
+Other than when called (after AUTOs are expanded), the functionality
+is otherwise identical to AUTOINSERTLISP and `verilog-auto-insert-lisp' which
+executes before (as opposed to after) other AUTOs.
+
+See `verilog-auto-insert-lisp' for examples."
+ (verilog-auto-insert-lisp))
+
+(defun verilog-auto-sense-sigs (moddecls presense-sigs)
+ "Return list of signals for current AUTOSENSE block."
+ (let* ((sigss (save-excursion
+ (search-forward ")")
+ (verilog-read-always-signals)))
+ (sig-list (verilog-signals-not-params
+ (verilog-signals-not-in (verilog-alw-get-inputs sigss)
+ (append (and (not verilog-auto-sense-include-inputs)
+ (verilog-alw-get-outputs-delayed sigss))
+ (and (not verilog-auto-sense-include-inputs)
+ (verilog-alw-get-outputs-immediate sigss))
+ (verilog-alw-get-temps sigss)
+ (verilog-decls-get-consts moddecls)
+ (verilog-decls-get-gparams moddecls)
+ presense-sigs)))))
+ sig-list))
+
+(defun verilog-auto-sense ()
+ "Expand AUTOSENSE statements, as part of \\[verilog-auto].
+Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
+with one automatically derived from all inputs declared in the always
+statement. Signals that are generated within the same always block are NOT
+placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
+Long lines are split based on the `fill-column', see \\[set-fill-column].
+
+Limitations:
+ Verilog does not allow memories (multidimensional arrays) in sensitivity
+ lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
+
+Constant signals:
+ AUTOSENSE cannot always determine if a \\=`define is a constant or a signal
+ (it could be in an include file for example). If a \\=`define or other signal
+ is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
+ declaration anywhere in the module (parenthesis are required):
+
+ /* AUTO_CONSTANT ( \\=`this_is_really_constant_dont_autosense_it ) */
+
+ Better yet, use a parameter, which will be understood to be constant
+ automatically.
+
+OOps!
+ If AUTOSENSE makes a mistake, please report it. (First try putting
+ a begin/end after your always!) As a workaround, if a signal that
+ shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
+ If a signal should be in the sensitivity list wasn't, placing it before
+ the /*AUTOSENSE*/ comment will prevent it from being deleted when the
+ autos are updated (or added if it occurs there already).
+
+An example:
+
+ always @ (/*AS*/) begin
+ /* AUTO_CONSTANT (\\=`constant) */
+ outin = ina | inb | \\=`constant;
+ out = outin;
+ end
+
+Typing \\[verilog-auto] will make this into:
+
+ always @ (/*AS*/ina or inb) begin
+ /* AUTO_CONSTANT (\\=`constant) */
+ outin = ina | inb | \\=`constant;
+ out = outin;
+ end
+
+Note in Verilog 2001, you can often get the same result from the new @*
+operator. (This was added to the language in part due to AUTOSENSE!)
+
+ always @* begin
+ outin = ina | inb | \\=`constant;
+ out = outin;
+ end"
+ (save-excursion
+ ;; Find beginning
+ (let* ((start-pt (save-excursion
+ (verilog-re-search-backward-quick "(" nil t)
+ (point)))
+ (indent-pt (save-excursion
+ (or (and (goto-char start-pt) (1+ (current-column)))
+ (current-indentation))))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (sig-memories (verilog-signals-memory
+ (verilog-decls-get-vars moddecls)))
+ sig-list not-first presense-sigs)
+ ;; Read signals in always, eliminate outputs from sense list
+ (setq presense-sigs (verilog-signals-from-signame
+ (save-excursion
+ (verilog-read-signals start-pt (point)))))
+ (setq sig-list (verilog-auto-sense-sigs moddecls presense-sigs))
+ (when sig-memories
+ (let ((tlen (length sig-list)))
+ (setq sig-list (verilog-signals-not-in sig-list sig-memories))
+ (if (not (eq tlen (length sig-list))) (verilog-insert " /*memory or*/ "))))
+ (if (and presense-sigs ; Add a "or" if not "(.... or /*AUTOSENSE*/"
+ (save-excursion (goto-char (point))
+ (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
+ (verilog-re-search-backward-quick "\\s-" start-pt t)
+ (while (looking-at "\\s-`endif")
+ (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
+ (verilog-re-search-backward-quick "\\s-" start-pt t))
+ (not (looking-at "\\s-or\\b"))))
+ (setq not-first t))
+ (setq sig-list (sort sig-list `verilog-signals-sort-compare))
+ (while sig-list
+ (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
+ (insert "\n")
+ (indent-to indent-pt)
+ (if not-first (insert "or ")))
+ (not-first (insert " or ")))
+ (insert (verilog-sig-name (car sig-list)))
+ (setq sig-list (cdr sig-list)
+ not-first t)))))
+
+(defun verilog-auto-reset ()
+ "Expand AUTORESET statements, as part of \\[verilog-auto].
+Replace the /*AUTORESET*/ comment with code to initialize all
+registers set elsewhere in the always block.
+
+Limitations:
+ AUTORESET will not clear memories.
+
+ AUTORESET uses <= if the signal has a <= assignment in the block,
+ else it uses =.
+
+ If <= is used, all = assigned variables are ignored if
+ `verilog-auto-reset-blocking-in-non' is nil; they are presumed
+ to be temporaries.
+
+/*AUTORESET*/ presumes that any signals mentioned between the previous
+begin/case/if statement and the AUTORESET comment are being reset manually
+and should not be automatically reset. This includes omitting any signals
+used on the right hand side of assignments.
+
+By default, AUTORESET will include the width of the signal in the
+autos, SystemVerilog designs may want to change this. To control
+this behavior, see `verilog-auto-reset-widths'. In some cases
+AUTORESET must use a \\='0 assignment and it will print NOWIDTH; use
+`verilog-auto-reset-widths' unbased to prevent this.
+
+AUTORESET ties signals to deasserted, which is presumed to be zero.
+Signals that match `verilog-active-low-regexp' will be deasserted by tying
+them to a one.
+
+AUTORESET may try to reset arrays or structures that cannot be
+reset by a simple assignment, resulting in compile errors. This
+is a feature to be taken as a hint that you need to reset these
+signals manually (or put them into a \"\\=`ifdef NEVER signal<=\\=`0;
+\\=`endif\" so Verilog-Mode ignores them.)
+
+An example:
+
+ always @(posedge clk or negedge reset_l) begin
+ if (!reset_l) begin
+ c <= 1;
+ /*AUTORESET*/
+ end
+ else begin
+ a <= in_a;
+ b <= in_b;
+ c <= in_c;
+ end
+ end
+
+Typing \\[verilog-auto] will make this into:
+
+ always @(posedge core_clk or negedge reset_l) begin
+ if (!reset_l) begin
+ c <= 1;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ a <= 0;
+ b = 0; // if `verilog-auto-reset-blocking-in-non' true
+ // End of automatics
+ end
+ else begin
+ a <= in_a;
+ b = in_b;
+ c <= in_c;
+ end
+ end"
+
+ (interactive)
+ (save-excursion
+ ;; Find beginning
+ (let* ((indent-pt (current-indentation))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (all-list (verilog-decls-get-signals moddecls))
+ sigss sig-list dly-list prereset-sigs)
+ ;; Read signals in always, eliminate outputs from reset list
+ (setq prereset-sigs (verilog-signals-from-signame
+ (save-excursion
+ (verilog-read-signals
+ (save-excursion
+ (verilog-re-search-backward-quick
+ "\\(@\\|\\<\\(begin\\|if\\|case[xz]?\\|always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
+ (point))
+ (point)))))
+ (save-excursion
+ (verilog-re-search-backward-quick "\\(@\\|\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
+ (setq sigss (verilog-read-always-signals)))
+ (setq dly-list (verilog-alw-get-outputs-delayed sigss))
+ (setq sig-list (verilog-signals-not-in-struct
+ (append
+ (verilog-alw-get-outputs-delayed sigss)
+ (when (or (not (verilog-alw-get-uses-delayed sigss))
+ verilog-auto-reset-blocking-in-non)
+ (verilog-alw-get-outputs-immediate sigss)))
+ (append
+ (verilog-alw-get-temps sigss)
+ prereset-sigs)))
+ (setq sig-list (sort sig-list `verilog-signals-sort-compare))
+ (when sig-list
+ (insert "\n");
+ (verilog-insert-indent "// Beginning of autoreset for uninitialized flops\n");
+ (while sig-list
+ (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ; As sig-list has no widths
+ (car sig-list))))
+ (indent-to indent-pt)
+ (insert (verilog-sig-name sig)
+ (if (assoc (verilog-sig-name sig) dly-list)
+ (concat " <= " verilog-assignment-delay)
+ " = ")
+ (verilog-sig-tieoff sig)
+ ";\n")
+ (setq sig-list (cdr sig-list))))
+ (verilog-insert-indent "// End of automatics")))))
+
+(defun verilog-auto-tieoff ()
+ "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
+Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
+signals to deasserted.
+
+/*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
+input/output list as another module, but no internals. Specifically, it
+finds all outputs in the module, and if that input is not otherwise declared
+as a register or wire, creates a tieoff.
+
+AUTORESET ties signals to deasserted, which is presumed to be zero.
+Signals that match `verilog-active-low-regexp' will be deasserted by tying
+them to a one.
+
+You can add signals you do not want included in AUTOTIEOFF with
+`verilog-auto-tieoff-ignore-regexp'.
+
+`verilog-auto-wire-type' may be used to change the datatype of
+the declarations.
+
+`verilog-auto-reset-widths' may be used to change how the tieoff
+value's width is generated.
+
+An example of making a stub for another module:
+
+ module ExampStub (/*AUTOINST*/);
+ /*AUTOINOUTPARAM(\"Foo\")*/
+ /*AUTOINOUTMODULE(\"Foo\")*/
+ /*AUTOTIEOFF*/
+ // verilator lint_off UNUSED
+ wire _unused_ok = &{1\\='b0,
+ /*AUTOUNUSED*/
+ 1\\='b0};
+ // verilator lint_on UNUSED
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampStub (/*AUTOINST*/...);
+ /*AUTOINOUTPARAM(\"Foo\")*/
+ /*AUTOINOUTMODULE(\"Foo\")*/
+ // Beginning of autotieoff
+ output [2:0] foo;
+ // End of automatics
+
+ /*AUTOTIEOFF*/
+ // Beginning of autotieoff
+ wire [2:0] foo = 3\\='b0;
+ // End of automatics
+ ...
+ endmodule"
+ (interactive)
+ (save-excursion
+ ;; Find beginning
+ (let* ((indent-pt (current-indentation))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (modsubdecls (verilog-modi-get-sub-decls modi))
+ (sig-list (verilog-signals-not-in
+ (verilog-decls-get-outputs moddecls)
+ (append (verilog-decls-get-vars moddecls)
+ (verilog-decls-get-assigns moddecls)
+ (verilog-decls-get-consts moddecls)
+ (verilog-decls-get-gparams moddecls)
+ (verilog-subdecls-get-interfaced modsubdecls)
+ (verilog-subdecls-get-outputs modsubdecls)
+ (verilog-subdecls-get-inouts modsubdecls)))))
+ (setq sig-list (verilog-signals-not-matching-regexp
+ sig-list verilog-auto-tieoff-ignore-regexp))
+ (when sig-list
+ (verilog-forward-or-insert-line)
+ (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
+ (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
+ (verilog-modi-cache-add-vars modi sig-list) ; Before we trash list
+ (while sig-list
+ (let ((sig (car sig-list)))
+ (cond ((equal verilog-auto-tieoff-declaration "assign")
+ (indent-to indent-pt)
+ (insert "assign " (verilog-sig-name sig)))
+ (t
+ (verilog-insert-one-definition sig verilog-auto-tieoff-declaration indent-pt)))
+ (indent-to (max 48 (+ indent-pt 40)))
+ (insert "= " (verilog-sig-tieoff sig)
+ ";\n")
+ (setq sig-list (cdr sig-list))))
+ (verilog-insert-indent "// End of automatics\n")))))
+
+(defun verilog-auto-undef ()
+ "Expand AUTOUNDEF statements, as part of \\[verilog-auto].
+Take any \\=`defines since the last AUTOUNDEF in the current file
+and create \\=`undefs for them. This is used to insure that
+file-local defines do not pollute the global \\=`define name space.
+
+Limitations:
+ AUTOUNDEF presumes any identifier following \\=`define is the
+ name of a define. Any \\=`ifdefs are ignored.
+
+ AUTOUNDEF suppresses creating an \\=`undef for any define that was
+ \\=`undefed before the AUTOUNDEF. This may be used to work around
+ the ignoring of \\=`ifdefs as shown below.
+
+An example:
+
+ \\=`define XX_FOO
+ \\=`define M_BAR(x)
+ \\=`define M_BAZ
+ ...
+ \\=`ifdef NEVER
+ \\=`undef M_BAZ // Emacs will see this and not \\=`undef M_BAZ
+ \\=`endif
+ ...
+ /*AUTOUNDEF*/
+
+Typing \\[verilog-auto] will make this into:
+
+ ...
+ /*AUTOUNDEF*/
+ // Beginning of automatic undefs
+ \\=`undef XX_FOO
+ \\=`undef M_BAR
+ // End of automatics
+
+You may also provide an optional regular expression, in which case only
+defines the regular expression will be undefed."
+ (save-excursion
+ (let* ((params (verilog-read-auto-params 0 1))
+ (regexp (nth 0 params))
+ (indent-pt (current-indentation))
+ (end-pt (point))
+ defs def)
+ (save-excursion
+ ;; Scan from start of file, or last AUTOUNDEF
+ (or (verilog-re-search-backward-quick "/\\*AUTOUNDEF\\>" end-pt t)
+ (goto-char (point-min)))
+ (while (verilog-re-search-forward-quick
+ "`\\(define\\|undef\\)\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" end-pt t)
+ (cond ((equal (match-string-no-properties 1) "define")
+ (setq def (match-string-no-properties 2))
+ (when (and (or (not regexp)
+ (string-match regexp def))
+ (not (member def defs))) ; delete-dups not in 21.1
+ (setq defs (cons def defs))))
+ (t
+ (setq defs (delete (match-string-no-properties 2) defs))))))
+ ;; Insert
+ (setq defs (sort defs 'string<))
+ (when defs
+ (verilog-forward-or-insert-line)
+ (verilog-insert-indent "// Beginning of automatic undefs\n")
+ (while defs
+ (verilog-insert-indent "`undef " (car defs) "\n")
+ (setq defs (cdr defs)))
+ (verilog-insert-indent "// End of automatics\n")))))
+
+(defun verilog-auto-unused ()
+ "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
+Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
+input and inout signals.
+
+/*AUTOUNUSED*/ is used to make stub modules; modules that have the same
+input/output list as another module, but no internals. Specifically, it
+finds all inputs and inouts in the module, and if that input is not otherwise
+used, adds it to a comma separated list.
+
+The comma separated list is intended to be used to create a _unused_ok
+signal. Using the exact name \"_unused_ok\" for name of the temporary
+signal is recommended as it will insure maximum forward compatibility, it
+also makes lint warnings easy to understand; ignore any unused warnings
+with \"unused\" in the signal name.
+
+To reduce simulation time, the _unused_ok signal should be forced to a
+constant to prevent wiggling. The easiest thing to do is use a
+reduction-and with 1\\='b0 as shown.
+
+This way all unused signals are in one place, making it convenient to add
+your tool's specific pragmas around the assignment to disable any unused
+warnings.
+
+You can add signals you do not want included in AUTOUNUSED with
+`verilog-auto-unused-ignore-regexp'.
+
+An example of making a stub for another module:
+
+ module ExampStub (/*AUTOINST*/);
+ /*AUTOINOUTPARAM(\"Examp\")*/
+ /*AUTOINOUTMODULE(\"Examp\")*/
+ /*AUTOTIEOFF*/
+ // verilator lint_off UNUSED
+ wire _unused_ok = &{1\\='b0,
+ /*AUTOUNUSED*/
+ 1\\='b0};
+ // verilator lint_on UNUSED
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ ...
+ // verilator lint_off UNUSED
+ wire _unused_ok = &{1\\='b0,
+ /*AUTOUNUSED*/
+ // Beginning of automatics
+ unused_input_a,
+ unused_input_b,
+ unused_input_c,
+ // End of automatics
+ 1\\='b0};
+ // verilator lint_on UNUSED
+ endmodule"
+ (interactive)
+ (save-excursion
+ ;; Find beginning
+ (let* ((indent-pt (progn (search-backward "/*") (current-column)))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (modsubdecls (verilog-modi-get-sub-decls modi))
+ (sig-list (verilog-signals-not-in
+ (append (verilog-decls-get-inputs moddecls)
+ (verilog-decls-get-inouts moddecls))
+ (append (verilog-subdecls-get-inputs modsubdecls)
+ (verilog-subdecls-get-inouts modsubdecls)))))
+ (setq sig-list (verilog-signals-not-matching-regexp
+ sig-list verilog-auto-unused-ignore-regexp))
+ (when sig-list
+ (verilog-forward-or-insert-line)
+ (verilog-insert-indent "// Beginning of automatic unused inputs\n")
+ (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
+ (while sig-list
+ (let ((sig (car sig-list)))
+ (indent-to indent-pt)
+ (insert (verilog-sig-name sig) ",\n")
+ (setq sig-list (cdr sig-list))))
+ (verilog-insert-indent "// End of automatics\n")))))
+
+(defun verilog-enum-ascii (signm elim-regexp)
+ "Convert an enum name SIGNM to an ascii string for insertion.
+Remove user provided prefix ELIM-REGEXP."
+ (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
+ (let ((case-fold-search t))
+ ;; All upper becomes all lower for readability
+ (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
+
+(defun verilog-auto-ascii-enum ()
+ "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
+Create a register to contain the ASCII decode of an enumerated signal type.
+This will allow trace viewers to show the ASCII name of states.
+
+First, parameters are built into an enumeration using the synopsys enum
+comment. The comment must be between the keyword and the symbol.
+\(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
+
+Next, registers which that enum applies to are also tagged with the same
+enum.
+
+Finally, an AUTOASCIIENUM command is used.
+
+ The first parameter is the name of the signal to be decoded.
+
+ The second parameter is the name to store the ASCII code into. For the
+ signal foo, I suggest the name _foo__ascii, where the leading _ indicates
+ a signal that is just for simulation, and the magic characters _ascii
+ tell viewers like Dinotrace to display in ASCII format.
+
+ The third optional parameter is a string which will be removed
+ from the state names. It defaults to \"\" which removes nothing.
+
+ The fourth optional parameter is \"onehot\" to force one-hot
+ decoding. If unspecified, if and only if the first parameter
+ width is 2^(number of states in enum) and does NOT match the
+ width of the enum, the signal is assumed to be a one-hot
+ decode. Otherwise, it's a normal encoded state vector.
+
+ `verilog-auto-wire-type' may be used to change the datatype of
+ the declarations.
+
+ \"auto enum\" may be used in place of \"synopsys enum\".
+
+An example:
+
+ //== State enumeration
+ parameter [2:0] // synopsys enum state_info
+ SM_IDLE = 3\\='b000,
+ SM_SEND = 3\\='b001,
+ SM_WAIT1 = 3\\='b010;
+ //== State variables
+ reg [2:0] /* synopsys enum state_info */
+ state_r; /* synopsys state_vector state_r */
+ reg [2:0] /* synopsys enum state_info */
+ state_e1;
+
+ /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
+
+Typing \\[verilog-auto] will make this into:
+
+ ... same front matter ...
+
+ /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
+ // Beginning of automatic ASCII enum decoding
+ reg [39:0] state_ascii_r; // Decode of state_r
+ always @(state_r) begin
+ case ({state_r})
+ SM_IDLE: state_ascii_r = \"idle \";
+ SM_SEND: state_ascii_r = \"send \";
+ SM_WAIT1: state_ascii_r = \"wait1\";
+ default: state_ascii_r = \"%Erro\";
+ endcase
+ end
+ // End of automatics"
+ (save-excursion
+ (let* ((params (verilog-read-auto-params 2 4))
+ (undecode-name (nth 0 params))
+ (ascii-name (nth 1 params))
+ (elim-regexp (and (nth 2 params)
+ (not (equal (nth 2 params) ""))
+ (nth 2 params)))
+ (one-hot-flag (nth 3 params))
+ ;;
+ (indent-pt (current-indentation))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ ;;
+ (sig-list-consts (append (verilog-decls-get-consts moddecls)
+ (verilog-decls-get-gparams moddecls)))
+ (sig-list-all (verilog-decls-get-iovars moddecls))
+ ;;
+ (undecode-sig (or (assoc undecode-name sig-list-all)
+ (error "%s: Signal `%s' not found in design"
+ (verilog-point-text) undecode-name)))
+ (undecode-enum (or (verilog-sig-enum undecode-sig)
+ (error "%s: Signal `%s' does not have an enum tag"
+ (verilog-point-text) undecode-name)))
+ ;;
+ (enum-sigs (verilog-signals-not-in
+ (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
+ (error "%s: No state definitions for `%s'"
+ (verilog-point-text) undecode-enum))
+ nil))
+ ;;
+ (one-hot (or
+ (string-match "onehot" (or one-hot-flag ""))
+ (and ; width(enum) != width(sig)
+ (or (not (verilog-sig-bits (car enum-sigs)))
+ (not (equal (verilog-sig-width (car enum-sigs))
+ (verilog-sig-width undecode-sig))))
+ ;; count(enums) == width(sig)
+ (equal (number-to-string (length enum-sigs))
+ (verilog-sig-width undecode-sig)))))
+ (enum-chars 0)
+ (ascii-chars 0))
+ ;;
+ ;; Find number of ascii chars needed
+ (let ((tmp-sigs enum-sigs))
+ (while tmp-sigs
+ (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
+ ascii-chars (max ascii-chars (length (verilog-enum-ascii
+ (verilog-sig-name (car tmp-sigs))
+ elim-regexp)))
+ tmp-sigs (cdr tmp-sigs))))
+ ;;
+ (verilog-forward-or-insert-line)
+ (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
+ (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
+ (concat "Decode of " undecode-name) nil nil))))
+ (verilog-insert-definition modi decode-sig-list "reg" indent-pt nil))
+ ;;
+ (verilog-insert-indent "always @(" undecode-name ") begin\n")
+ (setq indent-pt (+ indent-pt verilog-indent-level))
+ (verilog-insert-indent "case ({" undecode-name "})\n")
+ (setq indent-pt (+ indent-pt verilog-case-indent))
+ ;;
+ (let ((tmp-sigs enum-sigs)
+ (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n"
+ (+ (if one-hot 9 1) (max 8 enum-chars))
+ ascii-name ascii-chars))
+ (errname (substring "%Error" 0 (min 6 ascii-chars))))
+ (while tmp-sigs
+ (verilog-insert-indent
+ (concat
+ (format chrfmt
+ (concat (if one-hot "(")
+ ;; Use enum-sigs length as that's numeric
+ ;; verilog-sig-width undecode-sig might not be.
+ (if one-hot (number-to-string (length enum-sigs)))
+ ;; We use a shift instead of var[index]
+ ;; so that a non-one hot value will show as error.
+ (if one-hot "'b1<<")
+ (verilog-sig-name (car tmp-sigs))
+ (if one-hot ")") ":")
+ (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
+ elim-regexp))))
+ (setq tmp-sigs (cdr tmp-sigs)))
+ (verilog-insert-indent (format chrfmt "default:" errname)))
+ ;;
+ (setq indent-pt (- indent-pt verilog-case-indent))
+ (verilog-insert-indent "endcase\n")
+ (setq indent-pt (- indent-pt verilog-indent-level))
+ (verilog-insert-indent "end\n"
+ "// End of automatics\n"))))
+
+(defun verilog-auto-templated-rel ()
+ "Replace Templated relative line numbers with absolute line numbers.
+Internal use only. This hacks around the line numbers in AUTOINST Templates
+being different from the final output's line numbering."
+ (let ((templateno 0) (template-line (list 0)) (buf-line 1))
+ ;; Find line number each template is on
+ ;; Count lines as we go, as otherwise it's O(n^2) to use count-lines
+ (goto-char (point-min))
+ (while (not (eobp))
+ (when (looking-at ".*AUTO_TEMPLATE")
+ (setq templateno (1+ templateno))
+ (setq template-line (cons buf-line template-line)))
+ (setq buf-line (1+ buf-line))
+ (forward-line 1))
+ (setq template-line (nreverse template-line))
+ ;; Replace T# L# with absolute line number
+ (goto-char (point-min))
+ (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
+ (replace-match
+ (concat " Templated "
+ (int-to-string (+ (nth (string-to-number (match-string 1))
+ template-line)
+ (string-to-number (match-string 2)))))
+ t t))))
+
+(defun verilog-auto-template-lint ()
+ "Check AUTO_TEMPLATEs for unused lines.
+Enable with `verilog-auto-template-warn-unused'."
+ (let ((name1 (or (buffer-file-name) (buffer-name))))
+ (save-excursion
+ (goto-char (point-min))
+ (while (re-search-forward
+ "^\\s-*/?\\*?\\s-*[a-zA-Z0-9`_$]+\\s-+AUTO_TEMPLATE" nil t)
+ (let* ((tpl-info (verilog-read-auto-template-middle))
+ (tpl-list (aref tpl-info 1))
+ (tlines (append (nth 0 tpl-list) (nth 1 tpl-list)))
+ tpl-ass)
+ (while tlines
+ (setq tpl-ass (car tlines)
+ tlines (cdr tlines))
+ ;;
+ (unless (or (not (eval-when-compile (fboundp 'make-hash-table))) ; Not supported, no warning
+ (not verilog-auto-template-hits)
+ (gethash (vector (nth 2 tpl-ass) (nth 3 tpl-ass))
+ verilog-auto-template-hits))
+ (verilog-warn-error "%s:%d: AUTO_TEMPLATE line unused: \".%s (%s)\""
+ name1
+ (+ (elt tpl-ass 3) ; Template line number
+ (count-lines (point-min) (point)))
+ (elt tpl-ass 0) (elt tpl-ass 1))
+ )))))))
+
+
+;;; Auto top level:
+;;
+
+(defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing an arg
+ "Expand AUTO statements.
+Look for any /*AUTO...*/ commands in the code, as used in
+instantiations or argument headers. Update the list of signals
+following the /*AUTO...*/ command.
+
+Use \\[verilog-delete-auto] to remove the AUTOs.
+
+Use \\[verilog-diff-auto] to see differences in AUTO expansion.
+
+Use \\[verilog-inject-auto] to insert AUTOs for the first time.
+
+Use \\[verilog-faq] for a pointer to frequently asked questions.
+
+For new users, we recommend setting `verilog-case-fold' to nil
+and `verilog-auto-arg-sort' to t.
+
+The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
+called before and after this function, respectively.
+
+For example:
+ module ModuleName (/*AUTOARG*/);
+ /*AUTOINPUT*/
+ /*AUTOOUTPUT*/
+ /*AUTOWIRE*/
+ /*AUTOREG*/
+ InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
+
+You can also update the AUTOs from the shell using:
+ emacs --batch <filenames.v> -f verilog-batch-auto
+Or fix indentation with:
+ emacs --batch <filenames.v> -f verilog-batch-indent
+Likewise, you can delete or inject AUTOs with:
+ emacs --batch <filenames.v> -f verilog-batch-delete-auto
+ emacs --batch <filenames.v> -f verilog-batch-inject-auto
+Or check if AUTOs have the same expansion
+ emacs --batch <filenames.v> -f verilog-batch-diff-auto
+
+Using \\[describe-function], see also:
+ `verilog-auto-arg' for AUTOARG module instantiations
+ `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
+ `verilog-auto-assign-modport' for AUTOASSIGNMODPORT assignment to/from modport
+ `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
+ `verilog-auto-inout-comp' for AUTOINOUTCOMP copy complemented i/o
+ `verilog-auto-inout-in' for AUTOINOUTIN inputs for all i/o
+ `verilog-auto-inout-modport' for AUTOINOUTMODPORT i/o from an interface modport
+ `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
+ `verilog-auto-inout-param' for AUTOINOUTPARAM copying params from elsewhere
+ `verilog-auto-input' for AUTOINPUT making hierarchy inputs
+ `verilog-auto-insert-lisp' for AUTOINSERTLISP insert code from lisp function
+ `verilog-auto-insert-last' for AUTOINSERTLAST insert code from lisp function
+ `verilog-auto-inst' for AUTOINST instantiation pins
+ `verilog-auto-star' for AUTOINST .* SystemVerilog pins
+ `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
+ `verilog-auto-logic' for AUTOLOGIC declaring logic signals
+ `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
+ `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
+ `verilog-auto-reg' for AUTOREG registers
+ `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
+ `verilog-auto-reset' for AUTORESET flop resets
+ `verilog-auto-sense' for AUTOSENSE or AS always sensitivity lists
+ `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
+ `verilog-auto-undef' for AUTOUNDEF \\=`undef of local \\=`defines
+ `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
+ `verilog-auto-wire' for AUTOWIRE instantiation wires
+
+ `verilog-read-defines' for reading \\=`define values
+ `verilog-read-includes' for reading \\=`includes
+
+If you have bugs with these autos, please file an issue at
+URL `http://www.veripool.org/verilog-mode' or contact the AUTOAUTHOR
+Wilson Snyder (wsnyder@wsnyder.org)."
+ (interactive)
+ (unless noninteractive (message "Updating AUTOs..."))
+ (if (fboundp 'dinotrace-unannotate-all)
+ (dinotrace-unannotate-all))
+ ;; Disable change hooks for speed
+ ;; This let can't be part of above let; must restore
+ ;; after-change-functions before font-lock resumes
+ (verilog-save-font-no-change-functions
+ (let ((oldbuf (if (not (buffer-modified-p))
+ (buffer-string)))
+ (case-fold-search verilog-case-fold)
+ ;; Cache directories; we don't write new files, so can't change
+ (verilog-dir-cache-preserving t)
+ ;; Cache current module
+ (verilog-modi-cache-current-enable t)
+ (verilog-modi-cache-current-max (point-min)) ; IE it's invalid
+ verilog-modi-cache-current)
+ (verilog-save-scan-cache
+ (save-excursion
+ ;; Wipe cache; otherwise if we AUTOed a block above this one,
+ ;; we'll misremember we have generated IOs, confusing AUTOOUTPUT
+ (setq verilog-modi-cache-list nil)
+ ;; Local state
+ (verilog-read-auto-template-init)
+ ;; If we're not in verilog-mode, change syntax table so parsing works right
+ (unless (eq major-mode `verilog-mode) (verilog-mode))
+ ;; Allow user to customize
+ (verilog-run-hooks 'verilog-before-auto-hook)
+ ;; Try to save the user from needing to revert-file to reread file local-variables
+ (verilog-auto-reeval-locals)
+ (verilog-read-auto-lisp-present)
+ (verilog-read-auto-lisp (point-min) (point-max))
+ (verilog-getopt-flags)
+ ;; From here on out, we can cache anything we read from disk
+ (verilog-preserve-dir-cache
+ ;; These two may seem obvious to do always, but on large includes it can be way too slow
+ (when verilog-auto-read-includes
+ (verilog-read-includes)
+ (verilog-read-defines nil nil t))
+ ;; Setup variables due to SystemVerilog expansion
+ (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic-setup)
+ ;; This particular ordering is important
+ ;; INST: Lower modules correct, no internal dependencies, FIRST
+ (verilog-preserve-modi-cache
+ ;; Clear existing autos else we'll be screwed by existing ones
+ (verilog-delete-auto-buffer)
+ ;; Injection if appropriate
+ (when inject
+ (verilog-inject-inst)
+ (verilog-inject-sense)
+ (verilog-inject-arg))
+ ;;
+ ;; Do user inserts first, so their code can insert AUTOs
+ (verilog-auto-re-search-do "/\\*AUTOINSERTLISP(.*?)\\*/"
+ 'verilog-auto-insert-lisp)
+ ;; Expand instances before need the signals the instances input/output
+ (verilog-auto-re-search-do "/\\*AUTOINSTPARAM\\*/" 'verilog-auto-inst-param)
+ (verilog-auto-re-search-do "/\\*AUTOINST\\*/" 'verilog-auto-inst)
+ (verilog-auto-re-search-do "\\.\\*" 'verilog-auto-star)
+ ;; Doesn't matter when done, but combine it with a common changer
+ (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
+ (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
+ ;; Must be done before autoin/out as creates a reg
+ (verilog-auto-re-search-do "/\\*AUTOASCIIENUM(.*?)\\*/" 'verilog-auto-ascii-enum)
+ ;;
+ ;; first in/outs from other files
+ (verilog-auto-re-search-do "/\\*AUTOINOUTMODPORT(.*?)\\*/" 'verilog-auto-inout-modport)
+ (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE(.*?)\\*/" 'verilog-auto-inout-module)
+ (verilog-auto-re-search-do "/\\*AUTOINOUTCOMP(.*?)\\*/" 'verilog-auto-inout-comp)
+ (verilog-auto-re-search-do "/\\*AUTOINOUTIN(.*?)\\*/" 'verilog-auto-inout-in)
+ (verilog-auto-re-search-do "/\\*AUTOINOUTPARAM(.*?)\\*/" 'verilog-auto-inout-param)
+ ;; next in/outs which need previous sucked inputs first
+ (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((.*?)\\)?\\*/" 'verilog-auto-output)
+ (verilog-auto-re-search-do "/\\*AUTOINPUT\\((.*?)\\)?\\*/" 'verilog-auto-input)
+ (verilog-auto-re-search-do "/\\*AUTOINOUT\\((.*?)\\)?\\*/" 'verilog-auto-inout)
+ ;; Then tie off those in/outs
+ (verilog-auto-re-search-do "/\\*AUTOTIEOFF\\*/" 'verilog-auto-tieoff)
+ ;; These can be anywhere after AUTOINSERTLISP
+ (verilog-auto-re-search-do "/\\*AUTOUNDEF\\((.*?)\\)?\\*/" 'verilog-auto-undef)
+ ;; Wires/regs must be after inputs/outputs
+ (verilog-auto-re-search-do "/\\*AUTOASSIGNMODPORT(.*?)\\*/" 'verilog-auto-assign-modport)
+ (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic)
+ (verilog-auto-re-search-do "/\\*AUTOWIRE\\*/" 'verilog-auto-wire)
+ (verilog-auto-re-search-do "/\\*AUTOREG\\*/" 'verilog-auto-reg)
+ (verilog-auto-re-search-do "/\\*AUTOREGINPUT\\*/" 'verilog-auto-reg-input)
+ ;; outputevery needs AUTOOUTPUTs done first
+ (verilog-auto-re-search-do "/\\*AUTOOUTPUTEVERY\\((.*?)\\)?\\*/" 'verilog-auto-output-every)
+ ;; After we've created all new variables
+ (verilog-auto-re-search-do "/\\*AUTOUNUSED\\*/" 'verilog-auto-unused)
+ ;; Must be after all inputs outputs are generated
+ (verilog-auto-re-search-do "/\\*AUTOARG\\*/" 'verilog-auto-arg)
+ ;; User inserts
+ (verilog-auto-re-search-do "/\\*AUTOINSERTLAST(.*?)\\*/" 'verilog-auto-insert-last)
+ ;; Fix line numbers (comments only)
+ (when verilog-auto-inst-template-numbers
+ (verilog-auto-templated-rel))
+ (when verilog-auto-template-warn-unused
+ (verilog-auto-template-lint))))
+ ;;
+ (verilog-run-hooks 'verilog-auto-hook)
+ ;;
+ (when verilog-auto-delete-trailing-whitespace
+ (verilog-delete-trailing-whitespace))
+ ;;
+ (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))
+ ;;
+ ;; If end result is same as when started, clear modified flag
+ (cond ((and oldbuf (equal oldbuf (buffer-string)))
+ (verilog-restore-buffer-modified-p nil)
+ (unless noninteractive (message "Updating AUTOs...done (no changes)")))
+ (t (unless noninteractive (message "Updating AUTOs...done"))))
+ ;; End of save-cache
+ )))))
+
+;;; Skeletons:
+;;
+
+(defvar verilog-template-map
+ (let ((map (make-sparse-keymap)))
+ (define-key map "a" 'verilog-sk-always)
+ (define-key map "b" 'verilog-sk-begin)
+ (define-key map "c" 'verilog-sk-case)
+ (define-key map "f" 'verilog-sk-for)
+ (define-key map "g" 'verilog-sk-generate)
+ (define-key map "h" 'verilog-sk-header)
+ (define-key map "i" 'verilog-sk-initial)
+ (define-key map "j" 'verilog-sk-fork)
+ (define-key map "m" 'verilog-sk-module)
+ (define-key map "o" 'verilog-sk-ovm-class)
+ (define-key map "p" 'verilog-sk-primitive)
+ (define-key map "r" 'verilog-sk-repeat)
+ (define-key map "s" 'verilog-sk-specify)
+ (define-key map "t" 'verilog-sk-task)
+ (define-key map "u" 'verilog-sk-uvm-object)
+ (define-key map "w" 'verilog-sk-while)
+ (define-key map "x" 'verilog-sk-casex)
+ (define-key map "z" 'verilog-sk-casez)
+ (define-key map "?" 'verilog-sk-if)
+ (define-key map ":" 'verilog-sk-else-if)
+ (define-key map "/" 'verilog-sk-comment)
+ (define-key map "A" 'verilog-sk-assign)
+ (define-key map "F" 'verilog-sk-function)
+ (define-key map "I" 'verilog-sk-input)
+ (define-key map "O" 'verilog-sk-output)
+ (define-key map "S" 'verilog-sk-state-machine)
+ (define-key map "=" 'verilog-sk-inout)
+ (define-key map "U" 'verilog-sk-uvm-component)
+ (define-key map "W" 'verilog-sk-wire)
+ (define-key map "R" 'verilog-sk-reg)
+ (define-key map "D" 'verilog-sk-define-signal)
+ map)
+ "Keymap used in Verilog mode for smart template operations.")
+
+
+;;
+;; Place the templates into Verilog Mode. They may be inserted under any key.
+;; C-c C-t will be the default. If you use templates a lot, you
+;; may want to consider moving the binding to another key in your init
+;; file.
+;;
+;; Note \C-c and letter are reserved for users
+(define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
+
+;; ---- statement skeletons ------------------------------------------
+
+(define-skeleton verilog-sk-prompt-condition
+ "Prompt for the loop condition."
+ "[condition]: " str )
+
+(define-skeleton verilog-sk-prompt-init
+ "Prompt for the loop init statement."
+ "[initial statement]: " str )
+
+(define-skeleton verilog-sk-prompt-inc
+ "Prompt for the loop increment statement."
+ "[increment statement]: " str )
+
+(define-skeleton verilog-sk-prompt-name
+ "Prompt for the name of something."
+ "[name]: " str)
+
+(define-skeleton verilog-sk-prompt-clock
+ "Prompt for the name of something."
+ "name and edge of clock(s): " str)
+
+(defvar verilog-sk-reset nil)
+(defun verilog-sk-prompt-reset ()
+ "Prompt for the name of a state machine reset."
+ (setq verilog-sk-reset (read-string "name of reset: " "rst")))
+
+
+(define-skeleton verilog-sk-prompt-state-selector
+ "Prompt for the name of a state machine selector."
+ "name of selector (eg {a,b,c,d}): " str )
+
+(define-skeleton verilog-sk-prompt-output
+ "Prompt for the name of something."
+ "output: " str)
+
+(define-skeleton verilog-sk-prompt-msb
+ "Prompt for most significant bit specification."
+ "msb:" str & ?: & '(verilog-sk-prompt-lsb) | -1 )
+
+(define-skeleton verilog-sk-prompt-lsb
+ "Prompt for least significant bit specification."
+ "lsb:" str )
+
+(defvar verilog-sk-p nil)
+(define-skeleton verilog-sk-prompt-width
+ "Prompt for a width specification."
+ ()
+ (progn
+ (setq verilog-sk-p (point))
+ (verilog-sk-prompt-msb)
+ (if (> (point) verilog-sk-p) "] " " ")))
+
+(defun verilog-sk-header ()
+ "Insert a descriptive header at the top of the file.
+See also `verilog-header' for an alternative format."
+ (interactive "*")
+ (save-excursion
+ (goto-char (point-min))
+ (verilog-sk-header-tmpl)))
+
+(define-skeleton verilog-sk-header-tmpl
+ "Insert a comment block containing the module title, author, etc."
+ "[Description]: "
+ "// -*- Mode: Verilog -*-"
+ "\n// Filename : " (buffer-name)
+ "\n// Description : " str
+ "\n// Author : " (user-full-name)
+ "\n// Created On : " (current-time-string)
+ "\n// Last Modified By: " (user-full-name)
+ "\n// Last Modified On: " (current-time-string)
+ "\n// Update Count : 0"
+ "\n// Status : Unknown, Use with caution!"
+ "\n")
+
+(define-skeleton verilog-sk-module
+ "Insert a module definition."
+ ()
+ > "module " '(verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
+ > _ \n
+ > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
+
+;; ------------------------------------------------------------------------
+;; Define a default OVM class, with macros and new()
+;; ------------------------------------------------------------------------
+
+(define-skeleton verilog-sk-ovm-class
+ "Insert a class definition"
+ ()
+ > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
+ > _ \n
+ > "`ovm_object_utils_begin(" name ")" \n
+ > (- verilog-indent-level) " `ovm_object_utils_end" \n
+ > _ \n
+ > "function new(string name=\"" name "\");" \n
+ > "super.new(name);" \n
+ > (- verilog-indent-level) "endfunction" \n
+ > _ \n
+ > "endclass" (progn (electric-verilog-terminate-line) nil))
+
+(define-skeleton verilog-sk-uvm-object
+ "Insert a class definition"
+ ()
+ > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
+ > _ \n
+ > "`uvm_object_utils_begin(" name ")" \n
+ > (- verilog-indent-level) "`uvm_object_utils_end" \n
+ > _ \n
+ > "function new(string name=\"" name "\");" \n
+ > "super.new(name);" \n
+ > (- verilog-indent-level) "endfunction" \n
+ > _ \n
+ > "endclass" (progn (electric-verilog-terminate-line) nil))
+
+(define-skeleton verilog-sk-uvm-component
+ "Insert a class definition"
+ ()
+ > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
+ > _ \n
+ > "`uvm_component_utils_begin(" name ")" \n
+ > (- verilog-indent-level) "`uvm_component_utils_end" \n
+ > _ \n
+ > "function new(string name=\"\", uvm_component parent);" \n
+ > "super.new(name, parent);" \n
+ > (- verilog-indent-level) "endfunction" \n
+ > _ \n
+ > "endclass" (progn (electric-verilog-terminate-line) nil))
+
+(define-skeleton verilog-sk-primitive
+ "Insert a task definition."
+ ()
+ > "primitive " '(verilog-sk-prompt-name) " ( " '(verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
+ > _ \n
+ > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
+
+(define-skeleton verilog-sk-task
+ "Insert a task definition."
+ ()
+ > "task " '(verilog-sk-prompt-name) & ?; \n
+ > _ \n
+ > "begin" \n
+ > \n
+ > (- verilog-indent-level-behavioral) "end" \n
+ > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
+
+(define-skeleton verilog-sk-function
+ "Insert a function definition."
+ ()
+ > "function [" '(verilog-sk-prompt-width) | -1 '(verilog-sk-prompt-name) ?; \n
+ > _ \n
+ > "begin" \n
+ > \n
+ > (- verilog-indent-level-behavioral) "end" \n
+ > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
+
+(define-skeleton verilog-sk-always
+ "Insert always block. Uses the minibuffer to prompt
+for sensitivity list."
+ ()
+ > "always @ ( /*AUTOSENSE*/ ) begin\n"
+ > _ \n
+ > (- verilog-indent-level-behavioral) "end" \n >
+ )
+
+(define-skeleton verilog-sk-initial
+ "Insert an initial block."
+ ()
+ > "initial begin\n"
+ > _ \n
+ > (- verilog-indent-level-behavioral) "end" \n > )
+
+(define-skeleton verilog-sk-specify
+ "Insert specify block. "
+ ()
+ > "specify\n"
+ > _ \n
+ > (- verilog-indent-level-behavioral) "endspecify" \n > )
+
+(define-skeleton verilog-sk-generate
+ "Insert generate block. "
+ ()
+ > "generate\n"
+ > _ \n
+ > (- verilog-indent-level-behavioral) "endgenerate" \n > )
+
+(define-skeleton verilog-sk-begin
+ "Insert begin end block. Uses the minibuffer to prompt for name."
+ ()
+ > "begin" '(verilog-sk-prompt-name) \n
+ > _ \n
+ > (- verilog-indent-level-behavioral) "end" )
+
+(define-skeleton verilog-sk-fork
+ "Insert a fork join block."
+ ()
+ > "fork\n"
+ > "begin" \n
+ > _ \n
+ > (- verilog-indent-level-behavioral) "end" \n
+ > "begin" \n
+ > \n
+ > (- verilog-indent-level-behavioral) "end" \n
+ > (- verilog-indent-level-behavioral) "join" \n
+ > )
+
+
+(define-skeleton verilog-sk-case
+ "Build skeleton case statement, prompting for the selector expression,
+and the case items."
+ "[selector expression]: "
+ > "case (" str ") " \n
+ > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
+ resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
+
+(define-skeleton verilog-sk-casex
+ "Build skeleton casex statement, prompting for the selector expression,
+and the case items."
+ "[selector expression]: "
+ > "casex (" str ") " \n
+ > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
+ resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
+
+(define-skeleton verilog-sk-casez
+ "Build skeleton casez statement, prompting for the selector expression,
+and the case items."
+ "[selector expression]: "
+ > "casez (" str ") " \n
+ > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
+ resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
+
+(define-skeleton verilog-sk-if
+ "Insert a skeleton if statement."
+ > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n
+ > _ \n
+ > (- verilog-indent-level-behavioral) "end " \n )
+
+(define-skeleton verilog-sk-else-if
+ "Insert a skeleton else if statement."
+ > (verilog-indent-line) "else if ("
+ (progn (setq verilog-sk-p (point)) nil) '(verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
+ > _ \n
+ > "end" (progn (electric-verilog-terminate-line) nil))
+
+(define-skeleton verilog-sk-datadef
+ "Common routine to get data definition."
+ ()
+ '(verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
+
+(define-skeleton verilog-sk-input
+ "Insert an input definition."
+ ()
+ > "input [" '(verilog-sk-datadef))
+
+(define-skeleton verilog-sk-output
+ "Insert an output definition."
+ ()
+ > "output [" '(verilog-sk-datadef))
+
+(define-skeleton verilog-sk-inout
+ "Insert an inout definition."
+ ()
+ > "inout [" '(verilog-sk-datadef))
+
+(defvar verilog-sk-signal nil)
+(define-skeleton verilog-sk-def-reg
+ "Insert a reg definition."
+ ()
+ > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations-auto) )
+
+(defun verilog-sk-define-signal ()
+ "Insert a definition of signal under point at top of module."
+ (interactive "*")
+ (let* ((sig-re "[a-zA-Z0-9_]*")
+ (v1 (buffer-substring
+ (save-excursion
+ (skip-chars-backward sig-re)
+ (point))
+ (save-excursion
+ (skip-chars-forward sig-re)
+ (point)))))
+ (if (not (member v1 verilog-keywords))
+ (save-excursion
+ (setq verilog-sk-signal v1)
+ (verilog-beg-of-defun)
+ (verilog-end-of-statement)
+ (verilog-forward-syntactic-ws)
+ (verilog-sk-def-reg)
+ (message "signal at point is %s" v1))
+ (message "object at point (%s) is a keyword" v1))))
+
+(define-skeleton verilog-sk-wire
+ "Insert a wire definition."
+ ()
+ > "wire [" '(verilog-sk-datadef))
+
+(define-skeleton verilog-sk-reg
+ "Insert a reg definition."
+ ()
+ > "reg [" '(verilog-sk-datadef))
+
+(define-skeleton verilog-sk-assign
+ "Insert a skeleton assign statement."
+ ()
+ > "assign " '(verilog-sk-prompt-name) " = " _ ";" \n)
+
+(define-skeleton verilog-sk-while
+ "Insert a skeleton while loop statement."
+ ()
+ > "while (" '(verilog-sk-prompt-condition) ") begin" \n
+ > _ \n
+ > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
+
+(define-skeleton verilog-sk-repeat
+ "Insert a skeleton repeat loop statement."
+ ()
+ > "repeat (" '(verilog-sk-prompt-condition) ") begin" \n
+ > _ \n
+ > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
+
+(define-skeleton verilog-sk-for
+ "Insert a skeleton while loop statement."
+ ()
+ > "for ("
+ '(verilog-sk-prompt-init) "; "
+ '(verilog-sk-prompt-condition) "; "
+ '(verilog-sk-prompt-inc)
+ ") begin" \n
+ > _ \n
+ > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
+
+(define-skeleton verilog-sk-comment
+ "Inserts three comment lines, making a display comment."
+ ()
+ > "/*\n"
+ > "* " _ \n
+ > "*/")
+
+(define-skeleton verilog-sk-state-machine
+ "Insert a state machine definition."
+ "Name of state variable: "
+ '(setq input "state")
+ > "// State registers for " str | -23 \n
+ '(setq verilog-sk-state str)
+ > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
+ '(setq input nil)
+ > \n
+ > "// State FF for " verilog-sk-state \n
+ > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
+ > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
+ > verilog-sk-state " = next_" verilog-sk-state ?; \n
+ > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
+ > \n
+ > "// Next State Logic for " verilog-sk-state \n
+ > "always @ ( /*AUTOSENSE*/ ) begin\n"
+ > "case (" '(verilog-sk-prompt-state-selector) ") " \n
+ > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
+ resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
+ > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
+
+;;; Mouse Events:
+;;
+;; Include file loading with mouse/return event
+;;
+;; idea & first impl.: M. Rouat (eldo-mode.el)
+;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
+
+(if (featurep 'xemacs)
+ (require 'overlay))
+
+(defconst verilog-include-file-regexp
+ "^`include\\s-+\"\\([^\n\"]*\\)\""
+ "Regexp that matches the include file.")
+
+(defvar verilog-mode-mouse-map
+ (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
+ (set-keymap-parent map verilog-mode-map)
+ ;; mouse button bindings
+ (define-key map "\r" 'verilog-load-file-at-point)
+ (if (featurep 'xemacs)
+ (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
+ (define-key map [mouse-2] 'verilog-load-file-at-mouse))
+ (if (featurep 'xemacs)
+ (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
+ (define-key map [S-mouse-2] 'mouse-yank-at-click))
+ map)
+ "Map containing mouse bindings for `verilog-mode'.")
+
+
+(defun verilog-highlight-region (beg end _old-len)
+ "Colorize included files and modules in the (changed?) region.
+Clicking on the middle-mouse button loads them in a buffer (as in dired)."
+ (when (or verilog-highlight-includes
+ verilog-highlight-modules)
+ (save-excursion
+ (save-match-data ; A query-replace may call this function - do not disturb
+ (verilog-save-buffer-state
+ (verilog-save-scan-cache
+ (let (end-point)
+ (goto-char end)
+ (setq end-point (point-at-eol))
+ (goto-char beg)
+ (beginning-of-line) ; scan entire line
+ ;; delete overlays existing on this line
+ (let ((overlays (overlays-in (point) end-point)))
+ (while overlays
+ (if (and
+ (overlay-get (car overlays) 'detachable)
+ (or (overlay-get (car overlays) 'verilog-include-file)
+ (overlay-get (car overlays) 'verilog-inst-module)))
+ (delete-overlay (car overlays)))
+ (setq overlays (cdr overlays))))
+ ;;
+ ;; make new include overlays
+ (when verilog-highlight-includes
+ (while (search-forward-regexp verilog-include-file-regexp end-point t)
+ (goto-char (match-beginning 1))
+ (let ((ov (make-overlay (match-beginning 1) (match-end 1))))
+ (overlay-put ov 'start-closed 't)
+ (overlay-put ov 'end-closed 't)
+ (overlay-put ov 'evaporate 't)
+ (overlay-put ov 'verilog-include-file 't)
+ (overlay-put ov 'mouse-face 'highlight)
+ (overlay-put ov 'local-map verilog-mode-mouse-map))))
+ ;;
+ ;; make new module overlays
+ (goto-char beg)
+ ;; This scanner is syntax-fragile, so don't get bent
+ (when verilog-highlight-modules
+ (condition-case nil
+ (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-point t)
+ (save-excursion
+ (goto-char (match-beginning 0))
+ (unless (verilog-inside-comment-or-string-p)
+ (verilog-read-inst-module-matcher) ; sets match 0
+ (let* ((ov (make-overlay (match-beginning 0) (match-end 0))))
+ (overlay-put ov 'start-closed 't)
+ (overlay-put ov 'end-closed 't)
+ (overlay-put ov 'evaporate 't)
+ (overlay-put ov 'verilog-inst-module 't)
+ (overlay-put ov 'mouse-face 'highlight)
+ (overlay-put ov 'local-map verilog-mode-mouse-map)))))
+ (error nil)))
+ ;;
+ ;; Future highlights:
+ ;; variables - make an Occur buffer of where referenced
+ ;; pins - make an Occur buffer of the sig in the declaration module
+ )))))))
+
+(defun verilog-highlight-buffer ()
+ "Colorize included files and modules across the whole buffer."
+ ;; Invoked via verilog-mode calling font-lock then `font-lock-mode-hook'
+ (interactive)
+ ;; delete and remake overlays
+ (verilog-highlight-region (point-min) (point-max) nil))
+
+;; Deprecated, but was interactive, so we'll keep it around
+(defalias 'verilog-colorize-include-files-buffer 'verilog-highlight-buffer)
+
+;; ffap-at-mouse isn't useful for Verilog mode. It uses library paths.
+;; so define this function to do more or less the same as ffap-at-mouse
+;; but first resolve filename...
+(defun verilog-load-file-at-mouse (event)
+ "Load file under button 2 click's EVENT.
+Files are checked based on `verilog-library-flags'."
+ (interactive "@e")
+ (save-excursion ; implement a Verilog specific ffap-at-mouse
+ (mouse-set-point event)
+ (verilog-load-file-at-point t)))
+
+;; ffap isn't usable for Verilog mode. It uses library paths.
+;; so define this function to do more or less the same as ffap
+;; but first resolve filename...
+(defun verilog-load-file-at-point (&optional warn)
+ "Load file under point.
+If WARN, throw warning if not found.
+Files are checked based on `verilog-library-flags'."
+ (interactive)
+ (save-excursion ; implement a Verilog specific ffap
+ (let ((overlays (overlays-in (point) (point)))
+ hit)
+ (while (and overlays (not hit))
+ (when (overlay-get (car overlays) 'verilog-inst-module)
+ (verilog-goto-defun-file (buffer-substring
+ (overlay-start (car overlays))
+ (overlay-end (car overlays))))
+ (setq hit t))
+ (setq overlays (cdr overlays)))
+ ;; Include?
+ (beginning-of-line)
+ (when (and (not hit)
+ (looking-at verilog-include-file-regexp))
+ (if (and (car (verilog-library-filenames
+ (match-string 1) (buffer-file-name)))
+ (file-readable-p (car (verilog-library-filenames
+ (match-string 1) (buffer-file-name)))))
+ (find-file (car (verilog-library-filenames
+ (match-string 1) (buffer-file-name))))
+ (when warn
+ (message
+ "File `%s' isn't readable, use shift-mouse2 to paste in this field"
+ (match-string 1))))))))
+
+
+;;; Bug reporting:
+;;
+
+(defun verilog-faq ()
+ "Tell the user their current version, and where to get the FAQ etc."
+ (interactive)
+ (with-output-to-temp-buffer "*verilog-mode help*"
+ (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
+ (princ "\n")
+ (princ "For new releases, see http://www.verilog.com\n")
+ (princ "\n")
+ (princ "For frequently asked questions, see http://www.veripool.org/verilog-mode-faq.html\n")
+ (princ "\n")
+ (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
+ (princ "\n")))
+
+(autoload 'reporter-submit-bug-report "reporter")
+(defvar reporter-prompt-for-summary-p)
+
+(defun verilog-submit-bug-report ()
+ "Submit via mail a bug report on verilog-mode.el."
+ (interactive)
+ (let ((reporter-prompt-for-summary-p t))
+ (reporter-submit-bug-report
+ "mac@verilog.com, wsnyder@wsnyder.org"
+ (concat "verilog-mode v" verilog-mode-version)
+ '(
+ verilog-active-low-regexp
+ verilog-after-save-font-hook
+ verilog-align-ifelse
+ verilog-assignment-delay
+ verilog-auto-arg-sort
+ verilog-auto-declare-nettype
+ verilog-auto-delete-trailing-whitespace
+ verilog-auto-endcomments
+ verilog-auto-hook
+ verilog-auto-ignore-concat
+ verilog-auto-indent-on-newline
+ verilog-auto-inout-ignore-regexp
+ verilog-auto-input-ignore-regexp
+ verilog-auto-inst-column
+ verilog-auto-inst-dot-name
+ verilog-auto-inst-interfaced-ports
+ verilog-auto-inst-param-value
+ verilog-auto-inst-sort
+ verilog-auto-inst-template-numbers
+ verilog-auto-inst-vector
+ verilog-auto-lineup
+ verilog-auto-newline
+ verilog-auto-output-ignore-regexp
+ verilog-auto-read-includes
+ verilog-auto-reset-blocking-in-non
+ verilog-auto-reset-widths
+ verilog-auto-save-policy
+ verilog-auto-sense-defines-constant
+ verilog-auto-sense-include-inputs
+ verilog-auto-star-expand
+ verilog-auto-star-save
+ verilog-auto-template-warn-unused
+ verilog-auto-tieoff-declaration
+ verilog-auto-tieoff-ignore-regexp
+ verilog-auto-unused-ignore-regexp
+ verilog-auto-wire-type
+ verilog-before-auto-hook
+ verilog-before-delete-auto-hook
+ verilog-before-getopt-flags-hook
+ verilog-before-save-font-hook
+ verilog-cache-enabled
+ verilog-case-fold
+ verilog-case-indent
+ verilog-cexp-indent
+ verilog-compiler
+ verilog-coverage
+ verilog-delete-auto-hook
+ verilog-getopt-flags-hook
+ verilog-highlight-grouping-keywords
+ verilog-highlight-includes
+ verilog-highlight-modules
+ verilog-highlight-p1800-keywords
+ verilog-highlight-translate-off
+ verilog-indent-begin-after-if
+ verilog-indent-declaration-macros
+ verilog-indent-level
+ verilog-indent-level-behavioral
+ verilog-indent-level-declaration
+ verilog-indent-level-directive
+ verilog-indent-level-module
+ verilog-indent-lists
+ verilog-library-directories
+ verilog-library-extensions
+ verilog-library-files
+ verilog-library-flags
+ verilog-linter
+ verilog-minimum-comment-distance
+ verilog-mode-hook
+ verilog-mode-release-emacs
+ verilog-mode-version
+ verilog-preprocessor
+ verilog-simulator
+ verilog-tab-always-indent
+ verilog-tab-to-comment
+ verilog-typedef-regexp
+ verilog-warn-fatal
+ )
+ nil nil
+ (concat "Hi Mac,
+
+I want to report a bug.
+
+Before I go further, I want to say that Verilog mode has changed my life.
+I save so much time, my files are colored nicely, my co workers respect
+my coding ability... until now. I'd really appreciate anything you
+could do to help me out with this minor deficiency in the product.
+
+I've taken a look at the Verilog-Mode FAQ at
+http://www.veripool.org/verilog-mode-faq.html.
+
+And, I've considered filing the bug on the issue tracker at
+http://www.veripool.org/verilog-mode-bugs
+since I realize that public bugs are easier for you to track,
+and for others to search, but would prefer to email.
+
+So, to reproduce the bug, start a fresh Emacs via " invocation-name "
+-no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
+the code included below.
+
+Given those lines, I expected [[Fill in here]] to happen;
+but instead, [[Fill in here]] happens!.
+
+== The code: =="))))
+
+(provide 'verilog-mode)
+
+;; Local Variables:
+;; checkdoc-permit-comma-termination-flag:t
+;; checkdoc-force-docstrings-flag:nil
+;; indent-tabs-mode:nil
+;; End:
+
+;;; verilog-mode.el ends here
diff --git a/verilog.texinfo b/verilog.texinfo
new file mode 100644
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+++ b/verilog.texinfo
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+\input texinfo
+@setfilename verilog.info
+@c $Id$
+
+@ifinfo
+@format
+INFO-DIR-SECTION Emacs
+START-INFO-DIR-ENTRY
+* Verilog-mode: (verilog). The Verilog Mode user guide.
+END-INFO-DIR-ENTRY
+@end format
+@end ifinfo
+
+@ifinfo
+This file documents the Verilog-HDL and SystemVerilog editing mode for
+XEmacs and FSF Emacs, called the verilog-mode.
+
+Copyright (C) 2016 Free Software Foundation, Inc.
+Contributed and written by Michael McNamara and Wilson Snyder.
+
+Permission is granted to make and distribute verbatim copies of this
+manual provided the copyright notice and this permission notice are
+preserved on all copies.
+
+@ignore
+Permission is granted to process this file through Tex and print the
+results, provided the printed document carries copying permission notice
+identical to this one except for the removal of this paragraph (this
+paragraph not being relevant to the printed manual).
+
+@end ignore
+Permission is granted to copy or distribute modified versions of this
+manual under the terms of the GPL (for which purpose this text may be
+regarded as a program in the language TeX).
+@end ifinfo
+
+@setchapternewpage off
+@settitle Verilog Mode
+@titlepage
+@title The Verilog Mode
+@subtitle A guide to using the Verilog Mode
+@author Michael McNamara
+@page
+
+@vskip 0pt plus 1filll
+Copyright @copyright{} 2016 Free Software Foundation, Inc.
+
+Permission is granted to make and distribute verbatim copies of
+this manual provided the copyright notice and this permission notice
+are preserved on all copies.
+
+@end titlepage
+
+@node Top
+@c Perhaps this should be the title of the document (but only for info,
+@c not for TeX). Existing GNU manuals seem inconsistent on this point.
+@top Scope of this Document
+
+This document documents the use and customization of the Verilog-mode
+for Emacs.
+@menu
+* New Versions:: Getting new versions
+* Installing:: How to install the Verilog Mode
+* Getting Started:: Getting started using the Verilog-mode
+* Colors:: Enabling and customizing the colors
+* FAQ:: Frequently Asked Questions
+@end menu
+
+@node New Versions
+@chapter Getting New Versions
+
+Check the web at @file{http://www.veripool.org/verilog-mode} to see if
+there are newer versions of this mode.
+
+@node Installing
+@chapter Installing the Verilog-Mode
+
+See http://www.veripool.org/projects/verilog-mode/wiki/Installing
+and the instructions at the top of verilog-mode.el.
+
+@node Getting Started
+@chapter Getting Started Using the Verilog-Mode
+
+See http://www.veripool.org/projects/verilog-mode/wiki/Documentation
+including the papers and presentations therein.
+
+If you visit any Verilog or SystemVerilog file (.v, .vh, .sv, .svh
+file extension), in the menu bar there will be a Verilog
+item. Underneath this you will find a help item with various subitems.
+
+@node Colors
+@chapter Configuring and Using the syntax coloring features
+
+Coloring your code is really cool, impresses your friends, and actually
+does help one code quicker, and helps one understand others code. The
+only problem is that each version of emacs has different ways of
+specifying what color should be used, and hence it is a bear.
+
+Select the menu bar @code{Verilog->Customize Verilog Fonts and Colors}
+and a nice interface pops up where you can select the font-lock-* faces
+to colors that you find pleasing. You can choose the font face, whether
+it is bold, italic, and/or underlined; or
+all three.
+
+@node FAQ
+@chapter Frequently asked questions
+
+See http://www.veripool.org/projects/verilog-mode/wiki/FAQ
+
+@contents
+@bye