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Spice circuit integrator
.subckt wramp bias out in.p in.m
M1 net.1 net.1 GND GND nmos
M2 out net.1 GND GND nmos
M3 net.1 net.2 Vdd Vdd pmos
M4 out net.3 Vdd Vdd pmos
M5 net.3 net.3 Vdd Vdd pmos
M6 net.2 net.2 Vdd Vdd pmos
M7 net.4 bias GND GND nmos
M8 net.3 in.p net.4 GND nmos
M9 net.2 in.m net.4 GND nmos
.ends
C10 Output GND 1.0P
X1 Bias Output Input Output wramp
.end
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