diff options
author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-07-12 17:05:24 +0200 |
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committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-07-12 17:05:24 +0200 |
commit | 5f45a1bc47f75ccdaae3bc793b04b0b05cba7d39 (patch) | |
tree | 3865fd18f1fe435e3162dae513d17ad65301de8d | |
parent | 09963d6ddd745b07cac61c25d78d202e4d7043fd (diff) |
Some lintian fixes
-rw-r--r-- | debian/changelog | 2 | ||||
-rw-r--r-- | debian/patches/0008-Set-fixed-date-when-calling-pdflatex-for-presentatio.patch | 52 | ||||
-rw-r--r-- | debian/patches/0009-Some-spelling-errors-fixed.patch | 77 | ||||
-rw-r--r-- | debian/patches/series | 2 | ||||
-rwxr-xr-x | debian/rules | 9 |
5 files changed, 139 insertions, 3 deletions
diff --git a/debian/changelog b/debian/changelog index efd11d1b..359fb0e8 100644 --- a/debian/changelog +++ b/debian/changelog @@ -148,7 +148,7 @@ yosys (0.5.0+20151013gitf13e387-1) unstable; urgency=low yosys (0.5.0+20151007gitba4cce9-1) experimental; urgency=low - * New upstream version + * New upstream version - Refreshed patches * debian/control: Added "python3" as build-dependency diff --git a/debian/patches/0008-Set-fixed-date-when-calling-pdflatex-for-presentatio.patch b/debian/patches/0008-Set-fixed-date-when-calling-pdflatex-for-presentatio.patch new file mode 100644 index 00000000..231b837a --- /dev/null +++ b/debian/patches/0008-Set-fixed-date-when-calling-pdflatex-for-presentatio.patch @@ -0,0 +1,52 @@ +From: Ruben Undheim <ruben.undheim@gmail.com> +Date: Thu, 12 Jul 2018 10:41:21 +0000 +Subject: Set fixed date when calling pdflatex for presentation.tex. Remove ID + fields + +--- + Makefile | 2 +- + manual/presentation.sh | 5 ++++- + manual/presentation.tex | 1 + + 3 files changed, 6 insertions(+), 2 deletions(-) + +diff --git a/Makefile b/Makefile +index 8979641..53bab9b 100644 +--- a/Makefile ++++ b/Makefile +@@ -464,7 +464,7 @@ update-manual: $(TARGETS) $(EXTRA_TARGETS) + + manual: $(TARGETS) $(EXTRA_TARGETS) + cd manual && bash appnotes.sh +- cd manual && bash presentation.sh ++ cd manual && PDF_DATE=$(PDF_DATE) bash presentation.sh + cd manual && bash manual.sh + + clean: +diff --git a/manual/presentation.sh b/manual/presentation.sh +index ca8a6c9..a152484 100755 +--- a/manual/presentation.sh ++++ b/manual/presentation.sh +@@ -37,7 +37,10 @@ fi + + set -ex + +-pdflatex $PDFTEX_OPT presentation.tex ++echo ${PDF_DATE} ++pdflatex $PDFTEX_OPT '\pdfinfo{/CreationDate('${PDF_DATE}')/ModDate('${PDF_DATE}')}\input{presentation.tex}' ++grep -av '^/ID \[\(<[0-9A-F]\{32\}>\) \1]$$' presentation.pdf > presentation.pdf.without_pdf_id ++mv -f presentation.pdf.without_pdf_id presentation.pdf + + if ! $fast_mode; then + while +diff --git a/manual/presentation.tex b/manual/presentation.tex +index 8060998..a42648c 100644 +--- a/manual/presentation.tex ++++ b/manual/presentation.tex +@@ -81,6 +81,7 @@ + + \title{Yosys Open SYnthesis Suite} + \author{Clifford Wolf} ++\date{REPLACEWITHDATE} + \institute{http://www.clifford.at/yosys/} + + \usetheme{Madrid} diff --git a/debian/patches/0009-Some-spelling-errors-fixed.patch b/debian/patches/0009-Some-spelling-errors-fixed.patch new file mode 100644 index 00000000..d99a2f65 --- /dev/null +++ b/debian/patches/0009-Some-spelling-errors-fixed.patch @@ -0,0 +1,77 @@ +From: Ruben Undheim <ruben.undheim@gmail.com> +Date: Thu, 12 Jul 2018 13:41:39 +0200 +Subject: Some spelling errors fixed + +--- + backends/verilog/verilog_backend.cc | 2 +- + frontends/liberty/liberty.cc | 2 +- + manual/CHAPTER_Overview.tex | 2 +- + manual/command-reference-manual.tex | 2 +- + passes/cmds/show.cc | 2 +- + 5 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc +index a617215..6f03f25 100644 +--- a/backends/verilog/verilog_backend.cc ++++ b/backends/verilog/verilog_backend.cc +@@ -1253,7 +1253,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) + active_module = module; + + if (!module->processes.empty()) +- log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n" ++ log_warning("Module %s contains unmapped RTLIL processes. RTLIL processes\n" + "can't always be mapped directly to Verilog always blocks. Unintended\n" + "changes in simulation behavior are possible! Use \"proc\" to convert\n" + "processes to logic networks and registers.", log_id(module)); +diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc +index 4666c81..c130a57 100644 +--- a/frontends/liberty/liberty.cc ++++ b/frontends/liberty/liberty.cc +@@ -575,7 +575,7 @@ struct LibertyFrontend : public Frontend { + LibertyAst *bus_type_node = node->find("bus_type"); + + if (!bus_type_node || !type_map.count(bus_type_node->value)) +- log_error("Unkown or unsupported type for bus interface %s on cell %s.\n", ++ log_error("Unknown or unsupported type for bus interface %s on cell %s.\n", + node->args.at(0).c_str(), log_id(cell_name)); + + int bus_type_width = std::get<0>(type_map.at(bus_type_node->value)); +diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex +index 964875d..ae5cf09 100644 +--- a/manual/CHAPTER_Overview.tex ++++ b/manual/CHAPTER_Overview.tex +@@ -240,7 +240,7 @@ An RTLIL::Wire object has the following properties: + As with modules, the attributes can be Verilog attributes imported by the + Verilog frontend or attributes assigned by passes. + +-In Yosys, busses (signal vectors) are represented using a single wire object ++In Yosys, buses (signal vectors) are represented using a single wire object + with a width > 1. So Yosys does not convert signal vectors to individual signals. + This makes some aspects of RTLIL more complex but enables Yosys to be used for + coarse grain synthesis where the cells of the target architecture operate on +diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex +index 8af8ccd..3452ccb 100644 +--- a/manual/command-reference-manual.tex ++++ b/manual/command-reference-manual.tex +@@ -2859,7 +2859,7 @@ to a graphics file (usually SVG or PostScript). + assigned to each unique value of this attribute. + + -width +- annotate busses with a label indicating the width of the bus. ++ annotate buses with a label indicating the width of the bus. + + -signed + mark ports (A, B) that are declared as signed (using the [AB]_SIGNED +diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc +index 3a3939a..9170ad8 100644 +--- a/passes/cmds/show.cc ++++ b/passes/cmds/show.cc +@@ -618,7 +618,7 @@ struct ShowPass : public Pass { + log(" assigned to each unique value of this attribute.\n"); + log("\n"); + log(" -width\n"); +- log(" annotate busses with a label indicating the width of the bus.\n"); ++ log(" annotate buses with a label indicating the width of the bus.\n"); + log("\n"); + log(" -signed\n"); + log(" mark ports (A, B) that are declared as signed (using the [AB]_SIGNED\n"); diff --git a/debian/patches/series b/debian/patches/series index ea5639c7..4c0e09bb 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -5,3 +5,5 @@ switch-to-free-font.patch manual-build.patch kfreebsd-support.patch 0007-Disable-pretty-build.patch +0008-Set-fixed-date-when-calling-pdflatex-for-presentatio.patch +0009-Some-spelling-errors-fixed.patch diff --git a/debian/rules b/debian/rules index a41aee2f..0fe416b6 100755 --- a/debian/rules +++ b/debian/rules @@ -3,9 +3,13 @@ # Uncomment this to turn on verbose mode. #export DH_VERBOSE=1 +include /usr/share/dpkg/pkg-info.mk + export DEB_LDFLAGS_MAINT_APPEND = -Wl,--as-needed -CHANGELOG_DATE ?= $(shell LC_ALL=C date -u -d "`dpkg-parsechangelog --show-field Date`" +"%d %B %Y") +PDF_DATE := $(shell LC_ALL=C date -u -d @$(SOURCE_DATE_EPOCH) +D:%Y%m%d%H%M%SZ) +PDF_DATE2 := $(shell LC_ALL=C date -u -d @$(SOURCE_DATE_EPOCH) +"%B %d, %Y") +CHANGELOG_DATE ?= $(shell LC_ALL=C date -u -d @$(SOURCE_DATE_EPOCH) +"%d %B %Y") %: @@ -33,4 +37,5 @@ override_dh_auto_build-arch: dh_auto_build --parallel -- all override_dh_auto_build-indep: - dh_auto_build --parallel -- all manual + sed -i 's/REPLACEWITHDATE/$(PDF_DATE2)/' manual/presentation.tex + PDF_DATE=$(PDF_DATE) dh_auto_build --parallel -- all manual |