diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-02-14 10:23:03 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-14 10:23:03 +0100 |
| commit | 910556560fbf26df4f2960b7d94039a1f399f1a1 (patch) | |
| tree | 0275d15fa8aa833995f68784f205b2842a0ccb48 | |
| parent | ef151b0b30c7b7253aceba6d184e7721a4eff0c0 (diff) | |
Added $meminit cell type
| -rw-r--r-- | kernel/celltypes.h | 1 | ||||
| -rw-r--r-- | kernel/rtlil.cc | 9 | ||||
| -rw-r--r-- | passes/opt/opt_clean.cc | 2 | ||||
| -rw-r--r-- | techlibs/common/simlib.v | 22 |
4 files changed, 33 insertions, 1 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 60e6606f..57bcde47 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -135,6 +135,7 @@ struct CellTypes setup_type("$memrd", {CLK, ADDR}, {DATA}); setup_type("$memwr", {CLK, EN, ADDR, DATA}, pool<RTLIL::IdString>()); + setup_type("$meminit", {ADDR, DATA}, pool<RTLIL::IdString>()); setup_type("$mem", {RD_CLK, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA}); setup_type("$fsm", {CLK, ARST, CTRL_IN}, {CTRL_OUT}); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 776625b9..9fd3d295 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -904,6 +904,15 @@ namespace { return; } + if (cell->type == "$meminit") { + param("\\MEMID"); + param("\\PRIORITY"); + port("\\ADDR", param("\\ABITS")); + port("\\DATA", param("\\WIDTH")); + check_expected(); + return; + } + if (cell->type == "$mem") { param("\\MEMID"); param("\\SIZE"); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 6a7e6051..aea34175 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -47,7 +47,7 @@ void rmunused_module_cells(Module *module, bool verbose) if (bit.wire != nullptr) wire2driver[bit].insert(cell); } - if (cell->type == "$memwr" || cell->type == "$assert" || cell->has_keep_attr()) + if (cell->type.in("$memwr", "$meminit", "$assert") || cell->has_keep_attr()) queue.insert(cell); else unused.insert(cell); diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index a73c6ee0..6707e190 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1514,6 +1514,28 @@ endmodule // -------------------------------------------------------- +module \$meminit (ADDR, DATA); + +parameter MEMID = ""; +parameter ABITS = 8; +parameter WIDTH = 8; + +parameter PRIORITY = 0; + +input [ABITS-1:0] ADDR; +input [WIDTH-1:0] DATA; + +initial begin + if (MEMID != "") begin + $display("ERROR: Found non-simulatable instance of $meminit!"); + $finish; + end +end + +endmodule + +// -------------------------------------------------------- + module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); parameter MEMID = ""; |