diff options
authorRuben Undheim <>2018-10-17 18:13:44 +0200
committerRuben Undheim <>2018-10-17 18:13:44 +0200
commit0b254e3191dbed4a29ee37c5ae7cfcf8d723fbb2 (patch)
parent42daa78b5be0b7b54d2c6a870cbaa6112b7fe388 (diff)
Updated man page
1 files changed, 12 insertions, 1 deletions
diff --git a/debian/yosys.1 b/debian/yosys.1
index fbfb0aa0..84164d16 100644
--- a/debian/yosys.1
+++ b/debian/yosys.1
@@ -2,7 +2,7 @@
.\" First parameter, NAME, should be all caps
.\" Second parameter, SECTION, should be 1-8, maybe w/ subsection
.\" other parameters are allowed: see man(7), man(1)
-.TH YOSYS 1 "November 04, 2016"
+.TH YOSYS 1 "October 17, 2018"
.\" Please adjust this date whenever revising the manpage.
.\" Some roff macros, for reference:
@@ -99,9 +99,20 @@ dump the design when printing the specified log header to a file.
yosys_dump_<header_id>.il is used as filename if none is specified.
Use 'ALL' as <header_id> to dump at every header.
+.B \-W regex
+if a warning message matches the regex, it is printed as regular
+message instead.
+.B \-e regex
+if a warning message matches the regex, it is printed as error
+message instead and the tool terminates with a nonzero return code.
.B \-V
print version information and exit
+.B \-E depsfile
+write a Makefile dependencies file with in- and output file names
.B \-S
The option \-S is an alias for the "synth" command, a default
script for transforming the Verilog input to a gate-level netlist. For example: