summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2013-10-27 08:21:56 +0100
committerClifford Wolf <clifford@clifford.at>2013-10-27 08:21:56 +0100
commit02f321b6fcd17c94ad633d1070c03cbec1eb86e8 (patch)
treee745314afedc87fe1fdbff2d2fa9121228afb404
parentd9fa1e5a1d01e5a69dca6f8f0d760b047f29a772 (diff)
Xilinx mojo_counter example is now working
-rw-r--r--techlibs/xilinx/example_mojo_counter/example.sh6
-rw-r--r--techlibs/xilinx/example_mojo_counter/example.ucf1
-rw-r--r--techlibs/xilinx/example_mojo_counter/example.v6
3 files changed, 9 insertions, 4 deletions
diff --git a/techlibs/xilinx/example_mojo_counter/example.sh b/techlibs/xilinx/example_mojo_counter/example.sh
index 87af0ea3..466fadad 100644
--- a/techlibs/xilinx/example_mojo_counter/example.sh
+++ b/techlibs/xilinx/example_mojo_counter/example.sh
@@ -19,8 +19,12 @@ abc -lut 6; opt
# map internal cells to FPGA cells
techmap -map ../cells.v; opt
+# insert clock buffers
+select -set clocks */t:FDRE %x:+FDRE[C] */t:FDRE %d
+iopadmap -inpad BUFGP O:I @clocks
+
# insert i/o buffers
-iopadmap -outpad OBUF I:O -inpad BUFGP O:I
+iopadmap -outpad OBUF I:O -inpad IBUF O:I @clocks %n
# write netlist
write_edif synth.edif
diff --git a/techlibs/xilinx/example_mojo_counter/example.ucf b/techlibs/xilinx/example_mojo_counter/example.ucf
index 591cbe76..93d97b4d 100644
--- a/techlibs/xilinx/example_mojo_counter/example.ucf
+++ b/techlibs/xilinx/example_mojo_counter/example.ucf
@@ -2,6 +2,7 @@ NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
NET "clk" LOC = P56;
+NET "ctrl" LOC = P1;
NET "led_0" LOC = P134;
NET "led_1" LOC = P133;
diff --git a/techlibs/xilinx/example_mojo_counter/example.v b/techlibs/xilinx/example_mojo_counter/example.v
index 8e79942e..cb98cc1b 100644
--- a/techlibs/xilinx/example_mojo_counter/example.v
+++ b/techlibs/xilinx/example_mojo_counter/example.v
@@ -1,13 +1,13 @@
-module top(clk, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
+module top(clk, ctrl, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
-input clk;
+input clk, ctrl;
output led_7, led_6, led_5, led_4;
output led_3, led_2, led_1, led_0;
reg [31:0] counter;
always @(posedge clk)
- counter <= 32'b_1010_1010_1010_1010_1010_1010_1010_1010; // counter + 1;
+ counter <= counter + (ctrl ? 4 : 1);
assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24;