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authorClifford Wolf <clifford@clifford.at>2014-08-02 18:58:40 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-02 18:58:40 +0200
commit04727c7e0fb4c00b38999da192e4ada2a6f9474a (patch)
tree5cedd8807a1d846d5bd6790bfde555b70b8c283b
parent768eb846c4473040dc07bf62ce631c8a21474ae8 (diff)
No implicit conversion from IdString to anything else
-rw-r--r--backends/blif/blif.cc2
-rw-r--r--backends/btor/btor.cc2
-rw-r--r--backends/edif/edif.cc4
-rw-r--r--backends/spice/spice.cc2
-rw-r--r--kernel/log.cc2
-rw-r--r--kernel/register.cc4
-rw-r--r--kernel/rtlil.cc28
-rw-r--r--kernel/rtlil.h10
-rw-r--r--passes/abc/abc.cc2
-rw-r--r--passes/cmds/design.cc2
-rw-r--r--passes/cmds/select.cc4
-rw-r--r--passes/cmds/show.cc2
-rw-r--r--passes/fsm/fsm_export.cc2
-rw-r--r--passes/memory/memory_collect.cc2
-rw-r--r--passes/techmap/extract.cc4
-rw-r--r--passes/techmap/techmap.cc2
16 files changed, 37 insertions, 37 deletions
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index ecde8b5a..5daab669 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -363,7 +363,7 @@ struct BlifBackend : public Backend {
if (top_module_name.empty())
for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
- top_module_name = mod_it.first;
+ top_module_name = mod_it.first.str();
fprintf(f, "# Generated by %s\n", yosys_version_str);
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 201be0cf..a81d8f15 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -968,7 +968,7 @@ struct BtorBackend : public Backend {
if (top_module_name.empty())
for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
- top_module_name = mod_it.first;
+ top_module_name = mod_it.first.str();
fprintf(f, "; Generated by %s\n", yosys_version_str);
fprintf(f, "; %s developed and maintained by Clifford Wolf <clifford@clifford.at>\n", yosys_version_str);
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index bf1efc4a..ecdfaabf 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -126,7 +126,7 @@ struct EdifBackend : public Backend {
if (top_module_name.empty())
for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
- top_module_name = mod_it.first;
+ top_module_name = mod_it.first.str();
for (auto module_it : design->modules_)
{
@@ -135,7 +135,7 @@ struct EdifBackend : public Backend {
continue;
if (top_module_name.empty())
- top_module_name = module->name;
+ top_module_name = module->name.str();
if (module->processes.size() != 0)
log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index a445e9cc..be0086ff 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -172,7 +172,7 @@ struct SpiceBackend : public Backend {
if (top_module_name.empty())
for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
- top_module_name = mod_it.first;
+ top_module_name = mod_it.first.str();
fprintf(f, "* SPICE netlist generated by %s\n", yosys_version_str);
fprintf(f, "\n");
diff --git a/kernel/log.cc b/kernel/log.cc
index 01f6207e..81cc26da 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -215,7 +215,7 @@ const char *log_signal(const RTLIL::SigSpec &sig, bool autoint)
const char *log_id(RTLIL::IdString str)
{
- const char *p = str;
+ const char *p = str.c_str();
log_assert(RTLIL::IdString::global_refcount_storage_[str.index_] > 1);
if (p[0] == '\\' && p[1] != '$' && p[1] != 0)
return p+1;
diff --git a/kernel/register.cc b/kernel/register.cc
index 4d204069..868dbb94 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -240,7 +240,7 @@ void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &sele
void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command)
{
std::string backup_selected_active_module = design->selected_active_module;
- design->selected_active_module = module->name;
+ design->selected_active_module = module->name.str();
design->selection_stack.push_back(RTLIL::Selection(false));
design->selection_stack.back().select(module);
@@ -253,7 +253,7 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::str
void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args)
{
std::string backup_selected_active_module = design->selected_active_module;
- design->selected_active_module = module->name;
+ design->selected_active_module = module->name.str();
design->selection_stack.push_back(RTLIL::Selection(false));
design->selection_stack.back().select(module);
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 9ee8123f..2838449b 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -286,7 +286,7 @@ void RTLIL::Design::check()
for (auto &it : modules_) {
log_assert(this == it.second->design);
log_assert(it.first == it.second->name);
- log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+ log_assert(!it.first.empty());
it.second->check();
}
#endif
@@ -499,7 +499,7 @@ namespace {
void check()
{
- if (cell->type[0] != '$' || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
+ if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
return;
@@ -818,38 +818,38 @@ void RTLIL::Module::check()
for (auto &it : wires_) {
log_assert(this == it.second->module);
log_assert(it.first == it.second->name);
- log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+ log_assert(!it.first.empty());
log_assert(it.second->width >= 0);
log_assert(it.second->port_id >= 0);
for (auto &it2 : it.second->attributes) {
- log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+ log_assert(!it2.first.empty());
}
}
for (auto &it : memories) {
log_assert(it.first == it.second->name);
- log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+ log_assert(!it.first.empty());
log_assert(it.second->width >= 0);
log_assert(it.second->size >= 0);
for (auto &it2 : it.second->attributes) {
- log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+ log_assert(!it2.first.empty());
}
}
for (auto &it : cells_) {
log_assert(this == it.second->module);
log_assert(it.first == it.second->name);
- log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
- log_assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
+ log_assert(!it.first.empty());
+ log_assert(!it.second->type.empty());
for (auto &it2 : it.second->connections()) {
- log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+ log_assert(!it2.first.empty());
it2.second.check();
}
for (auto &it2 : it.second->attributes) {
- log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+ log_assert(!it2.first.empty());
}
for (auto &it2 : it.second->parameters) {
- log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+ log_assert(!it2.first.empty());
}
InternalCellChecker checker(this, it.second);
checker.check();
@@ -857,7 +857,7 @@ void RTLIL::Module::check()
for (auto &it : processes) {
log_assert(it.first == it.second->name);
- log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+ log_assert(!it.first.empty());
// FIXME: More checks here..
}
@@ -868,7 +868,7 @@ void RTLIL::Module::check()
}
for (auto &it : attributes) {
- log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+ log_assert(!it.first.empty());
}
#endif
}
@@ -1597,7 +1597,7 @@ void RTLIL::Cell::check()
void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
{
- if (type[0] != '$' || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
+ if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
return;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 6529603e..502969a1 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -162,11 +162,7 @@ namespace RTLIL
*this = id;
}
- const char*c_str() const {
- return global_id_storage_.at(index_);
- }
-
- operator const char*() const {
+ const char *c_str() const {
return global_id_storage_.at(index_);
}
@@ -193,6 +189,10 @@ namespace RTLIL
return c_str()[i];
}
+ char operator[](size_t i) const {
+ return c_str()[i];
+ }
+
std::string substr(size_t pos = 0, size_t len = std::string::npos) const {
if (len == std::string::npos || len >= strlen(c_str() + pos))
return std::string(c_str() + pos);
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 19664357..77419e61 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -303,7 +303,7 @@ static void handle_loops()
id1 = id2;
else if (edges[id1].size() > edges[id2].size())
continue;
- else if (w1->name > w2->name)
+ else if (w2->name < w1->name)
id1 = id2;
}
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 260e7b5d..9f800c31 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -192,7 +192,7 @@ struct DesignPass : public Pass {
for (auto mod : copy_src_modules)
{
- std::string trg_name = as_name.empty() ? std::string(mod->name) : RTLIL::escape_id(as_name);
+ std::string trg_name = as_name.empty() ? mod->name.str() : RTLIL::escape_id(as_name);
if (copy_to_design->modules_.count(trg_name))
delete copy_to_design->modules_.at(trg_name);
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index b4f4d26a..2d49e85e 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -1080,7 +1080,7 @@ struct SelectPass : public Pass {
RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]);
if (design->modules_.count(mod_name) == 0)
log_cmd_error("No such module: %s\n", id2cstr(mod_name));
- design->selected_active_module = mod_name;
+ design->selected_active_module = mod_name.str();
got_module = true;
continue;
}
@@ -1304,7 +1304,7 @@ struct CdPass : public Pass {
if (design->modules_.count(design->selected_active_module) > 0)
module = design->modules_.at(design->selected_active_module);
if (module != NULL && module->cells_.count(modname) > 0)
- modname = module->cells_.at(modname)->type;
+ modname = module->cells_.at(modname)->type.str();
}
if (design->modules_.count(modname) > 0) {
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index bbc0ff44..cbc4725f 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -322,7 +322,7 @@ struct ShowWorker
else if (it.second->port_output)
all_sinks.insert(stringf("n%d", id2num(it.first)));
} else {
- wires_on_demand[stringf("n%d", id2num(it.first))] = it.first;
+ wires_on_demand[stringf("n%d", id2num(it.first))] = it.first.str();
}
}
diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc
index 97ccf91e..cb762dc1 100644
--- a/passes/fsm/fsm_export.cc
+++ b/passes/fsm/fsm_export.cc
@@ -61,7 +61,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
kiss_name.assign(attr_it->second.decode_string());
}
else {
- kiss_name.assign(module->name);
+ kiss_name.assign(module->name.str());
kiss_name.append('-' + cell->name.str() + ".kiss2");
}
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 471a7d53..9c670f00 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -126,7 +126,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
}
std::stringstream sstr;
- sstr << "$mem$" << memory->name << "$" << (autoidx++);
+ sstr << "$mem$" << memory->name.str() << "$" << (autoidx++);
RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem");
mem->parameters["\\MEMID"] = RTLIL::Const(memory->name.str());
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 06af2923..985d51e5 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -240,8 +240,8 @@ namespace
if (sig_bit_ref.count(bit) == 0) {
bit_ref_t &bit_ref = sig_bit_ref[bit];
- bit_ref.cell = cell->name;
- bit_ref.port = conn.first;
+ bit_ref.cell = cell->name.str();
+ bit_ref.port = conn.first.str();
bit_ref.bit = i;
}
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 374fa9bf..c639cc48 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -155,7 +155,7 @@ struct TechmapWorker
if (!flatten_mode)
for (auto &it : tpl->cells_)
if (it.first == "\\_TECHMAP_REPLACE_") {
- orig_cell_name = cell->name;
+ orig_cell_name = cell->name.str();
module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
break;
}