diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-08-13 09:30:20 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-08-13 09:30:20 +0200 |
| commit | 08ad5409a2e5b6dda9f9b2c361e6d82bf0551e51 (patch) | |
| tree | 9281a91c8effbebe727ed1391b2e9036ef3b5361 | |
| parent | 667b0150185d53578b002a00df9c4f347a35fed2 (diff) | |
Some ASCII encoding fixes (comments and docs) by Larry Doolittle
| -rw-r--r-- | manual/APPNOTE_010_Verilog_to_BLIF.tex | 6 | ||||
| -rw-r--r-- | passes/cmds/scc.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/abc.cc | 2 | ||||
| -rw-r--r-- | tests/asicworld/code_hdl_models_up_counter.v | 2 |
4 files changed, 6 insertions, 6 deletions
diff --git a/manual/APPNOTE_010_Verilog_to_BLIF.tex b/manual/APPNOTE_010_Verilog_to_BLIF.tex index 3e36fa38..0ecdf619 100644 --- a/manual/APPNOTE_010_Verilog_to_BLIF.tex +++ b/manual/APPNOTE_010_Verilog_to_BLIF.tex @@ -100,7 +100,7 @@ regression testing Yosys. \section{Getting Started} -We start our tour with the Navré processor from yosys-bigsim. The Navré +We start our tour with the Navr\'e processor from yosys-bigsim. The Navr\'e processor \cite{navre} is an Open Source AVR clone. It is a single module ({\tt softusb\_navre}) in a single design file ({\tt softusb\_navre.v}). It also is using only features that map nicely to the BLIF format, for example it only @@ -226,7 +226,7 @@ further processed using custom commands. But in this case we don't want that. \medskip So now we have the final synthesis script for generating a BLIF file -for the Navré CPU: +for the Navr\'e CPU: \begin{figure}[H] \begin{lstlisting}[language=sh] @@ -445,7 +445,7 @@ yosys-bigsim, a collection of real-world Verilog designs for regression testing \url{https://github.com/cliffordwolf/yosys-bigsim} \bibitem{navre} -Sebastien Bourdeauducq. Navré AVR clone (8-bit RISC). \\ +Sebastien Bourdeauducq. Navr\'e AVR clone (8-bit RISC). \\ \url{http://opencores.org/project,navre} \bibitem{amber} diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 4acb5aef..43a43b4f 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -18,7 +18,7 @@ */ // [[CITE]] Tarjan's strongly connected components algorithm -// Tarjan, R. E. (1972), "Depth-first search and linear graph algorithms", SIAM Journal on Computing 1 (2): 146–160, doi:10.1137/0201010 +// Tarjan, R. E. (1972), "Depth-first search and linear graph algorithms", SIAM Journal on Computing 1 (2): 146-160, doi:10.1137/0201010 // http://en.wikipedia.org/wiki/Tarjan's_strongly_connected_components_algorithm #include "kernel/register.h" diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 1449f2e8..c19593f0 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -26,7 +26,7 @@ // http://www.ece.cmu.edu/~ee760/760docs/blif.pdf // [[CITE]] Kahn's Topological sorting algorithm -// Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558–562, doi:10.1145/368996.369025 +// Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558-562, doi:10.1145/368996.369025 // http://en.wikipedia.org/wiki/Topological_sorting #define ABC_COMMAND_LIB "strash; scorr; ifraig; retime {D}; strash; dch -f; map {D}" diff --git a/tests/asicworld/code_hdl_models_up_counter.v b/tests/asicworld/code_hdl_models_up_counter.v index ffe67099..e0530218 100644 --- a/tests/asicworld/code_hdl_models_up_counter.v +++ b/tests/asicworld/code_hdl_models_up_counter.v @@ -2,7 +2,7 @@ // Design Name : up_counter // File Name : up_counter.v // Function : Up counter -// Coder : Deepak +// Coder : Deepak //----------------------------------------------------- module up_counter ( out , // Output of the counter |