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authorClifford Wolf <clifford@clifford.at>2013-06-13 11:18:45 +0200
committerClifford Wolf <clifford@clifford.at>2013-06-13 11:18:45 +0200
commit0c6ffc4c656de69c92727580cd4c192211d10e6d (patch)
tree9ad133c4d71f687f1046692e1a80481d3d114a89
parentb1d39aa8656f8440eb748fbc7b5673d2129a2308 (diff)
More fixes for bugs found using xsthammer
-rw-r--r--frontends/ast/genrtlil.cc6
-rw-r--r--frontends/verilog/lexer.l4
-rw-r--r--frontends/verilog/parser.y14
-rw-r--r--kernel/satgen.h1
-rw-r--r--techlibs/stdcells.v15
5 files changed, 24 insertions, 16 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index cb59246c..aa5a98c4 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -752,7 +752,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint)
RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint);
is_signed = type == AST_NEG || (type == AST_POS && children[0]->is_signed);
int width = type == AST_NEG && arg.width < width_hint ? arg.width+1 : arg.width;
- if (width > width_hint && width_hint > 0)
+ if (width_hint > 0)
width = width_hint;
return uniop2rtlil(this, type_name, width, arg);
}
@@ -766,9 +766,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint)
RTLIL::SigSpec left = children[0]->genRTLIL(width_hint);
RTLIL::SigSpec right = children[1]->genRTLIL(width_hint);
int width = std::max(left.width, right.width);
- if (width > width_hint && width_hint > 0)
- width = width_hint;
- if (width < width_hint)
+ if (width_hint > 0)
width = width_hint;
return binop2rtlil(this, type_name, width, left, right);
}
diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l
index 783b790b..78f1d367 100644
--- a/frontends/verilog/lexer.l
+++ b/frontends/verilog/lexer.l
@@ -236,8 +236,8 @@ supply1 { return TOK_SUPPLY1; }
"===" { return OP_EQ; }
"!==" { return OP_NE; }
- /* "~&" { return OP_NAND; } */
- /* "~|" { return OP_NOR; } */
+"~&" { return OP_NAND; }
+"~|" { return OP_NOR; }
"~^" { return OP_XNOR; }
"^~" { return OP_XNOR; }
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index ea39e83d..68ac26bf 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -113,9 +113,9 @@ static void free_attr(std::map<std::string, AstNode*> *al)
// operator precedence from low to high
%left OP_LOR
%left OP_LAND
-%left '|'
+%left '|' OP_NOR
%left '^' OP_XNOR
-%left '&'
+%left '&' OP_NAND
%left OP_EQ OP_NE
%left '<' OP_LE OP_GE '>'
%left OP_SHL OP_SHR OP_SSHL OP_SSHR
@@ -982,10 +982,20 @@ basic_expr:
$$ = new AstNode(AST_REDUCE_AND, $3);
append_attr($$, $2);
} |
+ OP_NAND attr basic_expr %prec UNARY_OPS {
+ $$ = new AstNode(AST_REDUCE_AND, $3);
+ append_attr($$, $2);
+ $$ = new AstNode(AST_LOGIC_NOT, $$);
+ } |
'|' attr basic_expr %prec UNARY_OPS {
$$ = new AstNode(AST_REDUCE_OR, $3);
append_attr($$, $2);
} |
+ OP_NOR attr basic_expr %prec UNARY_OPS {
+ $$ = new AstNode(AST_REDUCE_OR, $3);
+ append_attr($$, $2);
+ $$ = new AstNode(AST_LOGIC_NOT, $$);
+ } |
'^' attr basic_expr %prec UNARY_OPS {
$$ = new AstNode(AST_REDUCE_XOR, $3);
append_attr($$, $2);
diff --git a/kernel/satgen.h b/kernel/satgen.h
index 05afeabf..991853c2 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -128,6 +128,7 @@ struct SatGen
if (cell->type == "$_INV_" || cell->type == "$not") {
std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
+ extendSignalWidthUnary(a, y, cell);
ez->assume(ez->vec_eq(ez->vec_not(a), y));
return true;
}
diff --git a/techlibs/stdcells.v b/techlibs/stdcells.v
index 41e20214..59209f9b 100644
--- a/techlibs/stdcells.v
+++ b/techlibs/stdcells.v
@@ -41,17 +41,16 @@ parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
+wire [Y_WIDTH-1:0] A_buf;
+\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+
genvar i;
generate
for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
- if (i < A_WIDTH) begin
- \$_INV_ gate (
- .A(A[i]),
- .Y(Y[i])
- );
- end else begin
- assign Y[i] = 0;
- end
+ \$_INV_ gate (
+ .A(A_buf[i]),
+ .Y(Y[i])
+ );
end
endgenerate