Renamed "stdcells.v" to "techmap.v"

9 files changed, 15 insertions, 12 deletions

diff --git a/CHECKLISTS b/CHECKLISTS
index 8a149a53..3a06e61e 100644
--- a/CHECKLISTS
+++ b/CHECKLISTS
@@ -124,7 +124,7 @@ Things to do right away:
 	- Add to kernel/celltypes.h (incl. eval() handling for non-mem cells)
 	- Add to InternalCellChecker::check() in kernel/rtlil.cc
 	- Add to techlibs/common/simlib.v
-	- Add to techlibs/common/stdcells.v
+	- Add to techlibs/common/techmap.v
 
 Things to do after finalizing the cell interface:
 
diff --git a/README b/README
index 4384cfbd..1e0ade91 100644
--- a/README
+++ b/README
@@ -304,8 +304,7 @@ Roadmap / Large-scale TODOs
    - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim
 
 - Technology mapping for real-world applications
-   - Add bit-wise const-folding via cell parameters to techmap pass
-   - Rewrite current stdcells.v techmap rules (modular and clean)
+   - Rewrite current techmap.v rules (modular and clean)
    - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.)
 
 - Implement SAT-based formal equivialence checker
diff --git a/manual/CHAPTER_Techmap.tex b/manual/CHAPTER_Techmap.tex
index be74c356..26632d0b 100644
--- a/manual/CHAPTER_Techmap.tex
+++ b/manual/CHAPTER_Techmap.tex
@@ -27,7 +27,7 @@ cells with the provided implementation.
 
 When no map file is provided, {\tt techmap} uses a built-in map file that
 maps the Yosys RTL cell types to the internal gate library used by Yosys.
-The curious reader may find this map file as {\tt techlibs/common/stdcells.v} in
+The curious reader may find this map file as {\tt techlibs/common/techmap.v} in
 the Yosys source tree.
 
 Additional features have been added to {\tt techmap} to allow for conditional
diff --git a/passes/techmap/.gitignore b/passes/techmap/.gitignore
index ca9d3942..e6dcc6bc 100644
--- a/passes/techmap/.gitignore
+++ b/passes/techmap/.gitignore
@@ -1 +1 @@
-stdcells.inc
+techmap.inc
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index e54c018a..b49259a8 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -10,16 +10,16 @@ OBJS += passes/techmap/hilomap.o
 OBJS += passes/techmap/extract.o
 endif
 
-GENFILES += passes/techmap/stdcells.inc
+GENFILES += passes/techmap/techmap.inc
 
-passes/techmap/stdcells.inc: techlibs/common/stdcells.v
+passes/techmap/techmap.inc: techlibs/common/techmap.v
 	$(P) echo "// autogenerated from $<" > $@.new
 	$(Q) echo "static char stdcells_code[] = {" >> $@.new
 	$(Q) od -v -td1 -An $< | $(SED) -e 's/[0-9][0-9]*/&,/g' >> $@.new
 	$(Q) echo "0};" >> $@.new
 	$(Q) mv $@.new $@
 
-passes/techmap/techmap.o: passes/techmap/stdcells.inc
+passes/techmap/techmap.o: passes/techmap/techmap.inc
 
 TARGETS += yosys-filterlib
 GENFILES += passes/techmap/filterlib.o
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 50936af0..2aa59e61 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -26,7 +26,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "passes/techmap/stdcells.inc"
+#include "passes/techmap/techmap.inc"
 
 // see simplemap.cc
 extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
@@ -790,7 +790,7 @@ struct TechmapPass : public Pass {
 		RTLIL::Design *map = new RTLIL::Design;
 		if (map_files.empty()) {
 			FILE *f = fmemopen(stdcells_code, strlen(stdcells_code), "rt");
-			Frontend::frontend_call(map, f, "<stdcells.v>", verilog_frontend);
+			Frontend::frontend_call(map, f, "<techmap.v>", verilog_frontend);
 			fclose(f);
 		} else
 			for (auto &fn : map_files)
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index a76d1a07..2be27b92 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -5,7 +5,7 @@ techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.
 	$(P) cat techlibs/common/simlib.v techlibs/common/simcells.v | $(SED) -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new
 	$(Q) mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v
 
-EXTRA_TARGETS += share/simlib.v share/simcells.v share/blackbox.v share/pmux2mux.v
+EXTRA_TARGETS += share/simlib.v share/simcells.v share/techmap.v share/blackbox.v share/pmux2mux.v
 
 share/simlib.v: techlibs/common/simlib.v
 	$(P) mkdir -p share
@@ -15,6 +15,10 @@ share/simcells.v: techlibs/common/simcells.v
 	$(P) mkdir -p share
 	$(Q) cp techlibs/common/simcells.v share/simcells.v
 
+share/techmap.v: techlibs/common/techmap.v
+	$(P) mkdir -p share
+	$(Q) cp techlibs/common/techmap.v share/techmap.v
+
 share/blackbox.v: techlibs/common/blackbox.v
 	$(P) mkdir -p share
 	$(Q) cp techlibs/common/blackbox.v share/blackbox.v
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 5ecec789..d492c2f1 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -21,7 +21,7 @@
  *
  *  This verilog library contains simple simulation models for the internal
  *  logic cells ($_INV_ , $_AND_ , ...) that are generated by the default technology
- *  mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
+ *  mapper (see "techmap.v" in this directory) and expected by the "abc" pass.
  *
  */
 
diff --git a/techlibs/common/stdcells.v b/techlibs/common/techmap.v
index 54652868..54652868 100644
--- a/techlibs/common/stdcells.v
+++ b/techlibs/common/techmap.v