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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-07-12 13:41:39 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2019-10-18 23:27:34 +0200 |
| commit | 12603432fed7e0332f09f34fad0bcc9aa88bd456 (patch) | |
| tree | 6bfc694ec2b40f91e6c66b2d2a0ba67f5f044461 | |
| parent | 1a4451589002afcec33f9b098a3584fe4beae2f1 (diff) | |
Some spelling errors fixed
Gbp-Pq: Name 0009-Some-spelling-errors-fixed.patch
| -rw-r--r-- | frontends/ast/genrtlil.cc | 2 | ||||
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 2 | ||||
| -rw-r--r-- | manual/command-reference-manual.tex | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 571ddd98..cee344a2 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -558,7 +558,7 @@ struct AST_INTERNAL::ProcessGenerator break; case AST_ASSIGN: - log_file_error(ast->filename, ast->linenum, "Found continous assignment in always/initial block!\n"); + log_file_error(ast->filename, ast->linenum, "Found continuous assignment in always/initial block!\n"); break; case AST_PARAMETER: diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 3009bf2c..4136efed 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -240,7 +240,7 @@ An RTLIL::Wire object has the following properties: As with modules, the attributes can be Verilog attributes imported by the Verilog frontend or attributes assigned by passes. -In Yosys, busses (signal vectors) are represented using a single wire object +In Yosys, buses (signal vectors) are represented using a single wire object with a width > 1. So Yosys does not convert signal vectors to individual signals. This makes some aspects of RTLIL more complex but enables Yosys to be used for coarse grain synthesis where the cells of the target architecture operate on diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index bed6326e..eb434676 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -3182,7 +3182,7 @@ to a graphics file (usually SVG or PostScript). assigned to each unique value of this attribute. -width - annotate busses with a label indicating the width of the bus. + annotate buses with a label indicating the width of the bus. -signed mark ports (A, B) that are declared as signed (using the [AB]_SIGNED |