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authorClifford Wolf <clifford@clifford.at>2014-10-16 11:49:31 +0200
committerClifford Wolf <clifford@clifford.at>2014-10-16 11:49:31 +0200
commit18cb8b4636933cb5a1ad3040f061d53345d1aa1d (patch)
tree6fef7c7b533b0bb07e2eda73f4dab8fcabc5889b
parent66eb254fc2595a6dcd94b439b0b287cc59c47270 (diff)
Don't be too smart with $dff cells with "init" attribute on out signal
-rw-r--r--passes/opt/opt_rmdff.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index c7e92ddc..5f52bb8d 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -83,7 +83,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx);
}
- if (dff->type == "$dff" && mux_drivers.has(sig_d)) {
+ if (dff->type == "$dff" && mux_drivers.has(sig_d) && !has_init) {
std::set<RTLIL::Cell*> muxes;
mux_drivers.find(sig_d, muxes);
for (auto mux : muxes) {