Added module->ports

9 files changed, 23 insertions, 10 deletions

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index f18124e2..9f17f3bf 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -919,6 +919,7 @@ static AstModule* process_module(AstNode *ast, bool defer)
 	current_module->noopt = flag_noopt;
 	current_module->icells = flag_icells;
 	current_module->autowire = flag_autowire;
+	current_module->fixup_ports();
 	return current_module;
 }
 
diff --git a/frontends/ilang/parser.y b/frontends/ilang/parser.y
index f696140e..e1ef39a5 100644
--- a/frontends/ilang/parser.y
+++ b/frontends/ilang/parser.y
@@ -101,6 +101,7 @@ module:
 	} module_body TOK_END {
 		if (attrbuf.size() != 0)
 			rtlil_frontend_ilang_yyerror("dangling attribute");
+		current_module->fixup_ports();
 	} EOL;
 
 module_body:
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 6beaa3fe..5486f6ac 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -67,7 +67,8 @@ struct CellTypes
 	void setup_module(RTLIL::Module *module)
 	{
 		std::set<RTLIL::IdString> inputs, outputs;
-		for (auto wire : module->wires()) {
+		for (RTLIL::IdString wire_name : module->ports) {
+			RTLIL::Wire *wire = module->wire(wire_name);
 			if (wire->port_input)
 				inputs.insert(wire->name);
 			if (wire->port_output)
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index fdb33ed8..96ae0f97 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -821,6 +821,8 @@ void RTLIL::Module::check()
 		for (auto &it2 : it.second->attributes)
 			log_assert(!it2.first.empty());
 		if (it.second->port_id) {
+			log_assert(SIZE(ports) >= it.second->port_id);
+			log_assert(ports.at(it.second->port_id-1) == it.first);
 			log_assert(it.second->port_input || it.second->port_output);
 			if (SIZE(ports_declared) < it.second->port_id)
 				ports_declared.resize(it.second->port_id);
@@ -831,6 +833,7 @@ void RTLIL::Module::check()
 	}
 	for (auto port_declared : ports_declared)
 		log_assert(port_declared == true);
+	log_assert(SIZE(ports) == SIZE(ports_declared));
 
 	for (auto &it : memories) {
 		log_assert(it.first == it.second->name);
@@ -915,6 +918,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
 	RewriteSigSpecWorker rewriteSigSpecWorker;
 	rewriteSigSpecWorker.mod = new_mod;
 	new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
+	new_mod->fixup_ports();
 }
 
 RTLIL::Module *RTLIL::Module::clone() const
@@ -1154,8 +1158,12 @@ void RTLIL::Module::fixup_ports()
 			w.second->port_id = 0;
 
 	std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
-	for (size_t i = 0; i < all_ports.size(); i++)
+
+	ports.clear();
+	for (size_t i = 0; i < all_ports.size(); i++) {
+		ports.push_back(all_ports[i]->name);
 		all_ports[i]->port_id = i+1;
+	}
 }
 
 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 10da7463..0093b8a1 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -575,6 +575,8 @@ public:
 	void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
 	void new_connections(const std::vector<RTLIL::SigSig> &new_conn);
 	const std::vector<RTLIL::SigSig> &connections() const;
+
+	std::vector<RTLIL::IdString> ports;
 	void fixup_ports();
 
 	template<typename T> void rewrite_sigspecs(T functor);
diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc
index 1891a745..bc8f343a 100644
--- a/passes/abc/blifparse.cc
+++ b/passes/abc/blifparse.cc
@@ -58,7 +58,6 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 	RTLIL::Const *lutptr = NULL;
 	RTLIL::State lut_default_state = RTLIL::State::Sx;
 
-	int port_count = 0;
 	module->name = "\\netlist";
 	design->add(module);
 
@@ -91,6 +90,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 				continue;
 
 			if (!strcmp(cmd, ".end")) {
+				module->fixup_ports();
 				free(buffer);
 				return design;
 			}
@@ -99,7 +99,6 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 				char *p;
 				while ((p = strtok(NULL, " \t\r\n")) != NULL) {
 					RTLIL::Wire *wire = module->addWire(stringf("\\%s", p));
-					wire->port_id = ++port_count;
 					if (!strcmp(cmd, ".inputs"))
 						wire->port_input = true;
 					else
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 50b4989d..2f28afb2 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -126,6 +126,8 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 			wire->port_output = decl.output;
 		}
 
+		mod->fixup_ports();
+
 		for (auto &para : parameters)
 			log("  ignoring parameter %s.\n", RTLIL::id2cstr(para));
 
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 89f45e02..1b03ab55 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -106,7 +106,7 @@ struct SubmodWorker
 		RTLIL::Module *new_mod = new RTLIL::Module;
 		new_mod->name = submod.full_name;
 		design->add(new_mod);
-		int port_counter = 1, auto_name_counter = 1;
+		int auto_name_counter = 1;
 
 		std::set<RTLIL::IdString> all_wire_names;
 		for (auto &it : wire_flags) {
@@ -151,9 +151,6 @@ struct SubmodWorker
 			new_wire->start_offset = wire->start_offset;
 			new_wire->attributes = wire->attributes;
 
-			if (new_wire->port_input || new_wire->port_output)
-				new_wire->port_id = port_counter++;
-
 			if (new_wire->port_input && new_wire->port_output)
 				log("  signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());
 			else if (new_wire->port_input)
@@ -166,6 +163,8 @@ struct SubmodWorker
 			flags.new_wire = new_wire;
 		}
 
+		new_mod->fixup_ports();
+
 		for (RTLIL::Cell *cell : submod.cells) {
 			RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
 			for (auto &conn : new_cell->connections_)
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 985d51e5..ebf4d77f 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -726,14 +726,14 @@ struct ExtractPass : public Pass {
 				newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
 				map->add(newMod);
 
-				int portCounter = 1;
 				for (auto wire : wires) {
 					RTLIL::Wire *newWire = newMod->addWire(wire->name, wire->width);
-					newWire->port_id = portCounter++;
 					newWire->port_input = true;
 					newWire->port_output = true;
 				}
 
+				newMod->fixup_ports();
+
 				for (auto cell : cells) {
 					RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type);
 					newCell->parameters = cell->parameters;