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authorAhmed Irfan <irfan@ubuntu.(none)>2014-01-18 18:10:31 +0100
committerAhmed Irfan <irfan@ubuntu.(none)>2014-01-18 18:10:31 +0100
commit1dd797ab09d2fb6a4ab903cfa050fa51cfcc6dcd (patch)
tree3c254e7a3ca11831e463d9a4ce88b5aea0677952
parent66198d8591a66b8ec34237c1151d992c7f4d5224 (diff)
parentbef17eeb109dd2dc4eaba6eb808a0172c0c53265 (diff)
Merge branch 'master' of https://github.com/cliffordwolf/yosys
-rw-r--r--frontends/verilog/verilog_frontend.cc66
-rw-r--r--kernel/log.h7
-rw-r--r--kernel/rtlil.h3
-rw-r--r--passes/cmds/Makefile.inc1
-rw-r--r--passes/cmds/select.cc51
-rw-r--r--passes/cmds/setundef.cc157
-rw-r--r--passes/memory/Makefile.inc1
-rw-r--r--passes/memory/memory_unpack.cc116
-rw-r--r--passes/opt/opt_rmdff.cc6
-rw-r--r--techlibs/common/Makefile.inc6
-rw-r--r--techlibs/common/pmux2mux.v21
-rw-r--r--techlibs/common/simlib.v22
-rw-r--r--techlibs/common/stdcells.v6
13 files changed, 451 insertions, 12 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index dcccb4e9..142e5e72 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -38,6 +38,9 @@ using namespace VERILOG_FRONTEND;
// use the Verilog bison/flex parser to generate an AST and use AST::process() to convert it to RTLIL
+static std::vector<std::string> verilog_defaults;
+static std::list<std::vector<std::string>> verilog_defaults_stack;
+
struct VerilogFrontend : public Frontend {
VerilogFrontend() : Frontend("verilog", "read modules from verilog file") { }
virtual void help()
@@ -108,6 +111,9 @@ struct VerilogFrontend : public Frontend {
log(" add 'dir' to the directories which are used when searching include\n");
log(" files\n");
log("\n");
+ log("The command 'verilog_defaults' can be used to register default options for\n");
+ log("subsequent calls to 'read_verilog'.\n");
+ log("\n");
}
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
@@ -128,6 +134,8 @@ struct VerilogFrontend : public Frontend {
log_header("Executing Verilog-2005 frontend.\n");
+ args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end());
+
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx];
@@ -248,3 +256,61 @@ void frontend_verilog_yyerror(char const *fmt, ...)
exit(1);
}
+struct VerilogDefaults : public Pass {
+ VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" verilog_defaults -add [options]\n");
+ log("\n");
+ log("Add the sepcified options to the list of default options to read_verilog.\n");
+ log("\n");
+ log("\n");
+ log(" verilog_defaults -clear");
+ log("\n");
+ log("Clear the list of verilog default options.\n");
+ log("\n");
+ log("\n");
+ log(" verilog_defaults -push");
+ log(" verilog_defaults -pop");
+ log("\n");
+ log("Push or pop the list of default options to a stack. Note that -push does\n");
+ log("not imply -clear.\n");
+ log("\n");
+ }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design*)
+ {
+ if (args.size() == 0)
+ cmd_error(args, 1, "Missing argument.");
+
+ if (args[1] == "-add") {
+ verilog_defaults.insert(verilog_defaults.end(), args.begin()+2, args.end());
+ return;
+ }
+
+ if (args.size() != 2)
+ cmd_error(args, 2, "Extra argument.");
+
+ if (args[1] == "-clear") {
+ verilog_defaults.clear();
+ return;
+ }
+
+ if (args[1] == "-push") {
+ verilog_defaults_stack.push_back(verilog_defaults);
+ return;
+ }
+
+ if (args[1] == "-pop") {
+ if (verilog_defaults_stack.empty()) {
+ verilog_defaults.clear();
+ } else {
+ verilog_defaults.swap(verilog_defaults_stack.back());
+ verilog_defaults_stack.pop_back();
+ }
+ return;
+ }
+ }
+} VerilogDefaults;
+
diff --git a/kernel/log.h b/kernel/log.h
index 5ee6b565..c4c03352 100644
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -95,11 +95,16 @@ struct PerformanceTimer
// simple API for quickly dumping values when debugging
+static inline void log_dump_val_worker(short v) { log("%d", v); }
+static inline void log_dump_val_worker(unsigned short v) { log("%u", v); }
static inline void log_dump_val_worker(int v) { log("%d", v); }
-static inline void log_dump_val_worker(size_t v) { log("%zd", v); }
+static inline void log_dump_val_worker(unsigned int v) { log("%u", v); }
static inline void log_dump_val_worker(long int v) { log("%ld", v); }
+static inline void log_dump_val_worker(unsigned long int v) { log("%lu", v); }
static inline void log_dump_val_worker(long long int v) { log("%lld", v); }
+static inline void log_dump_val_worker(unsigned long long int v) { log("%lld", v); }
static inline void log_dump_val_worker(char c) { log(c >= 32 && c < 127 ? "'%c'" : "'\\x%02x'", c); }
+static inline void log_dump_val_worker(unsigned char c) { log(c >= 32 && c < 127 ? "'%c'" : "'\\x%02x'", c); }
static inline void log_dump_val_worker(bool v) { log("%s", v ? "true" : "false"); }
static inline void log_dump_val_worker(double v) { log("%f", v); }
static inline void log_dump_val_worker(const char *v) { log("%s", v); }
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 504fdbbd..e0b3a693 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -227,6 +227,9 @@ struct RTLIL::Selection {
if (!full_selection && selected_modules.count(module->name) == 0)
selected_members[module->name].insert(member->name);
}
+ bool empty() const {
+ return !full_selection && selected_modules.empty() && selected_members.empty();
+ }
};
struct RTLIL::Design {
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index 9e96ff36..ea70f40c 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -6,6 +6,7 @@ OBJS += passes/cmds/show.o
OBJS += passes/cmds/rename.o
OBJS += passes/cmds/connect.o
OBJS += passes/cmds/scatter.o
+OBJS += passes/cmds/setundef.o
OBJS += passes/cmds/splitnets.o
OBJS += passes/cmds/stat.o
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index ec560772..55054538 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -656,6 +656,7 @@ struct SelectPass : public Pass {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" select [ -add | -del | -set <name> ] <selection>\n");
+ log(" select [ -assert-none | -assert-any ] <selection>\n");
log(" select [ -list | -write <filename> | -count | -clear ]\n");
log(" select -module <modname>\n");
log("\n");
@@ -676,6 +677,14 @@ struct SelectPass : public Pass {
log(" do not modify the current selection. instead save the new selection\n");
log(" under the given name (see @<name> below).\n");
log("\n");
+ log(" -assert-none\n");
+ log(" asserts that the given selection is empty. i.e. produce an error if\n");
+ log(" any object matching the selection is found.\n");
+ log("\n");
+ log(" -assert-any\n");
+ log(" asserts that the given selection is non-empty. i.e. produce an error\n");
+ log(" if no object matching the selection is found.\n");
+ log("\n");
log(" -list\n");
log(" list all objects in the current selection\n");
log("\n");
@@ -802,6 +811,8 @@ struct SelectPass : public Pass {
bool list_mode = false;
bool count_mode = false;
bool got_module = false;
+ bool assert_none = false;
+ bool assert_any = false;
std::string write_file;
std::string set_name;
@@ -819,6 +830,14 @@ struct SelectPass : public Pass {
del_mode = true;
continue;
}
+ if (arg == "-assert-none") {
+ assert_none = true;
+ continue;
+ }
+ if (arg == "-assert-any") {
+ assert_any = true;
+ continue;
+ }
if (arg == "-clear") {
clear_mode = true;
continue;
@@ -853,16 +872,16 @@ struct SelectPass : public Pass {
}
if (clear_mode && args.size() != 2)
- log_cmd_error("Option -clear can not be combined with other options.\n");
+ log_cmd_error("Option -clear can not be combined with any other options.\n");
- if (add_mode && del_mode)
- log_cmd_error("Options -add and -del can not be combined.\n");
+ if (add_mode + del_mode + assert_none + assert_any > 1)
+ log_cmd_error("Options -add, -del, -assert-none or -assert-any can not be combined.\n");
- if ((list_mode || !write_file.empty() || count_mode) && (add_mode || del_mode))
- log_cmd_error("Options -list, -write and -count can not be combined with -add or -del.\n");
+ if ((list_mode || !write_file.empty() || count_mode) && (add_mode || del_mode || assert_none || assert_any))
+ log_cmd_error("Options -list, -write and -count can not be combined with -add, -del, -assert-none or -assert-any.\n");
- if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || del_mode))
- log_cmd_error("Option -set can not be combined with -list, -write, -count, -add or -del.\n");
+ if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || del_mode || assert_none || assert_any))
+ log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none or -assert-any.\n");
if (work_stack.size() == 0 && got_module) {
RTLIL::Selection sel;
@@ -943,6 +962,24 @@ struct SelectPass : public Pass {
return;
}
+ if (assert_none)
+ {
+ if (work_stack.size() == 0)
+ log_cmd_error("No selection to check.\n");
+ if (!work_stack.back().empty())
+ log_error("Assertation failed: selection is not empty.\n");
+ return;
+ }
+
+ if (assert_any)
+ {
+ if (work_stack.size() == 0)
+ log_cmd_error("No selection to check.\n");
+ if (work_stack.back().empty())
+ log_error("Assertation failed: selection is empty.\n");
+ return;
+ }
+
if (!set_name.empty())
{
if (work_stack.size() == 0)
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
new file mode 100644
index 00000000..9d59834c
--- /dev/null
+++ b/passes/cmds/setundef.cc
@@ -0,0 +1,157 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/sigtools.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+static int next_bit_mode;
+static uint32_t next_bit_state;
+
+static RTLIL::State next_bit()
+{
+ if (next_bit_mode == 0)
+ return RTLIL::State::S0;
+
+ if (next_bit_mode == 1)
+ return RTLIL::State::S1;
+
+ // xorshift32
+ next_bit_state ^= next_bit_state << 13;
+ next_bit_state ^= next_bit_state >> 17;
+ next_bit_state ^= next_bit_state << 5;
+ log_assert(next_bit_state != 0);
+
+ return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1;
+}
+
+struct SetundefWorker
+{
+ void operator()(RTLIL::SigSpec &sig)
+ {
+ sig.expand();
+ for (auto &c : sig.chunks)
+ if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1)
+ c.data.bits.at(0) = next_bit();
+ sig.optimize();
+ }
+};
+
+struct SetundefPass : public Pass {
+ SetundefPass() : Pass("setundef", "replace undef values with defined constants") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" setundef [options] [selection]\n");
+ log("\n");
+ log("This command replaced undef (x) constants with defined (0/1) constants.\n");
+ log("\n");
+ log(" -undriven\n");
+ log(" also set undriven nets to constant values\n");
+ log("\n");
+ log(" -zero\n");
+ log(" replace with bits cleared (0)\n");
+ log("\n");
+ log(" -one\n");
+ log(" replace with bits set (1)\n");
+ log("\n");
+ log(" -random <seed>\n");
+ log(" replace with random bits using the specified integer als seed\n");
+ log(" value for the random number generator.\n");
+ log("\n");
+ }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ {
+ bool got_value = false;
+ bool undriven_mode = false;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-undriven") {
+ undriven_mode = true;
+ continue;
+ }
+ if (args[argidx] == "-zero") {
+ got_value = true;
+ next_bit_mode = 0;
+ continue;
+ }
+ if (args[argidx] == "-one") {
+ got_value = true;
+ next_bit_mode = 1;
+ continue;
+ }
+ if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) {
+ got_value = true;
+ next_bit_mode = 2;
+ next_bit_state = atoi(args[++argidx].c_str()) + 1;
+ for (int i = 0; i < 10; i++)
+ next_bit();
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if (!got_value)
+ log_cmd_error("One of the options -zero, -one, or -random <seed> must be specified.\n");
+
+ for (auto &mod_it : design->modules)
+ {
+ RTLIL::Module *module = mod_it.second;
+ if (!design->selected(module))
+ continue;
+
+ if (undriven_mode)
+ {
+ if (!module->processes.empty())
+ log_error("The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n");
+
+ SigMap sigmap(module);
+ SigPool undriven_signals;
+
+ for (auto &it : module->wires)
+ if (!it.second->port_input)
+ undriven_signals.add(sigmap(it.second));
+
+ CellTypes ct(design);
+ for (auto &it : module->cells)
+ for (auto &conn : it.second->connections)
+ if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
+ undriven_signals.del(sigmap(conn.second));
+
+ RTLIL::SigSpec sig = undriven_signals.export_all();
+ for (auto &c : sig.chunks) {
+ RTLIL::SigSpec bits;
+ for (int i = 0; i < c.width; i++)
+ bits.append(next_bit());
+ bits.optimize();
+ module->connections.push_back(RTLIL::SigSig(c, bits));
+ }
+ }
+
+ module->rewrite_sigspecs(SetundefWorker());
+ }
+ }
+} SetundefPass;
+
diff --git a/passes/memory/Makefile.inc b/passes/memory/Makefile.inc
index cffdefe8..21f17db5 100644
--- a/passes/memory/Makefile.inc
+++ b/passes/memory/Makefile.inc
@@ -2,5 +2,6 @@
OBJS += passes/memory/memory.o
OBJS += passes/memory/memory_dff.o
OBJS += passes/memory/memory_collect.o
+OBJS += passes/memory/memory_unpack.o
OBJS += passes/memory/memory_map.o
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
new file mode 100644
index 00000000..060d8e67
--- /dev/null
+++ b/passes/memory/memory_unpack.cc
@@ -0,0 +1,116 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/log.h"
+#include <sstream>
+#include <algorithm>
+#include <stdlib.h>
+#include <assert.h>
+
+static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
+{
+ log("Creating $memrd and $memwr for memory `%s' in module `%s':\n",
+ memory->name.c_str(), module->name.c_str());
+
+ RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string());
+
+ while (module->memories.count(mem_name) != 0)
+ mem_name += stringf("_%d", RTLIL::autoidx++);
+
+ RTLIL::Memory *mem = new RTLIL::Memory;
+ mem->name = mem_name;
+ mem->width = memory->parameters.at("\\WIDTH").as_int();
+ mem->start_offset = memory->parameters.at("\\OFFSET").as_int();
+ mem->size = memory->parameters.at("\\SIZE").as_int();
+ module->memories[mem_name] = mem;
+
+ int abits = memory->parameters.at("\\ABITS").as_int();
+ int num_rd_ports = memory->parameters.at("\\RD_PORTS").as_int();
+ int num_wr_ports = memory->parameters.at("\\WR_PORTS").as_int();
+
+ for (int i = 0; i < num_rd_ports; i++)
+ {
+ RTLIL::Cell *cell = new RTLIL::Cell;
+ cell->name = NEW_ID;
+ cell->type = "$memrd";
+ cell->parameters["\\MEMID"] = mem_name;
+ cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
+ cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
+ cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const();
+ cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const();
+ cell->connections["\\CLK"] = memory->connections.at("\\RD_CLK").extract(i, 1);
+ cell->connections["\\ADDR"] = memory->connections.at("\\RD_ADDR").extract(i*abits, abits);
+ cell->connections["\\DATA"] = memory->connections.at("\\RD_DATA").extract(i*mem->width, mem->width);
+ module->add(cell);
+ }
+
+ for (int i = 0; i < num_wr_ports; i++)
+ {
+ RTLIL::Cell *cell = new RTLIL::Cell;
+ cell->name = NEW_ID;
+ cell->type = "$memwr";
+ cell->parameters["\\MEMID"] = mem_name;
+ cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
+ cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
+ cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const();
+ cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const();
+ cell->parameters["\\PRIORITY"] = i;
+ cell->connections["\\CLK"] = memory->connections.at("\\WR_CLK").extract(i, 1);
+ cell->connections["\\EN"] = memory->connections.at("\\WR_EN").extract(i, 1);
+ cell->connections["\\ADDR"] = memory->connections.at("\\WR_ADDR").extract(i*abits, abits);
+ cell->connections["\\DATA"] = memory->connections.at("\\WR_DATA").extract(i*mem->width, mem->width);
+ module->add(cell);
+ }
+
+ module->cells.erase(memory->name);
+ delete memory;
+}
+
+static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
+{
+ std::vector<RTLIL::IdString> memcells;
+ for (auto &cell_it : module->cells)
+ if (cell_it.second->type == "$mem" && design->selected(module, cell_it.second))
+ memcells.push_back(cell_it.first);
+ for (auto &it : memcells)
+ handle_memory(module, module->cells.at(it));
+}
+
+struct MemoryUnpackPass : public Pass {
+ MemoryUnpackPass() : Pass("memory_unpack", "unpack multi-port memory cells") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" memory_unpack [selection]\n");
+ log("\n");
+ log("This pass converts the multi-port $mem memory cells into individual $memrd and\n");
+ log("$memwr cells. It is the counterpart to the memory_collect pass.\n");
+ log("\n");
+ }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
+ log_header("Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
+ extra_args(args, 1, design);
+ for (auto &mod_it : design->modules)
+ if (design->selected(mod_it.second))
+ handle_module(design, mod_it.second);
+ }
+} MemoryUnpackPass;
+
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index a84bf437..9ce98004 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -92,6 +92,12 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
}
}
+ if (sig_d.is_fully_undef() && sig_d.width == int(val_rv.bits.size())) {
+ RTLIL::SigSig conn(sig_q, val_rv);
+ mod->connections.push_back(conn);
+ goto delete_dff;
+ }
+
if (sig_d.is_fully_const() && sig_r.width == 0) {
RTLIL::SigSig conn(sig_q, sig_d);
mod->connections.push_back(conn);
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index e2e1ba25..6d94d5c9 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -5,7 +5,7 @@ techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.
cat techlibs/common/simlib.v techlibs/common/simcells.v | sed -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new
mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v
-EXTRA_TARGETS += share/simlib.v share/simcells.v share/blackbox.v
+EXTRA_TARGETS += share/simlib.v share/simcells.v share/blackbox.v share/pmux2mux.v
share/simlib.v: techlibs/common/simlib.v
mkdir -p share
@@ -19,3 +19,7 @@ share/blackbox.v: techlibs/common/blackbox.v
mkdir -p share
cp techlibs/common/blackbox.v share/blackbox.v
+share/pmux2mux.v: techlibs/common/pmux2mux.v
+ mkdir -p share
+ cp techlibs/common/pmux2mux.v share/pmux2mux.v
+
diff --git a/techlibs/common/pmux2mux.v b/techlibs/common/pmux2mux.v
new file mode 100644
index 00000000..9c97245a
--- /dev/null
+++ b/techlibs/common/pmux2mux.v
@@ -0,0 +1,21 @@
+module \$pmux (A, B, S, Y);
+
+wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+parameter WIDTH = 1;
+parameter S_WIDTH = 1;
+
+input [WIDTH-1:0] A;
+input [WIDTH*S_WIDTH-1:0] B;
+input [S_WIDTH-1:0] S;
+output reg [WIDTH-1:0] Y;
+
+integer i;
+
+always @* begin
+ Y <= A;
+ for (i = 0; i < S_WIDTH; i=i+1)
+ if (S[i]) Y <= B[WIDTH*i +: WIDTH];
+end
+
+endmodule
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 034244ca..f3d652f0 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -55,6 +55,28 @@ endmodule
// --------------------------------------------------------
+module \$bu0 (A, Y);
+
+parameter A_SIGNED = 0;
+parameter A_WIDTH = 0;
+parameter Y_WIDTH = 0;
+
+`INPUT_A
+output [Y_WIDTH-1:0] Y;
+
+generate
+ if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:A
+ assign Y[A_WIDTH-1:0] = A_BUF.val;
+ assign Y[Y_WIDTH-1:A_WIDTH] = 0;
+ end else begin:B
+ assign Y = +A_BUF.val;
+ end
+endgenerate
+
+endmodule
+
+// --------------------------------------------------------
+
module \$pos (A, Y);
parameter A_SIGNED = 0;
diff --git a/techlibs/common/stdcells.v b/techlibs/common/stdcells.v
index 4e764078..e33e651c 100644
--- a/techlibs/common/stdcells.v
+++ b/techlibs/common/stdcells.v
@@ -456,7 +456,7 @@ wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
.Cin(1'b1),
.Y(Y_buf),
.Cout(carry),
- .Csign(carry_sign),
+ .Csign(carry_sign)
);
// ALU flags
@@ -505,7 +505,7 @@ wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
.Cin(1'b1),
.Y(Y_buf),
.Cout(carry),
- .Csign(carry_sign),
+ .Csign(carry_sign)
);
// ALU flags
@@ -849,7 +849,7 @@ assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
.A(A_buf_u),
.B(B_buf_u),
.Y(Y_u),
- .R(R_u),
+ .R(R_u)
);
assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;