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authorClifford Wolf <clifford@clifford.at>2013-07-12 13:13:04 +0200
committerClifford Wolf <clifford@clifford.at>2013-07-12 13:13:04 +0200
commit3650fd7fbe45a00792770d9ecb9397bc27ea0845 (patch)
tree0ecf122082e664a9d2d7267bca5a17e8852fba62
parentded769c98cffe5682c0211dba08abc4a1efe3d5a (diff)
More fixes in ternary op sign handling
-rw-r--r--frontends/ast/genrtlil.cc3
-rw-r--r--tests/simple/vloghammer.v8
2 files changed, 11 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index a9574254..e7ceec5f 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -998,6 +998,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// generate multiplexer for ternary operator (aka ?:-operator)
case AST_TERNARY:
{
+ if (width_hint < 0)
+ detectSignWidth(width_hint, sign_hint);
+
RTLIL::SigSpec cond = children[0]->genRTLIL();
RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v
index c97a2be5..fffa3505 100644
--- a/tests/simple/vloghammer.v
+++ b/tests/simple/vloghammer.v
@@ -65,3 +65,11 @@ module test09(a, b, c, y);
assign y = a ? b : c;
endmodule
+module test10(a, b, c, y);
+ input a;
+ input signed [1:0] b;
+ input signed [2:0] c;
+ output y;
+ assign y = ^(a ? b : c);
+endmodule
+