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authorClifford Wolf <clifford@clifford.at>2014-07-23 19:36:43 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-23 19:36:43 +0200
commit3ec785b881a7bbceb5ac4db1e761b75c07f8642a (patch)
tree82dde863d4629a4a5d9e1068da5f4932c6c43074
parenta62c21c9c64ad5b3e0dae5d4ee4857425f73068e (diff)
Fixed manual/CHAPTER_Prog/stubnets.cc
-rw-r--r--manual/CHAPTER_Prog/stubnets.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index efb3ca95..3f8d553a 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -62,7 +62,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// for each bit (unless it is a constant):
// check if it is used at least two times and add to stub_bits otherwise
- for (size_t i = 0; i < SIZE(sig); i++)
+ for (int i = 0; i < SIZE(sig); i++)
if (sig[i].wire != NULL && (bit_usage_count[sig[i]] + usage_offset) < 2)
stub_bits.insert(i);
@@ -72,7 +72,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// report stub bits and/or stub wires, don't report single bits
// if called with report_bits set to false.
- if (int(stub_bits.size()) == sig.width) {
+ if (SIZE(stub_bits) == SIZE(sig)) {
log(" found stub wire: %s\n", RTLIL::id2cstr(wire->name));
} else {
if (!report_bits)