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authorClifford Wolf <clifford@clifford.at>2013-08-07 02:19:35 +0200
committerClifford Wolf <clifford@clifford.at>2013-08-07 02:19:35 +0200
commit3f5d7df603dd80d7f877e8050fc4b572318ae62e (patch)
treee7a63e3fb801ba030c7aaa569d1cf0fb3463f452
parent653750faac4a2bf17440851c2ec7207a6a8ddcaa (diff)
Added stubnets example to manual prog chapter
-rw-r--r--manual/CHAPTER_Prog.tex8
-rw-r--r--manual/FILES_Prog/Makefile11
-rw-r--r--manual/FILES_Prog/stubnets.cc3
3 files changed, 15 insertions, 7 deletions
diff --git a/manual/CHAPTER_Prog.tex b/manual/CHAPTER_Prog.tex
index a1ca383d..b6157aa1 100644
--- a/manual/CHAPTER_Prog.tex
+++ b/manual/CHAPTER_Prog.tex
@@ -11,3 +11,11 @@ with an example module.
\section{Internal Utility Libraries}
\section{Loadable Modules}
+\section{Example Module}
+
+\lstinputlisting[title=stubnets.cc,numbers=left,frame=single,language=C++]{FILES_Prog/stubnets.cc}
+
+\lstinputlisting[title=Makefile,numbers=left,frame=single,language=make]{FILES_Prog/Makefile}
+
+\lstinputlisting[title=test.v,numbers=left,frame=single,language=Verilog]{FILES_Prog/test.v}
+
diff --git a/manual/FILES_Prog/Makefile b/manual/FILES_Prog/Makefile
index d7358188..1afde80f 100644
--- a/manual/FILES_Prog/Makefile
+++ b/manual/FILES_Prog/Makefile
@@ -1,14 +1,13 @@
-
test: stubnets.so
- yosys -q -l test1.log -m ./stubnets.so test.v -p "proc; stubnets"
- yosys -q -l test2.log -m ./stubnets.so test.v -p "proc; opt; stubnets"
- yosys -q -l test3.log -m ./stubnets.so test.v -p "proc; techmap; opt; stubnets -report_bits"
+ yosys -ql test1.log -m ./stubnets.so test.v -p "stubnets"
+ yosys -ql test2.log -m ./stubnets.so test.v -p "opt; stubnets"
+ yosys -ql test3.log -m ./stubnets.so test.v -p "techmap; opt; stubnets -report_bits"
tail test1.log test2.log test3.log
stubnets.so: stubnets.cc
- $(shell yosys-config --cxx --cxxflags --ldflags -o stubnets.so -shared stubnets.cc --ldlibs )
+ $(shell yosys-config --cxx --cxxflags --ldflags -o stubnets.so \
+ -shared stubnets.cc --ldlibs )
clean:
rm -f test1.log test2.log test3.log
rm -f stubnets.so stubnets.d
-
diff --git a/manual/FILES_Prog/stubnets.cc b/manual/FILES_Prog/stubnets.cc
index 00eab1b1..1c71f78b 100644
--- a/manual/FILES_Prog/stubnets.cc
+++ b/manual/FILES_Prog/stubnets.cc
@@ -67,7 +67,8 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// for each bit (unless it is a constant):
// check if it is used at least two times and add to stub_bits otherwise
for (size_t i = 0; i < sig.chunks.size(); i++)
- if (sig.chunks[i].wire != NULL && (bit_usage_count[sig.chunks[i]] + usage_offset) < 2)
+ if (sig.chunks[i].wire != NULL && (bit_usage_count[sig.chunks[i]] +
+ usage_offset) < 2)
stub_bits.insert(i);
// continue if no stub bits found