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authorClifford Wolf <clifford@clifford.at>2013-08-06 15:53:09 +0200
committerClifford Wolf <clifford@clifford.at>2013-08-06 15:53:09 +0200
commit653750faac4a2bf17440851c2ec7207a6a8ddcaa (patch)
tree85919f7407a2e4326f25282df4b49fdaac021084
parent6efca9ea5a64cd2440c9736c4db863e78d14b5c6 (diff)
Small bugfixes in freduce pass
-rw-r--r--passes/sat/freduce.cc18
1 files changed, 14 insertions, 4 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index 0416cd00..b822405f 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -28,7 +28,7 @@
#include <string.h>
#include <algorithm>
-#define NUM_INITIAL_RANDOM_TEST_VECTORS 3
+#define NUM_INITIAL_RANDOM_TEST_VECTORS 10
namespace {
@@ -141,8 +141,11 @@ struct FreduceHelper
restart:
std::map<RTLIL::Const, RTLIL::SigSpec> reverse_map;
- for (auto &it : node_to_data)
+ for (auto &it : node_to_data) {
+ if (node_result.count(it.first) && node_result.at(it.first).is_fully_const())
+ continue;
reverse_map[it.second].append(it.first);
+ }
for (auto &it : reverse_map)
{
@@ -295,8 +298,10 @@ struct FreduceHelper
continue;
for (auto &conn : cell->connections)
if (ct.cell_output(cell->type, conn.first)) {
- conn.second.expand();
- for (auto &c : conn.second.chunks) {
+ RTLIL::SigSpec sig = sigmap(conn.second);
+ sig.expand();
+ bool did_something = false;
+ for (auto &c : sig.chunks) {
if (c.wire == NULL || !groups_unlink.check_any(c))
continue;
c.wire = new RTLIL::Wire;
@@ -304,6 +309,11 @@ struct FreduceHelper
module->add(c.wire);
assert(c.width == 1);
c.offset = 0;
+ did_something = true;
+ }
+ if (did_something) {
+ sig.optimize();
+ conn.second = sig;
}
}
}