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authorClifford Wolf <clifford@clifford.at>2016-02-03 08:59:57 +0100
committerClifford Wolf <clifford@clifford.at>2016-02-03 08:59:57 +0100
commit6a27cbe5b17b012aef904bc31c13d8a2b0b15f01 (patch)
tree5c1abdc8d97299dcacf2c47226c6bd93ad14b3b4
parent4a3e1ded1e2dfd3d9a836aaed793978ddff6161b (diff)
Bugfix in Verific front-end
-rw-r--r--frontends/verific/verific.cc7
1 files changed, 5 insertions, 2 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 1ec6a7c0..d2440f69 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -773,8 +773,11 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
}
IdString port_name_id = RTLIL::escape_id(port_name);
auto &sigvec = cell_port_conns[port_name_id];
- if (GetSize(sigvec) <= port_offset)
- sigvec.resize(port_offset+1, State::Sz);
+ if (GetSize(sigvec) <= port_offset) {
+ SigSpec zwires = module->addWire(NEW_ID, port_offset+1-GetSize(sigvec));
+ for (auto bit : zwires)
+ sigvec.push_back(bit);
+ }
sigvec[port_offset] = net_map.at(pr->GetNet());
}