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authorClifford Wolf <clifford@clifford.at>2013-11-24 14:10:46 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-24 14:10:46 +0100
commit72b35e0b99381df7bda7fdd2811e67ae5cfad80a (patch)
tree85fc1e10c08d8edd5e76680106a3225a78d449c1
parent981677cf09226925c272e818b1a7f7f552da9299 (diff)
Fixed "flatten" top-module detection: Only use on fully selected designs
-rw-r--r--passes/techmap/techmap.cc7
1 files changed, 4 insertions, 3 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 7e3ba23e..4f9d9c4e 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -501,9 +501,10 @@ struct FlattenPass : public Pass {
celltypeMap[it.first].insert(it.first);
RTLIL::Module *top_mod = NULL;
- for (auto &mod_it : design->modules)
- if (mod_it.second->get_bool_attribute("\\top"))
- top_mod = mod_it.second;
+ if (design->full_selection())
+ for (auto &mod_it : design->modules)
+ if (mod_it.second->get_bool_attribute("\\top"))
+ top_mod = mod_it.second;
bool did_something = true;
std::set<RTLIL::Cell*> handled_cells;