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authorClifford Wolf <clifford@clifford.at>2014-07-16 11:38:02 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-16 11:38:02 +0200
commit73e0e13d2f1b959a05d69ed715c8fdde84894d6f (patch)
tree8a604b9990ca8e3ffd405b5e74a2d0e01141fb4b
parent964a67ac4194bb85fb3cb7a90a62dc1e4a685ea4 (diff)
Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
-rw-r--r--kernel/rtlil.cc4
-rw-r--r--manual/CHAPTER_CellLib.tex7
2 files changed, 6 insertions, 5 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 028cd6d8..c4c08d5b 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -619,7 +619,7 @@ namespace {
param_bool("\\CLK_POLARITY");
param("\\PRIORITY");
port("\\CLK", 1);
- port("\\EN", 1);
+ port("\\EN", param("\\WIDTH"));
port("\\ADDR", param("\\ABITS"));
port("\\DATA", param("\\WIDTH"));
check_expected();
@@ -639,7 +639,7 @@ namespace {
port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
port("\\WR_CLK", param("\\WR_PORTS"));
- port("\\WR_EN", param("\\WR_PORTS"));
+ port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
check_expected();
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index e7895521..f09c4929 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -256,8 +256,9 @@ If this parameter is set to {\tt 1'b1}, a read and write to the same address in
return the new value. Otherwise the old value is returned.
\end{itemize}
-The {\tt \$memwr} cells have a clock input \B{CLK}, an enable input \B{EN}, an address input \B{ADDR}
-and a data input \B{DATA}. They also have the following parameters:
+The {\tt \$memwr} cells have a clock input \B{CLK}, an enable input \B{EN} (one
+enable bit for each data bit), an address input \B{ADDR} and a data input
+\B{DATA}. They also have the following parameters:
\begin{itemize}
\item \B{MEMID} \\
@@ -341,7 +342,7 @@ This input is \B{RD\_PORTS}*\B{WIDTH} bits wide, containing all data signals for
This input is \B{WR\_PORTS} bits wide, containing all clock signals for the write ports.
\item \B{WR\_EN} \\
-This input is \B{WR\_PORTS} bits wide, containing all enable signals for the write ports.
+This input is \B{WR\_PORTS}*\B{WIDTH} bits wide, containing all enable signals for the write ports.
\item \B{WR\_ADDR} \\
This input is \B{WR\_PORTS}*\B{ABITS} bits wide, containing all address signals for the write ports.