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authorClifford Wolf <clifford@clifford.at>2015-04-29 19:55:32 +0200
committerClifford Wolf <clifford@clifford.at>2015-04-29 19:55:32 +0200
commit74626185910fb5da623645539b44d7173382dcc2 (patch)
tree76ac7d288f452f747ac77c7e21adab4057be656e
parent96be31de89bfcfb64d195dbdc0891bd507aec399 (diff)
Fixed memory_unpack for initialized memories
-rw-r--r--passes/memory/memory_unpack.cc17
1 files changed, 17 insertions, 0 deletions
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
index e650facb..0f8d5217 100644
--- a/passes/memory/memory_unpack.cc
+++ b/passes/memory/memory_unpack.cc
@@ -76,6 +76,23 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
cell->setPort("\\DATA", memory->getPort("\\WR_DATA").extract(i*mem->width, mem->width));
}
+ Const initval = memory->parameters.at("\\INIT");
+ for (int i = 0; i < GetSize(initval) && i/mem->width < (1 << abits); i += mem->width) {
+ Const val = initval.extract(i, mem->width, State::Sx);
+ for (auto bit : val.bits)
+ if (bit != State::Sx)
+ goto found_non_undef_initval;
+ continue;
+ found_non_undef_initval:
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$meminit");
+ cell->parameters["\\MEMID"] = mem_name.str();
+ cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
+ cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
+ cell->parameters["\\PRIORITY"] = i/mem->width;
+ cell->setPort("\\ADDR", SigSpec(i/mem->width, abits));
+ cell->setPort("\\DATA", val);
+ }
+
module->remove(memory);
}