Initialization support for all iCE40 bram modes

8 files changed, 65 insertions, 28 deletions

diff --git a/techlibs/ice40/.gitignore b/techlibs/ice40/.gitignore
new file mode 100644
index 00000000..6bf3b671
--- /dev/null
+++ b/techlibs/ice40/.gitignore
@@ -0,0 +1,4 @@
+brams_init.mk
+brams_init1.vh
+brams_init2.vh
+brams_init3.vh
diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 14ef4e7d..0dc0c844 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -2,9 +2,27 @@
 OBJS += techlibs/ice40/synth_ice40.o
 OBJS += techlibs/ice40/ice40_ffssr.o
 
+GENFILES += techlibs/ice40/brams_init1.vh
+GENFILES += techlibs/ice40/brams_init2.vh
+GENFILES += techlibs/ice40/brams_init3.vh
+
+EXTRA_OBJS += techlibs/ice40/brams_init.mk
+.SECONDARY: techlibs/ice40/brams_init.mk
+
+techlibs/ice40/brams_init.mk: techlibs/ice40/brams_init.py
+	cd techlibs/ice40 && python brams_init.py
+	touch techlibs/ice40/brams_init.mk
+
+techlibs/ice40/brams_init1.vh: techlibs/ice40/brams_init.mk
+techlibs/ice40/brams_init2.vh: techlibs/ice40/brams_init.mk
+techlibs/ice40/brams_init3.vh: techlibs/ice40/brams_init.mk
+
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/arith_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_init3.vh))
 
diff --git a/techlibs/ice40/brams.txt b/techlibs/ice40/brams.txt
index 6d227d03..e025b368 100644
--- a/techlibs/ice40/brams.txt
+++ b/techlibs/ice40/brams.txt
@@ -12,7 +12,7 @@ bram $__ICE40_RAM4K_M0
 endbram
 
 bram $__ICE40_RAM4K_M123
-  init 0
+  init 1
   abits  9 @M1
   dbits  8 @M1
   abits 10 @M2
diff --git a/techlibs/ice40/brams_init.py b/techlibs/ice40/brams_init.py
new file mode 100644
index 00000000..b99a2f3c
--- /dev/null
+++ b/techlibs/ice40/brams_init.py
@@ -0,0 +1,17 @@
+#!/usr/bin/python
+
+from __future__ import division
+from __future__ import print_function
+
+def write_init_vh(filename, initbits):
+    with open(filename, "w") as f:
+        for i in range(16):
+            print("localparam [255:0] INIT_%X = {" % i, file=f)
+            for k in range(32):
+                print("  %s%s" % (", ".join(["INIT[%4d]" % initbits[i*256 + 255 - k*8 - l] for l in range(8)]), "," if k != 31 else ""), file=f)
+            print("};", file=f);
+
+write_init_vh("brams_init1.vh", [i//2 + 2048*(i%2) for i in range(4096)])
+write_init_vh("brams_init2.vh", [i//4 + 1024*(i%4) for i in range(4096)])
+write_init_vh("brams_init3.vh", [i//8 +  512*(i%8) for i in range(4096)])
+
diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v
index d6ebb249..8c5c7e81 100644
--- a/techlibs/ice40/brams_map.v
+++ b/techlibs/ice40/brams_map.v
@@ -230,6 +230,8 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 	parameter [0:0] CLKPOL2 = 1;
 	parameter [0:0] CLKPOL3 = 1;
 
+	parameter [4095:0] INIT = 4096'bx;
+
 	localparam MODE =
 		CFG_ABITS ==  9 ? 1 :
 		CFG_ABITS == 10 ? 2 :
@@ -256,14 +258,17 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 			                 A1DATA_16[ 6], A1DATA_16[ 4], A1DATA_16[ 2], A1DATA_16[ 0]};
 			assign {B1DATA_16[14], B1DATA_16[12], B1DATA_16[10], B1DATA_16[ 8],
 			        B1DATA_16[ 6], B1DATA_16[ 4], B1DATA_16[ 2], B1DATA_16[ 0]} = B1DATA;
+			`include "brams_init1.vh"
 		end
 		if (MODE == 2) begin
 			assign A1DATA = {A1DATA_16[13], A1DATA_16[9], A1DATA_16[5], A1DATA_16[1]};
 			assign {B1DATA_16[13], B1DATA_16[9], B1DATA_16[5], B1DATA_16[1]} = B1DATA;
+			`include "brams_init2.vh"
 		end
 		if (MODE == 3) begin
 			assign A1DATA = {A1DATA_16[11], A1DATA_16[3]};
 			assign {B1DATA_16[11], B1DATA_16[3]} = B1DATA;
+			`include "brams_init3.vh"
 		end
 	endgenerate
 
@@ -272,22 +277,22 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 		.WRITE_MODE(MODE),
 		.NEGCLK_R(!CLKPOL2),
 		.NEGCLK_W(!CLKPOL3),
-		// .INIT_0(INIT[ 0*256 +: 256]),
-		// .INIT_1(INIT[ 1*256 +: 256]),
-		// .INIT_2(INIT[ 2*256 +: 256]),
-		// .INIT_3(INIT[ 3*256 +: 256]),
-		// .INIT_4(INIT[ 4*256 +: 256]),
-		// .INIT_5(INIT[ 5*256 +: 256]),
-		// .INIT_6(INIT[ 6*256 +: 256]),
-		// .INIT_7(INIT[ 7*256 +: 256]),
-		// .INIT_8(INIT[ 8*256 +: 256]),
-		// .INIT_9(INIT[ 9*256 +: 256]),
-		// .INIT_A(INIT[10*256 +: 256]),
-		// .INIT_B(INIT[11*256 +: 256]),
-		// .INIT_C(INIT[12*256 +: 256]),
-		// .INIT_D(INIT[13*256 +: 256]),
-		// .INIT_E(INIT[14*256 +: 256]),
-		// .INIT_F(INIT[15*256 +: 256])
+		.INIT_0(INIT_0),
+		.INIT_1(INIT_1),
+		.INIT_2(INIT_2),
+		.INIT_3(INIT_3),
+		.INIT_4(INIT_4),
+		.INIT_5(INIT_5),
+		.INIT_6(INIT_6),
+		.INIT_7(INIT_7),
+		.INIT_8(INIT_8),
+		.INIT_9(INIT_9),
+		.INIT_A(INIT_A),
+		.INIT_B(INIT_B),
+		.INIT_C(INIT_C),
+		.INIT_D(INIT_D),
+		.INIT_E(INIT_E),
+		.INIT_F(INIT_F)
 	) _TECHMAP_REPLACE_ (
 		.RDATA(A1DATA_16),
 		.RADDR(A1ADDR_11),
diff --git a/techlibs/ice40/tests/test_bram.sh b/techlibs/ice40/tests/test_bram.sh
index 73d889ce..d4d641a9 100644
--- a/techlibs/ice40/tests/test_bram.sh
+++ b/techlibs/ice40/tests/test_bram.sh
@@ -5,13 +5,8 @@ set -ex
 for abits in 7 8 9 10 11 12; do
 for dbits in 2 4 8 16 24 32; do
 	id="test_bram_${abits}_${dbits}"
-	if [ $((RANDOM % 2)) -eq 0 ]; then
-		iadr=0
-		idat=0
-	else
-		iadr=$((RANDOM % (1 << abits)))
-		idat=$((RANDOM % (1 << dbits)))
-	fi
+	iadr=$((RANDOM % (1 << abits)))
+	idat=$((RANDOM % ((1 << dbits) - 1) + 1))
 	sed -re "s/(ABITS = )0/\1$abits/g; s/(DBITS = )0/\1$dbits/g; s/(INIT_ADDR = )0/\1$iadr/g; s/(INIT_DATA = )0/\1$idat/g;" < test_bram.v > ${id}.v
 	sed -re "s/(ABITS = )0/\1$abits/g; s/(DBITS = )0/\1$dbits/g; s/(INIT_ADDR = )0/\1$iadr/g; s/(INIT_DATA = )0/\1$idat/g;" < test_bram_tb.v > ${id}_tb.v
 	../../../yosys -ql ${id}_syn.log -p "synth_ice40" -o ${id}_syn.v ${id}.v
diff --git a/techlibs/ice40/tests/test_bram.v b/techlibs/ice40/tests/test_bram.v
index a625b6b6..320735d0 100644
--- a/techlibs/ice40/tests/test_bram.v
+++ b/techlibs/ice40/tests/test_bram.v
@@ -14,8 +14,7 @@ module bram #(
 	reg [DBITS-1:0] memory [0:2**ABITS-1];
 
 	initial begin
-		if (INIT_ADDR || INIT_DATA)
-			memory[INIT_ADDR] <= INIT_DATA;
+		memory[INIT_ADDR] <= INIT_DATA;
 	end
 
 	always @(posedge clk) begin
diff --git a/techlibs/ice40/tests/test_bram_tb.v b/techlibs/ice40/tests/test_bram_tb.v
index abf95305..bdb8d456 100644
--- a/techlibs/ice40/tests/test_bram_tb.v
+++ b/techlibs/ice40/tests/test_bram_tb.v
@@ -64,8 +64,7 @@ module bram_tb #(
 		// $dumpfile("testbench.vcd");
 		// $dumpvars(0, bram_tb);
 
-		if (INIT_ADDR || INIT_DATA)
-			memory[INIT_ADDR] <= INIT_DATA;
+		memory[INIT_ADDR] <= INIT_DATA;
 
 		xorshift64_next;
 		xorshift64_next;