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authorClifford Wolf <clifford@clifford.at>2014-09-14 16:09:06 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-14 16:09:06 +0200
commit7815f81c320a025c5b92677e375c12951dcbd14b (patch)
treef5a09485b53fd3c5f6c0b54e2d1e0bb15dbe6301
parent7e156a541909ec857fbaa4a08940d0aaf0d27d4b (diff)
Added "synth" command
-rw-r--r--Makefile1
-rw-r--r--README21
-rw-r--r--kernel/driver.cc14
-rw-r--r--techlibs/common/Makefile.inc2
-rw-r--r--techlibs/common/synth.cc152
-rwxr-xr-xtests/tools/autotest.sh4
6 files changed, 174 insertions, 20 deletions
diff --git a/Makefile b/Makefile
index 3ec89916..7e8c7042 100644
--- a/Makefile
+++ b/Makefile
@@ -111,6 +111,7 @@ LDFLAGS += -pg
endif
ifeq ($(ENABLE_ABC),1)
+CXXFLAGS += -DYOSYS_ENABLE_ABC
TARGETS += yosys-abc
endif
diff --git a/README b/README
index 7e8a42a8..d7f5aaa4 100644
--- a/README
+++ b/README
@@ -199,6 +199,19 @@ Various more complex liberty files (for testing) can be found here:
../cadence/lib/tsmc018/signalstorm/osu018_stdcells.lib
../cadence/lib/ami05/signalstorm/osu05_stdcells.lib
+The command "synth" provides a good default synthesis script (see "help synth").
+If possible a synthesis script should borrow from "synth". For example:
+
+ # the high-level stuff
+ hierarchy
+ synth -run coarse
+
+ # mapping to internal cells
+ techmap; opt -fast
+ dfflibmap -liberty mycells.lib
+ abc -liberty mycells.lib
+ clean
+
Yosys is under construction. A more detailed documentation will follow.
@@ -351,12 +364,7 @@ from SystemVerilog:
Roadmap / Large-scale TODOs
===========================
-- Verification and Regression Tests
- - VlogHammer: http://www.clifford.at/yosys/vloghammer.html
- - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim
-
- Technology mapping for real-world applications
- - Rewrite current techmap.v rules (modular and clean)
- Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.)
- Implement SAT-based formal equivialence checker
@@ -382,7 +390,4 @@ Other Unsorted TODOs
- Add brief source code documentation to most passes and kernel code
- Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees
- - Add more commands for changing the design (delete, add, modify objects)
- - Add full support for $lut cell type (const evaluation, sat solving, etc.)
- - Smarter resource sharing pass (add MUXes and get rid of duplicated cells)
diff --git a/kernel/driver.cc b/kernel/driver.cc
index e778e138..f26d9ef8 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -76,13 +76,7 @@ int main(int argc, char **argv)
printf("%s\n", yosys_version_str);
exit(0);
case 'S':
- passes_commands.push_back("hierarchy");
- passes_commands.push_back("proc");
- passes_commands.push_back("opt");
- passes_commands.push_back("memory");
- passes_commands.push_back("opt");
- passes_commands.push_back("techmap");
- passes_commands.push_back("opt");
+ passes_commands.push_back("synth");
break;
case 'm':
plugin_filenames.push_back(optarg);
@@ -187,10 +181,10 @@ int main(int argc, char **argv)
fprintf(stderr, " -V\n");
fprintf(stderr, " print version information and exit\n");
fprintf(stderr, "\n");
- fprintf(stderr, "The option -S is an alias for the following options that perform a simple\n");
- fprintf(stderr, "transformation of the input to a gate-level netlist.\n");
+ fprintf(stderr, "The option -S is an shortcut for calling the \"synth\" command, a default\n");
+ fprintf(stderr, "script for transforming the verilog input to a gate-level netlist. For example:\n");
fprintf(stderr, "\n");
- fprintf(stderr, " -p hierarchy -p proc -p opt -p memory -p opt -p techmap -p opt\n");
+ fprintf(stderr, " yosys -o output.blif -S input.v\n");
fprintf(stderr, "\n");
fprintf(stderr, "For more complex synthesis jobs it is recommended to use the read_* and write_*\n");
fprintf(stderr, "commands in a script file instead of specifying input and output files on the\n");
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index 461c1cb4..7c8cc2f6 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -1,4 +1,6 @@
+OBJS += techlibs/common/synth.o
+
EXTRA_TARGETS += techlibs/common/blackbox.v
techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.v techlibs/common/simcells.v
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
new file mode 100644
index 00000000..95221afa
--- /dev/null
+++ b/techlibs/common/synth.cc
@@ -0,0 +1,152 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+static bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
+{
+ if (!run_from.empty() && run_from == run_to) {
+ active = (label == run_from);
+ } else {
+ if (label == run_from)
+ active = true;
+ if (label == run_to)
+ active = false;
+ }
+ return active;
+}
+
+struct SynthPass : public Pass {
+ SynthPass() : Pass("synth", "generic synthesis script") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" synth [options]\n");
+ log("\n");
+ log("This command runs the default synthesis script. This command does not operate\n");
+ log("on partly selected designs.\n");
+ log("\n");
+ log(" -top <module>\n");
+ log(" use the specified module as top module (default='top')\n");
+ log("\n");
+ log(" -run <from_label>[:<to_label>]\n");
+ log(" only run the commands between the labels (see below). an empty\n");
+ log(" from label is synonymous to 'begin', and empty to label is\n");
+ log(" synonymous to the end of the command list.\n");
+ log("\n");
+ log("\n");
+ log("The following commands are executed by this synthesis command:\n");
+ log("\n");
+ log(" begin:\n");
+ log(" hierarchy -check [-top <top>]\n");
+ log("\n");
+ log(" coarse:\n");
+ log(" proc\n");
+ log(" opt\n");
+ log(" wreduce\n");
+ log(" alumacc\n");
+ log(" share\n");
+ log(" opt -fast\n");
+ log(" fsm\n");
+ log(" opt -fast\n");
+ log(" memory\n");
+ log("\n");
+ log(" fine:\n");
+ log(" techmap\n");
+ log(" opt -fast\n");
+ #ifdef YOSYS_ENABLE_ABC
+ log(" abc\n");
+ #endif
+ log(" clean\n");
+ log("\n");
+ }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ {
+ std::string top_module;
+ std::string run_from, run_to;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-top" && argidx+1 < args.size()) {
+ top_module = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-run" && argidx+1 < args.size()) {
+ size_t pos = args[argidx+1].find(':');
+ if (pos == std::string::npos) {
+ run_from = args[++argidx];
+ run_to = args[argidx];
+ } else {
+ run_from = args[++argidx].substr(0, pos);
+ run_to = args[argidx].substr(pos+1);
+ }
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if (!design->full_selection())
+ log_cmd_error("This comannd only operates on fully selected designs!\n");
+
+ bool active = run_from.empty();
+
+ log_header("Executing SYNTH pass.\n");
+ log_push();
+
+ if (check_label(active, run_from, run_to, "begin"))
+ {
+ if (top_module.empty())
+ Pass::call(design, stringf("hierarchy -check"));
+ else
+ Pass::call(design, stringf("hierarchy -check -top %s", top_module.c_str()));
+ }
+
+ if (check_label(active, run_from, run_to, "coarse"))
+ {
+ Pass::call(design, "proc");
+ Pass::call(design, "opt");
+ Pass::call(design, "wreduce");
+ Pass::call(design, "alumacc");
+ Pass::call(design, "share");
+ Pass::call(design, "opt -fast");
+ Pass::call(design, "fsm");
+ Pass::call(design, "opt -fast");
+ Pass::call(design, "memory");
+ }
+
+ if (check_label(active, run_from, run_to, "fine"))
+ {
+ Pass::call(design, "techmap");
+ Pass::call(design, "opt -fast");
+ #ifdef YOSYS_ENABLE_ABC
+ Pass::call(design, "abc");
+ #endif
+ Pass::call(design, "clean");
+ }
+
+ log_pop();
+ }
+} SynthPass;
+
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 102c021e..50f5cb58 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -145,8 +145,8 @@ do
elif [ "$frontend" = "verific_gates" ]; then
test_passes -p "verific -vlog2k $fn; verific -import -gates -all; opt; memory;;"
else
- test_passes -f "$frontend" -p "hierarchy; proc; opt_const; opt_share;; wreduce;; share;; opt; memory -nomap;; fsm; opt" $fn
- test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt -fine; techmap; opt; abc -dff; opt" $fn
+ test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt -fine" $fn
+ test_passes -f "$frontend" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" $fn
fi
touch ../${bn}.log
}