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authorClifford Wolf <clifford@clifford.at>2014-07-26 14:38:33 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 15:58:21 +0200
commit7ac9dc7f6eab40b3853583848933c4a8a94df9c9 (patch)
treebf27c3ea022ca9b9d06a5a9dc2c6b6d336fa6631
parentb03aec6e3212a387e3d255583476d472d16663f1 (diff)
Added RTLIL::Module::connections()
-rw-r--r--kernel/rtlil.cc5
-rw-r--r--kernel/rtlil.h1
2 files changed, 6 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index ce4ecea6..1638682c 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -883,6 +883,11 @@ void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs
connections_.push_back(RTLIL::SigSig(lhs, rhs));
}
+const std::vector<RTLIL::SigSig> &RTLIL::Module::connections()
+{
+ return connections_;
+}
+
void RTLIL::Module::fixup_ports()
{
std::vector<RTLIL::Wire*> all_ports;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 4f91b720..1775975d 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -290,6 +290,7 @@ struct RTLIL::Module
void connect(const RTLIL::SigSig &conn);
void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
+ const std::vector<RTLIL::SigSig> &connections();
void fixup_ports();
template<typename T> void rewrite_sigspecs(T functor);