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authorClifford Wolf <clifford@clifford.at>2014-12-08 10:56:43 +0100
committerClifford Wolf <clifford@clifford.at>2014-12-08 10:56:43 +0100
commit7b62bbeee824f1ff6d483247f5613e597b8c854f (patch)
treefb81b36ba248facc689337c2211e95ddd225243b
parentf1764b4fe99807c445526774563a98224b642766 (diff)
Added more documentation fixmes for nontrivial register cells
-rw-r--r--manual/CHAPTER_CellLib.tex10
1 files changed, 9 insertions, 1 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 64d3633e..c12d8734 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -357,7 +357,7 @@ Add a brief description of the {\tt \$fsm} cell type.
For gate level logic networks, fixed function single bit cells are used that do
not provide any parameters.
-Simulation models for these cells can be found in the file {\tt techlibs/common/stdcells\_sim.v} in the Yosys
+Simulation models for these cells can be found in the file {\tt techlibs/common/simcells.v} in the Yosys
source tree.
\begin{table}[t]
@@ -429,6 +429,14 @@ Add information about {\tt \$alu}, {\tt \$macc}, {\tt \$fa}, and {\tt \$lcu} cel
\end{fixme}
\begin{fixme}
+Add information about {\tt \$dffe}, {\tt \$dffsr}, {\tt \$dlatch}, and {\tt \$dlatchsr} cells.
+\end{fixme}
+
+\begin{fixme}
+Add information about {\tt \$\_DFFE\_??\_}, {\tt \$\_DFFSR\_???\_}, {\tt \$\_DLATCH\_?\_}, and {\tt \$\_DLATCHSR\_???\_} cells.
+\end{fixme}
+
+\begin{fixme}
Add information about {\tt \$\_NAND\_}, {\tt \$\_NOR\_}, {\tt \$\_XNOR\_}, {\tt \$\_AOI3\_}, {\tt \$\_OAI3\_}, {\tt \$\_AOI4\_}, and {\tt \$\_OAI4\_} cells.
\end{fixme}