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authorClifford Wolf <clifford@clifford.at>2015-01-06 17:21:18 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-06 17:21:18 +0100
commit7cc5192125244d3fd990f3043d619262066ff962 (patch)
tree911b2f175c0f9c6edc7c3fbe351d8b1c2e9f6626
parent07703bdac40f5b7807b627d289e67897bf2b7396 (diff)
small fix in xilinx/brams.v
-rw-r--r--techlibs/xilinx/brams.v10
1 files changed, 5 insertions, 5 deletions
diff --git a/techlibs/xilinx/brams.v b/techlibs/xilinx/brams.v
index a5d2b59c..a0baeaf0 100644
--- a/techlibs/xilinx/brams.v
+++ b/techlibs/xilinx/brams.v
@@ -97,8 +97,8 @@ module \$__XILINX_RAMB18_SDP36 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
input [35:0] B1DATA;
input [3:0] B1EN;
- wire [15:0] A1ADDR_16 = {A1ADDR, 5'b0};
- wire [15:0] B1ADDR_16 = {B1ADDR, 5'b0};
+ wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0};
+ wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0};
wire [3:0] DIP, DOP;
wire [31:0] DI, DO;
@@ -139,15 +139,15 @@ module \$__XILINX_RAMB18_SDP36 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
.DIPBDIP(DIP[3:2]),
.DIPADIP(DIP[1:0]),
- .ADDRARDADDR(A1ADDR_16),
+ .ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
.ENARDEN(|1),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
- .WEA(4'b0),
+ .WEA(2'b0),
- .ADDRBWRADDR(B1ADDR_16),
+ .ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
.ENBWREN(|1),
.REGCEB(|0),