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authorClifford Wolf <clifford@clifford.at>2014-08-16 23:50:36 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-16 23:50:36 +0200
commit7f734ecc098a2a113ced835cefc9d4e1982f08d0 (patch)
tree0e73ad74bd4602da7a6a1a3b264e1842deccac18
parentf82c978e08604c596b034fb6e74ac34c78b9364b (diff)
Added module->uniquify()
-rw-r--r--frontends/verific/verific.cc8
-rw-r--r--kernel/rtlil.cc22
-rw-r--r--kernel/rtlil.h3
-rw-r--r--passes/cmds/splitnets.cc5
-rw-r--r--passes/fsm/fsm_map.cc6
5 files changed, 29 insertions, 15 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 95b3c407..0440f88e 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -603,9 +603,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
// log(" importing net %s.\n", net->Name());
- std::string wire_name = RTLIL::escape_id(net->Name());
- while (module->count_id(wire_name))
- wire_name += "_";
+ RTLIL::IdString wire_name = module->uniquify(RTLIL::escape_id(net->Name()));
RTLIL::Wire *wire = module->addWire(wire_name);
import_attributes(wire->attributes, net);
@@ -627,9 +625,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
{
// log(" importing netbus %s.\n", netbus->Name());
- std::string wire_name = RTLIL::escape_id(netbus->Name());
- while (module->count_id(wire_name))
- wire_name += "_";
+ RTLIL::IdString wire_name = module->uniquify(RTLIL::escape_id(netbus->Name()));
RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
wire->start_offset = std::min(netbus->LeftIndex(), netbus->RightIndex());
import_attributes(wire->attributes, netbus);
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 3df7d83c..60c514d1 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1108,6 +1108,28 @@ void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
cells_[c2->name] = c2;
}
+RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
+{
+ int index = 0;
+ return uniquify(name, index);
+}
+
+RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
+{
+ if (index == 0) {
+ if (count_id(name) == 0)
+ return name;
+ index++;
+ }
+
+ while (1) {
+ RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
+ if (count_id(new_name) == 0)
+ return new_name;
+ index++;
+ }
+}
+
static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
{
if (a->port_id && !b->port_id)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 43e36cbd..7e052b09 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -625,6 +625,9 @@ public:
void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);
void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);
+ RTLIL::IdString uniquify(RTLIL::IdString name);
+ RTLIL::IdString uniquify(RTLIL::IdString name, int &index);
+
RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index a3daf239..cef0a272 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -46,10 +46,7 @@ struct SplitnetsWorker
if (format.size() > 1)
new_wire_name += format.substr(1, 1);
- while (module->count_id(new_wire_name) > 0)
- new_wire_name += "_";
-
- RTLIL::Wire *new_wire = module->addWire(new_wire_name, width);
+ RTLIL::Wire *new_wire = module->addWire(module->uniquify(new_wire_name), width);
new_wire->port_id = wire->port_id;
new_wire->port_input = wire->port_input;
new_wire->port_output = wire->port_output;
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
index 60580eb4..ab6d5671 100644
--- a/passes/fsm/fsm_map.cc
+++ b/passes/fsm/fsm_map.cc
@@ -163,11 +163,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
// create state register
- std::string state_wire_name = fsm_cell->parameters["\\NAME"].decode_string();
- while (module->count_id(state_wire_name) > 0)
- state_wire_name += "_";
-
- RTLIL::Wire *state_wire = module->addWire(state_wire_name, fsm_data.state_bits);
+ RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters["\\NAME"].decode_string()), fsm_data.state_bits);
RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");