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authorClifford Wolf <clifford@clifford.at>2015-01-13 13:20:09 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-13 13:20:09 +0100
commit8426884b4052deeebf25b80d105adf1c2a5a5698 (patch)
tree0259843335a58de96b7265854e0575a6f89e599e
parentdfa42e272cd13a08314299817423052488eb58ab (diff)
Re-enabled mux->and/or transform (and fixed lm32 in yosys-bigsim)
-rw-r--r--passes/opt/opt_const.cc5
1 files changed, 0 insertions, 5 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 5d557b98..6a830dd0 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -681,10 +681,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
goto next_cell;
}
- #if 0
- // disabled because replacing muxes with and/or gates sometimes causes probems with
- // simulating undefs (e.g. lm32 from yosys-bigsim vs. icarus verilog init problems)
-
if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1)) {
cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type.str());
log("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
@@ -724,7 +720,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
did_something = true;
goto next_cell;
}
- #endif
if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) {
RTLIL::SigSpec new_a, new_b, new_s;