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authorClifford Wolf <clifford@clifford.at>2013-11-21 03:01:20 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-21 03:01:20 +0100
commit84ced2bb8ee2e6498b53ae6cdb77930aa98affbb (patch)
tree7096e1bc1d2756700fd40c88346ad17c779b54a8
parent64a5f8f75e99eb9970b69f2d7165c014a57c29cf (diff)
Fixed a bug in "add -global_input"
-rw-r--r--passes/cmds/add.cc33
1 files changed, 17 insertions, 16 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index 8e478355..12706c4f 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -23,12 +23,11 @@
static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
{
+ RTLIL::Wire *wire = NULL;
name = RTLIL::escape_id(name);
if (module->count_id(name) != 0)
{
- RTLIL::Wire *wire = NULL;
-
if (module->wires.count(name) > 0)
wire = module->wires.at(name);
@@ -43,23 +42,25 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
if (wire == NULL)
log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str());
- log("Skipping module %s as it already has such an object.\n", module->name.c_str());
- return;
- }
-
- RTLIL::Wire *wire = new RTLIL::Wire;
- wire->name = name;
- wire->width = width;
- wire->port_input = flag_input;
- wire->port_output = flag_output;
- module->add(wire);
- if (flag_input || flag_output) {
- wire->port_id = module->wires.size();
- module->fixup_ports();
+ log("Module %s already has such an object.\n", module->name.c_str());
}
+ else
+ {
+ wire = new RTLIL::Wire;
+ wire->name = name;
+ wire->width = width;
+ wire->port_input = flag_input;
+ wire->port_output = flag_output;
+ module->add(wire);
+
+ if (flag_input || flag_output) {
+ wire->port_id = module->wires.size();
+ module->fixup_ports();
+ }
- log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
+ log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
+ }
if (!flag_global)
return;