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authorClifford Wolf <clifford@clifford.at>2014-02-08 14:21:04 +0100
committerClifford Wolf <clifford@clifford.at>2014-02-08 14:21:04 +0100
commit922d1c9520ec1863b932cd7910be86029726ae95 (patch)
tree93aa1a702a9526a4330e257ad081836325374ff6
parent669a6e462dde005c5c6474bccf9a433340666661 (diff)
Only count non-trivial attributes when findinf master signal in opt_clean
-rw-r--r--passes/opt/opt_clean.cc15
1 files changed, 13 insertions, 2 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 740185cb..733a1cbf 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -96,6 +96,14 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
}
}
+static int count_nontrivial_wire_attrs(RTLIL::Wire *w)
+{
+ int count = w->attributes.size();
+ count -= w->attributes.count("\\src");
+ count -= w->attributes.count("\\unused_bits");
+ return count;
+}
+
static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2, SigPool &regs, SigPool &conns, std::set<RTLIL::Wire*> &direct_wires)
{
assert(s1.width == 1);
@@ -127,8 +135,11 @@ static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2, SigPool &reg
if (w1->name[0] != w2->name[0])
return w2->name[0] == '\\';
- if (w1->attributes.size() != w2->attributes.size())
- return w2->attributes.size() > w1->attributes.size();
+ int attrs1 = count_nontrivial_wire_attrs(w1);
+ int attrs2 = count_nontrivial_wire_attrs(w2);
+
+ if (attrs1 != attrs2)
+ return attrs2 > attrs1;
return w2->name < w1->name;
}