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authorClifford Wolf <clifford@clifford.at>2014-09-06 20:30:46 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-06 20:30:46 +0200
commit9329a768181d3765a08c3b264c8b0031b732c0d4 (patch)
tree092793d2517d97851d50307f8777aead6924173d
parent98e6463ca78d8c0a342c9b86d9223dbeb45c093c (diff)
Various bug fixes (related to $macc model testing)
-rw-r--r--backends/verilog/verilog_backend.cc3
-rw-r--r--passes/tests/test_cell.cc2
-rw-r--r--techlibs/common/simlib.v2
-rw-r--r--techlibs/common/techmap.v2
4 files changed, 5 insertions, 4 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 82a2c519..bbdbbbfa 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -973,7 +973,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
for (int i = 0; i < wire->width; i++)
if (reg_bits.count(std::pair<RTLIL::Wire*,int>(wire, i)) == 0)
goto this_wire_aint_reg;
- reg_wires.insert(wire->name);
+ if (wire->width)
+ reg_wires.insert(wire->name);
this_wire_aint_reg:;
}
}
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index edab51eb..c69bd123 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -262,7 +262,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, std::string uut_n
gold_ce.set(gold_wire, in_value);
gate_ce.set(gate_wire, in_value);
- if (vlog_file.is_open()) {
+ if (vlog_file.is_open() && SIZE(in_value) > 0) {
vlog_file << stringf(" %s = 'b%s;\n", log_id(gold_wire), in_value.as_string().c_str());
if (!vlog_pattern_info.empty())
vlog_pattern_info += " ";
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index b1f871d9..465efc0a 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -768,7 +768,7 @@ module \$macc (A, B, Y);
localparam integer num_bits = CONFIG[3:0];
localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);
- localparam integer num_abits = $clog2(A_WIDTH);
+ localparam integer num_abits = $clog2(A_WIDTH) > 0 ? $clog2(A_WIDTH) : 1;
function [2*num_ports*num_abits-1:0] get_port_offsets;
input [CONFIG_WIDTH-1:0] cfg;
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index f0397858..3fc6ccb8 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -594,7 +594,7 @@ module \$macc (A, B, Y);
localparam integer num_bits = CONFIG[3:0];
localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);
- localparam integer num_abits = $clog2(A_WIDTH);
+ localparam integer num_abits = $clog2(A_WIDTH) > 0 ? $clog2(A_WIDTH) : 1;
function [2*num_ports*num_abits-1:0] get_port_offsets;
input [CONFIG_WIDTH-1:0] cfg;