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authorClifford Wolf <clifford@clifford.at>2014-08-14 23:14:47 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-14 23:14:47 +0200
commit978a933b6af8863200096bd3a56780e3378e4848 (patch)
treeb6f2dbb89c50c3f6c35098aa8ecff4c20675a52f
parentc83b9904582b81e71c4c510ffdc26f9796f5da21 (diff)
Added RTLIL::SigSpec::to_sigbit_map()
-rw-r--r--frontends/ast/genrtlil.cc14
-rw-r--r--kernel/rtlil.cc16
-rw-r--r--kernel/rtlil.h1
3 files changed, 20 insertions, 11 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 24251486..3c8f1fa1 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -400,10 +400,7 @@ struct AST_INTERNAL::ProcessGenerator
case AST_ASSIGN_EQ:
case AST_ASSIGN_LE:
{
- std::map<RTLIL::SigBit, RTLIL::SigBit> new_subst_rvalue_map;
- for (int i = 0; i < SIZE(subst_rvalue_to); i++)
- new_subst_rvalue_map[subst_rvalue_from[i]] = subst_rvalue_to[i];
-
+ std::map<RTLIL::SigBit, RTLIL::SigBit> new_subst_rvalue_map = subst_rvalue_from.to_sigbit_map(subst_rvalue_to);
RTLIL::SigSpec unmapped_lvalue = ast->children[0]->genRTLIL(), lvalue = unmapped_lvalue;
RTLIL::SigSpec rvalue = ast->children[1]->genWidthRTLIL(lvalue.size(), &new_subst_rvalue_map);
lvalue.replace(subst_lvalue_from, subst_lvalue_to);
@@ -421,10 +418,7 @@ struct AST_INTERNAL::ProcessGenerator
case AST_CASE:
{
- std::map<RTLIL::SigBit, RTLIL::SigBit> new_subst_rvalue_map;
- for (int i = 0; i < SIZE(subst_rvalue_to); i++)
- new_subst_rvalue_map[subst_rvalue_from[i]] = subst_rvalue_to[i];
-
+ std::map<RTLIL::SigBit, RTLIL::SigBit> new_subst_rvalue_map = subst_rvalue_from.to_sigbit_map(subst_rvalue_to);
RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
sw->signal = ast->children[0]->genWidthRTLIL(-1, &new_subst_rvalue_map);
current_case->switches.push_back(sw);
@@ -478,9 +472,7 @@ struct AST_INTERNAL::ProcessGenerator
else if (node->type == AST_BLOCK)
processAst(node);
else {
- std::map<RTLIL::SigBit, RTLIL::SigBit> new_subst_rvalue_map;
- for (int i = 0; i < SIZE(subst_rvalue_to); i++)
- new_subst_rvalue_map[subst_rvalue_from[i]] = subst_rvalue_to[i];
+ std::map<RTLIL::SigBit, RTLIL::SigBit> new_subst_rvalue_map = subst_rvalue_from.to_sigbit_map(subst_rvalue_to);
current_case->compare.push_back(node->genWidthRTLIL(sw->signal.size(), &new_subst_rvalue_map));
}
}
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 297537f0..f4f32f60 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2687,6 +2687,22 @@ std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const
return bits_;
}
+std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const
+{
+ cover("kernel.rtlil.sigspec.to_sigbit_map");
+
+ unpack();
+ other.unpack();
+
+ log_assert(width_ == other.width_);
+
+ std::map<RTLIL::SigBit, RTLIL::SigBit> new_map;
+ for (int i = 0; i < width_; i++)
+ new_map[bits_[i]] = other.bits_[i];
+
+ return new_map;
+}
+
RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
{
cover("kernel.rtlil.sigspec.to_single_sigbit");
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 8f780c82..3a0f0ff8 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1020,6 +1020,7 @@ public:
std::set<RTLIL::SigBit> to_sigbit_set() const;
std::vector<RTLIL::SigBit> to_sigbit_vector() const;
+ std::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;
RTLIL::SigBit to_single_sigbit() const;
static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);