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authorClifford Wolf <clifford@clifford.at>2014-08-01 15:25:42 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-01 15:25:42 +0200
commit97a17d39e2f0088e02ed8496d905528722115674 (patch)
tree8929691e146e0ab75829ef50e1d585861a06db06
parent5e641acc905a5c99d037378f6b7a481c43eb7de0 (diff)
Packed SigBit::data and SigBit::offset in a union
-rw-r--r--kernel/rtlil.cc4
-rw-r--r--kernel/rtlil.h20
2 files changed, 14 insertions, 10 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 01225314..79ddd2e0 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1681,9 +1681,11 @@ RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
{
wire = bit.wire;
+ offset = 0;
if (wire == NULL)
data = RTLIL::Const(bit.data);
- offset = bit.offset;
+ else
+ offset = bit.offset;
width = 1;
}
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 796d45df..43c7e105 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -707,15 +707,17 @@ struct RTLIL::SigChunk
struct RTLIL::SigBit
{
RTLIL::Wire *wire;
- RTLIL::State data;
- int offset;
-
- SigBit() : wire(NULL), data(RTLIL::State::S0), offset(0) { }
- SigBit(RTLIL::State bit) : wire(NULL), data(bit), offset(0) { }
- SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { log_assert(wire && wire->width == 1); }
- SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { log_assert(wire); }
- SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { log_assert(chunk.width == 1); }
- SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[index]), offset(chunk.wire ? chunk.offset + index : 0) { }
+ union {
+ RTLIL::State data;
+ int offset;
+ };
+
+ SigBit() : wire(NULL), data(RTLIL::State::S0) { }
+ SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
+ SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0) { log_assert(wire && wire->width == 1); }
+ SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); }
+ SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { if (wire) offset = chunk.offset; else data = chunk.data.bits[0]; log_assert(chunk.width == 1); }
+ SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data.bits[index]; }
SigBit(const RTLIL::SigSpec &sig);
bool operator <(const RTLIL::SigBit &other) const {