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authorClifford Wolf <clifford@clifford.at>2014-07-22 23:49:26 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-22 23:49:26 +0200
commit9e94f41b89bca54f8a3ce2e8e54c0467a7e8c43d (patch)
treeeab29f4418d6e2ebb1fc37821c9338e3a68b110e
parent4a6d234ec7acff085e3c923d3872d0863c766ad1 (diff)
SigSpec refactoring: Added RTLIL::SigSpecIterator
-rw-r--r--kernel/rtlil.h34
1 files changed, 28 insertions, 6 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index da3a2661..53770088 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -69,6 +69,7 @@ namespace RTLIL
struct Cell;
struct SigChunk;
struct SigBit;
+ struct SigSpecIterator;
struct SigSpec;
struct CaseRule;
struct SwitchRule;
@@ -494,6 +495,14 @@ struct RTLIL::SigBit {
}
};
+struct RTLIL::SigSpecIterator {
+ RTLIL::SigSpec *sig_p;
+ int index;
+ inline RTLIL::SigBit &operator*() const;
+ inline bool operator!=(const RTLIL::SigSpecIterator &other) { return index != other.index; }
+ inline void operator++() { index++; }
+};
+
struct RTLIL::SigSpec {
private:
std::vector<RTLIL::SigChunk> chunks_; // LSB at index 0
@@ -504,6 +513,11 @@ private:
void unpack() const;
bool packed() const;
+ inline void inline_unpack() const {
+ if (!chunks_.empty())
+ unpack();
+ }
+
public:
SigSpec();
SigSpec(const RTLIL::Const &data);
@@ -513,17 +527,21 @@ public:
SigSpec(int val, int width = 32);
SigSpec(RTLIL::State bit, int width = 1);
SigSpec(RTLIL::SigBit bit, int width = 1);
+ SigSpec(std::vector<RTLIL::SigChunk> chunks);
SigSpec(std::vector<RTLIL::SigBit> bits);
SigSpec(std::set<RTLIL::SigBit> bits);
- std::vector<RTLIL::SigChunk> &chunks_rw() { pack(); return chunks_; }
- const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }
- const std::vector<RTLIL::SigBit> &bits() const { unpack(); return bits_; }
+ inline std::vector<RTLIL::SigChunk> &chunks_rw() { pack(); return chunks_; }
+ inline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }
+ inline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }
- int size() const { return width_; }
+ inline int size() const { return width_; }
- RTLIL::SigBit &operator[](int index) { unpack(); return bits_.at(index); }
- const RTLIL::SigBit &operator[](int index) const { unpack(); return bits_.at(index); }
+ inline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }
+ inline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }
+
+ inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }
+ inline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; }
void expand();
void optimize();
@@ -582,6 +600,10 @@ public:
void check() const;
};
+inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const {
+ return (*sig_p)[index];
+}
+
inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
assert(sig.size() == 1 && sig.chunks().size() == 1);
*this = SigBit(sig.chunks()[0]);