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authorClifford Wolf <clifford@clifford.at>2013-03-19 13:33:33 +0100
committerClifford Wolf <clifford@clifford.at>2013-03-19 13:33:33 +0100
commit9f10acb84042ce0943c3b4d1234efa3899f0dff1 (patch)
tree0093dadd88b796f71361599402bccbfc4c8024de
parentd8a7fa6b6771245b99af41783cbb3b8c0a12946a (diff)
added optimizations for single-bit $eq/$ne with constant input to opt_const
-rw-r--r--passes/opt/opt_const.cc25
1 files changed, 25 insertions, 0 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index aa376ae0..0effd964 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -174,6 +174,31 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module)
}
}
+ if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 &&
+ cell->parameters["\\A_WIDTH"].as_int() == 1 && cell->parameters["\\B_WIDTH"].as_int() == 1)
+ {
+ RTLIL::SigSpec a = assign_map(cell->connections["\\A"]);
+ RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
+
+ if (a.is_fully_const()) {
+ RTLIL::SigSpec tmp = a;
+ a = b, b = tmp;
+ }
+
+ if (b.is_fully_const()) {
+ if (b.as_bool() == (cell->type == "$eq")) {
+ RTLIL::SigSpec input = b;
+ ACTION_DO("\\Y", cell->connections["\\A"]);
+ } else {
+ cell->type = "$not";
+ cell->parameters.erase("\\B_WIDTH");
+ cell->parameters.erase("\\B_SIGNED");
+ cell->connections.erase("\\B");
+ }
+ goto next_cell;
+ }
+ }
+
#define FOLD_1ARG_CELL(_t) \
if (cell->type == "$" #_t) { \
RTLIL::SigSpec a = cell->connections["\\A"]; \