diff options
authorClifford Wolf <>2014-01-27 20:42:35 +0100
committerClifford Wolf <>2014-01-27 20:42:35 +0100
commita3ac6b6f4715413aed2ed9ed499bd233563cfbfe (patch)
parentfb4c3dff331f617bb04d2d07a47a0168d3ec2967 (diff)
Progress on presentation
2 files changed, 79 insertions, 5 deletions
diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex
index c14e055e..e243da88 100644
--- a/manual/PRESENTATION_Intro.tex
+++ b/manual/PRESENTATION_Intro.tex
@@ -7,7 +7,7 @@
\subsection{Representations of (digital) Circuits}
\item Graphical
@@ -23,10 +23,61 @@
- \only<1>{Schematic Diagrams are ...}
- \only<2>{Physical Layouts are ...}
- \only<3>{Netlists are ...}
- \only<4>{Hardware Description Languages are ...}
+ \only<1>{Schematic Diagrams are ... TBD}
+ \only<2>{Physical Layouts are ... TBD}
+ \only<3>{Netlists are ... TBD}
+ \only<4>{Hardware Description Languages are ... TBD}
+\subsection{Levels of Abstraction for Digital Circuits}
+ \item \alert<1>{System Level}
+ \item \alert<2>{High Level}
+ \item \alert<3>{Behavioral Level}
+ \item \alert<4>{Register-Transfer Level (RTL)}
+ \item \alert<5>{Logical Gate Level}
+ \item \alert<6>{Physical Gate Level}
+ \item \alert<7>{Switch Level}
+\only<1>{System Level}%
+\only<2>{High Level}%
+\only<3>{Behavioral Level}%
+\only<4>{Register-Transfer Level (RTL)}%
+\only<5>{Logical Gate Level}%
+\only<6>{Physical Gate Level}%
+\only<7>{Switch Level}}
+ Overall view of the circuit: E.g. block-diagrams or instruction-set architecture descriptions
+ Functional implementation of circuit in high-level programming language (C, C++, SystemC, Matlab, Python, etc.).
+ Cycle-accurate description of circuit in hardware description language (Verilog, VHDL, etc.).
+ List of registers (flip-flops) and logic functions that calculate the next state from the previous one. Usually
+ a netlist utilizing high-level cells such as adders, multiplieres, multiplexer, etc.
+ Netlist of single-bit registers and basic logic gates (such as AND, OR,
+ NOT, etc.). Popular form: And-Inverter-Graphs (AIGs) with pairs of primary
+ inputs and outputs for each register bit.
+ Netlist of cells that actually are available on the target architecture
+ (such as CMOS gates in an ASCI or LUTs in an FPGA). Optimized for
+ area and/or and/or speed (static timing or number of logic levels).
+ Netlist of individual transistors.
diff --git a/manual/presentation.tex b/manual/presentation.tex
index 893c6683..bd1e7c6a 100644
--- a/manual/presentation.tex
+++ b/manual/presentation.tex
@@ -2,15 +2,38 @@
\title{Yosys Open SYnthesis Suite}
\author{Clifford Wolf}
+\setbeamercolor{block title}{fg=black,bg=YosysGreen!70}
+\setbeamercolor{item projected}{fg=black,bg=YosysGreen}
+Yosys is an Open Source Verilog synthesis tool, and more.
+Outline of this presentation:
+\item Introduction to the field and Yosys
+\item Yosys usage examples (synthesis)
+\item Yosys usage examples (beyond synthesis)
+\item Programming Yosys extensions