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authorClifford Wolf <clifford@clifford.at>2015-11-24 12:16:19 +0100
committerClifford Wolf <clifford@clifford.at>2015-11-24 12:16:19 +0100
commitab2d8e5c8cc78eb60f380fbdf5b09f2401ce27f6 (patch)
treebe7439f45aef836bdf9362809ee7aae9c47ab4e4
parent8ff229a3ead38f89b0dddde9d952c8677d89f980 (diff)
Added PRIM_DLATCHRS support to verific front-end
-rw-r--r--frontends/verific/verific.cc10
1 files changed, 10 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index e40f24cb..45cd4f3f 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -314,6 +314,16 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
return true;
}
+ if (inst->Type() == PRIM_DLATCHRS)
+ {
+ if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd())
+ module->addDlatch(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetControl()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()));
+ else
+ module->addDlatchsr(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetControl()), net_map.at(inst->GetSet()), net_map.at(inst->GetReset()),
+ net_map.at(inst->GetInput()), net_map.at(inst->GetOutput()));
+ return true;
+ }
+
#define IN operatorInput(inst, net_map)
#define IN1 operatorInput1(inst, net_map)
#define IN2 operatorInput2(inst, net_map)