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authorClifford Wolf <clifford@clifford.at>2015-08-16 09:50:17 +0200
committerClifford Wolf <clifford@clifford.at>2015-08-16 09:50:17 +0200
commitae09c89f626d48bb2fa274903a220d32170b033e (patch)
treeb50a8e4f6b7e54fe8eac2a3f54c6f0e36461fd50
parentb659ffb4571a07db7df7c102790f850f003c9066 (diff)
Fixed opt_clean handling of inout ports
-rw-r--r--passes/opt/opt_clean.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index e6de9d3c..49615d9d 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -90,7 +90,7 @@ void rmunused_module_cells(Module *module, bool verbose)
for (auto &it : module->cells_) {
Cell *cell = it.second;
for (auto &it2 : cell->connections()) {
- if (!ct_all.cell_input(cell->type, it2.first))
+ if (!ct_all.cell_known(cell->type) || ct_all.cell_output(cell->type, it2.first))
for (auto bit : sigmap(it2.second))
if (bit.wire != nullptr)
wire2driver[bit].insert(cell);
@@ -115,7 +115,7 @@ void rmunused_module_cells(Module *module, bool verbose)
pool<SigBit> bits;
for (auto cell : queue)
for (auto &it : cell->connections())
- if (!ct_all.cell_output(cell->type, it.first))
+ if (!ct_all.cell_known(cell->type) || ct_all.cell_input(cell->type, it.first))
for (auto bit : sigmap(it.second))
bits.insert(bit);