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authorClifford Wolf <clifford@clifford.at>2013-11-24 17:55:46 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-24 17:55:46 +0100
commitae798d3fd5dc6bdd82083cce3994f449b829995e (patch)
treea70e38ef82a4f544e1c07046132dc61bb426cad1
parent41205afc39ae83881d82738765da148370eb5f4d (diff)
Fixed xilinx/example_sim_counter test bench
-rw-r--r--techlibs/xilinx/example_sim_counter/run_sim.sh2
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/example_sim_counter/run_sim.sh b/techlibs/xilinx/example_sim_counter/run_sim.sh
index e26d00db..b8354c00 100644
--- a/techlibs/xilinx/example_sim_counter/run_sim.sh
+++ b/techlibs/xilinx/example_sim_counter/run_sim.sh
@@ -8,7 +8,7 @@ XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE
iverilog -o testbench_gold counter_tb.v counter.v
iverilog -o testbench_gate counter_tb.v testbench_synth.v \
- $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v
+ $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6,BUFGP,IBUF}}.v
./testbench_gold > testbench_gold.txt
./testbench_gate > testbench_gate.txt