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authorClifford Wolf <clifford@clifford.at>2014-02-17 09:44:39 +0100
committerClifford Wolf <clifford@clifford.at>2014-02-17 09:44:39 +0100
commitca53ef50982d84917a4f6d293dd0d07805bb8eb6 (patch)
tree1de5fdc1451d1e6711a133d764a5bfb7a0df2c64
parent37cbb1ca60b03cbaaef5041db5f631b90a303f9a (diff)
Better preserve wires when flattening (in comparison to techmap)
-rw-r--r--passes/techmap/techmap.cc24
1 files changed, 12 insertions, 12 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index f0d1e6da..53164b58 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -151,18 +151,18 @@ struct TechmapWorker
if (c.second.width < c.first.width)
c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.width - c.second.width));
assert(c.first.width == c.second.width);
-#if 0
- // more conservative approach:
- // connect internal and external wires
- module->connections.push_back(c);
-#else
- // approach that yields nicer outputs:
- // replace internal wires that are connected to external wires
- if (w->port_output)
- port_signal_map.add(c.second, c.first);
- else
- port_signal_map.add(c.first, c.second);
-#endif
+ if (flatten_mode) {
+ // more conservative approach:
+ // connect internal and external wires
+ module->connections.push_back(c);
+ } else {
+ // approach that yields nicer outputs:
+ // replace internal wires that are connected to external wires
+ if (w->port_output)
+ port_signal_map.add(c.second, c.first);
+ else
+ port_signal_map.add(c.first, c.second);
+ }
}
for (auto &it : tpl->cells) {