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authorClifford Wolf <clifford@clifford.at>2014-08-27 19:44:12 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-27 19:44:12 +0200
commitd148b0af0d5d1a039b13b9e610859a2e55da945e (patch)
tree9db15b60842f32b13b96bc1e0f7633325590a8dd
parentcfb43383198aeb59e461bc0565a9a178d2ae6f01 (diff)
Fixed inserting of Q-inverters in dfflibmap
-rw-r--r--passes/techmap/dfflibmap.cc5
1 files changed, 5 insertions, 0 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 7e39040c..07993b86 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -409,6 +409,11 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
if ('A' <= port.second && port.second <= 'Z') {
sig = cell_connections[std::string("\\") + port.second];
} else
+ if (port.second == 'q') {
+ RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
+ sig = module->addWire(NEW_ID, SIZE(old_sig));
+ module->addNotGate(NEW_ID, sig, old_sig);
+ } else
if ('a' <= port.second && port.second <= 'z') {
sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
sig = module->NotGate(NEW_ID, sig);