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authorClifford Wolf <clifford@clifford.at>2014-09-02 22:49:24 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-02 22:49:24 +0200
commitda360771a193707b59eac9b95b3bfe1652a057aa (patch)
tree8f09645fbab743bfe8b0246584d29b007f674a70
parentc38283dbd033ba95554600bbaa850de707ab2a78 (diff)
Create a default selection stack in RTLIL::Design::Design()
-rw-r--r--kernel/rtlil.cc1
-rw-r--r--kernel/yosys.cc2
2 files changed, 1 insertions, 2 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index f237f57e..35cd54b4 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -228,6 +228,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
RTLIL::Design::Design()
{
refcount_modules_ = 0;
+ selection_stack.push_back(RTLIL::Selection());
}
RTLIL::Design::~Design()
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 7b8173b6..0ecb4cda 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -74,9 +74,7 @@ int SIZE(RTLIL::Wire *wire)
void yosys_setup()
{
Pass::init_register();
-
yosys_design = new RTLIL::Design;
- yosys_design->selection_stack.push_back(RTLIL::Selection());
log_push();
}