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authorClifford Wolf <clifford@clifford.at>2015-09-18 20:12:56 +0200
committerClifford Wolf <clifford@clifford.at>2015-09-18 20:12:56 +0200
commitdb548800b6fe7ddfdbc18abd8943b4e7b89b385c (patch)
treeb66ab635b5291983b36097b5c633c299f98789ce
parent745d56149d276f52146e302d59f74ede8d1875ba (diff)
Added buffer detection to "abc -lut"
-rw-r--r--passes/techmap/abc.cc6
1 files changed, 6 insertions, 0 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index d1e629b5..64586927 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1075,6 +1075,12 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
design->select(module, cell);
continue;
}
+ if (c->type == "$lut" && GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
+ SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
+ SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)];
+ module->connect(my_y, my_a);
+ continue;
+ }
RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
cell->parameters = c->parameters;