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authorClifford Wolf <clifford@clifford.at>2013-04-13 21:19:10 +0200
committerClifford Wolf <clifford@clifford.at>2013-04-13 21:19:10 +0200
commite0c408cb4a9fb411aff087d5c1e8c610d3f5bc3d (patch)
tree034935880a2713f77256c168a8e37cd0382e33bc
parentc6198ea5a833008789ecbc9cc4da3ab61fcf4e82 (diff)
Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values
-rw-r--r--frontends/ast/genrtlil.cc8
-rw-r--r--tests/simple/process.v19
2 files changed, 23 insertions, 4 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 36074be3..cb57bbab 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -337,9 +337,9 @@ struct AST_INTERNAL::ProcessGenerator
reg.sort_and_unify();
}
- // remove all assignments to the given signal pattern in a case and all its children
- // when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
- // function is acalled to clean up the first two assignments as they are overwritten by
+ // remove all assignments to the given signal pattern in a case and all its children.
+ // e.g. when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
+ // function is called to clean up the first two assignments as they are overwritten by
// the third assignment.
void removeSignalFromCaseTree(RTLIL::SigSpec pattern, RTLIL::CaseRule *cs)
{
@@ -461,7 +461,7 @@ struct AST_INTERNAL::ProcessGenerator
} else if (node->type == AST_BLOCK) {
processAst(node);
} else if (!generated_default_case)
- current_case->compare.push_back(node->genWidthRTLIL(sw->signal.width));
+ current_case->compare.push_back(node->genWidthRTLIL(sw->signal.width, &subst_rvalue_from, &subst_rvalue_to));
}
sw->cases.push_back(current_case);
current_case = backup_case;
diff --git a/tests/simple/process.v b/tests/simple/process.v
index 53258664..8cb4c870 100644
--- a/tests/simple/process.v
+++ b/tests/simple/process.v
@@ -1,4 +1,23 @@
+module blocking_cond (in, out);
+
+input in;
+output reg out;
+reg tmp;
+
+always @* begin
+ tmp = 1;
+ out = 1'b0;
+ case (1'b1)
+ tmp: out = in;
+ endcase
+ tmp = 0;
+end
+
+endmodule
+
+// -------------------------------------------------------------
+
module uut(clk, arst, a, b, c, d, e, f, out1);
input clk, arst, a, b, c, d, e, f;