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authorClifford Wolf <clifford@clifford.at>2014-02-16 17:56:19 +0100
committerClifford Wolf <clifford@clifford.at>2014-02-16 17:56:19 +0100
commitf08c71b96c325f2432abb4f95fd823ae243e003b (patch)
treead428898a6d96273014239a63bec4da8af89214d
parent42ce3db983fdb512e181daab1817991a661066ff (diff)
Progress in presentation
-rw-r--r--manual/PRESENTATION_ExAdv.tex41
-rw-r--r--manual/PRESENTATION_ExAdv/Makefile5
-rw-r--r--manual/PRESENTATION_ExAdv/mymul_map.v15
-rw-r--r--manual/PRESENTATION_ExAdv/mymul_test.v4
-rw-r--r--manual/PRESENTATION_ExAdv/mymul_test.ys15
5 files changed, 79 insertions, 1 deletions
diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex
index 4ef10d7a..cf36d32c 100644
--- a/manual/PRESENTATION_ExAdv.tex
+++ b/manual/PRESENTATION_ExAdv.tex
@@ -320,6 +320,47 @@ is non-zero then the module is disabled for this set of parameters.
\end{columns}
\end{frame}
+\subsubsection{Scripting in map modules}
+
+\begin{frame}{\subsubsecname}
+\begin{itemize}
+\item The special wires {\tt \_TECHMAP\_DO\_*} can be used to run Yosys scripts
+in the context of the replacement module.
+\medskip
+\item The wire that comes first in alphatecial oder is interprated as string (must
+be connected to constants) that is executed as script. Then the wire is removed. Repeat.
+\medskip
+\item You can even call techmap recursively!
+\medskip
+\item Example use-cases:
+\begin{itemize}
+\item Using always blocks in map module: call {\tt proc}
+\item Perform expensive optimizations (such as {\tt freduce}) on cells where
+this is known to work well.
+\item Interacting with custom commands.
+\end{itemize}
+\end{itemize}
+\end{frame}
+
+\begin{frame}[t]{\subsubsecname{} -- Example}
+\vbox to 0cm{
+\vskip4.2cm
+\hskip0.5cm\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/mymul.pdf}
+\vss
+}
+\vskip-0.6cm
+\begin{columns}
+\column[t]{6cm}
+\vskip-0.6cm
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/mymul_map.v}
+\column[t]{4.2cm}
+\vskip-0.6cm
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/mymul_test.v}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/mymul_test.ys}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, frame=single, language=ys, firstline=7, lastline=12]{PRESENTATION_ExAdv/mymul_test.ys}
+\end{columns}
+\end{frame}
+
\subsubsection{TBD}
\begin{frame}{\subsubsecname}
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 4ee5886d..74f26327 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,5 +1,5 @@
-all: select_01.pdf red_or3x1.pdf sym_mul.pdf
+all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf
select_01.pdf: select_01.v select_01.ys
../../yosys select_01.ys
@@ -10,3 +10,6 @@ red_or3x1.pdf: red_or3x1_*
sym_mul.pdf: sym_mul_*
../../yosys sym_mul_test.ys
+mymul.pdf: mymul_*
+ ../../yosys mymul_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/mymul_map.v b/manual/PRESENTATION_ExAdv/mymul_map.v
new file mode 100644
index 00000000..e888a7a7
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mymul_map.v
@@ -0,0 +1,15 @@
+module MYMUL(A, B, Y);
+ parameter WIDTH = 1;
+ input [WIDTH-1:0] A, B;
+ output reg [WIDTH-1:0] Y;
+
+ wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+ integer i;
+ always @* begin
+ Y = 0;
+ for (i = 0; i < WIDTH; i=i+1)
+ if (A[i])
+ Y = Y + (B << i);
+ end
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/mymul_test.v b/manual/PRESENTATION_ExAdv/mymul_test.v
new file mode 100644
index 00000000..620a06d9
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mymul_test.v
@@ -0,0 +1,4 @@
+module test(A, B, Y);
+ input [1:0] A, B;
+ output [1:0] Y = A * B;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/mymul_test.ys b/manual/PRESENTATION_ExAdv/mymul_test.ys
new file mode 100644
index 00000000..48203e31
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/mymul_test.ys
@@ -0,0 +1,15 @@
+read_verilog mymul_test.v
+hierarchy -check -top test
+
+techmap -map sym_mul_map.v \
+ -map mymul_map.v;;
+
+rename test test_mapped
+read_verilog mymul_test.v
+miter -equiv test test_mapped miter
+flatten miter
+
+sat -verify -prove trigger 0 miter
+
+splitnets -ports test_mapped/A
+show -prefix mymul -format pdf -notitle test_mapped